Patents by Inventor Wen Tseng

Wen Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11686625
    Abstract: A method for measuring temperature is used to obtain a room temperature of a room. The method for measuring temperature includes: obtaining a first temperature inside an operating area in a portable electronic device in the room; obtaining a second temperature outside the operating area in the portable electronic device by a first temperature sensor; calculating a temperature difference between the first temperature and the second temperature; obtaining a compensation temperature according to the temperature difference and a compensation temperature table; and calculating the room temperature according to the second temperature and the compensation temperature.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: June 27, 2023
    Assignee: AmTRAN Technology Co., Ltd.
    Inventors: Chiung-Wen Tseng, Yi-Xuan Huang, Yu-An Hsu
  • Patent number: 11672181
    Abstract: A semiconductor device includes a magnetic random access memory (MRAM). The MRAM comprises a plurality of MRAM cells including a first type MRAM cell and a second type MRAM cell. Each of the plurality of MRAM cells includes a magnetic tunneling junction (MTJ) layer including a pinned magnetic layer, a tunneling barrier layer and a free magnetic layer. A size of the MTJ film stack of the first type MRAM cell is different from a size of the MTJ film stack of the second type MRAM cell. In one or more of the foregoing and following embodiments, a width of the MTJ film stack of the first type MRAM cell is different from a width of the MTJ film stack of the second type MRAM cell.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: June 6, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Huang-Wen Tseng, Cheng-Chou Wu, Che-Jui Chang
  • Patent number: 11670689
    Abstract: A method for eliminating divot formation includes forming an isolation layer; forming a conduction layer which has an upper inclined boundary with the isolation layer such that the conduction layer has a portion located above a portion of the isolation layer at the upper inclined boundary; etching back the isolation layer; and etching back the conduction layer after etching back the isolation layer such that a top surface of the etched conduction layer is located at a level lower than a top surface of the etched isolation layer.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: June 6, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Wen Tseng, Po-Wei Liu, Hung-Ling Shih, Tsung-Yu Yang, Tsung-Hua Yang, Yu-Chun Chang
  • Publication number: 20230124003
    Abstract: A conference system, including a remote device and a local device, is disclosed. The remote device includes a voice broadcasting element. The local device includes several image capture elements and a processor. When the remote device is communicatively connected through an internet to the local device, several image capture elements obtain a number of people present in a local environment of the local device. The processor, coupled to several image capture elements, generates a voice message according to the number of people present, and the processor transmits the voice message to the remote device, so that the voice broadcasting element of the remote device plays the voice message.
    Type: Application
    Filed: July 5, 2022
    Publication date: April 20, 2023
    Inventors: Chiung Wen TSENG, Yu Ruei LEE, I Jui YU
  • Patent number: 11626343
    Abstract: A method includes forming a solder layer on a surface of one or more chips. A lid is positioned over the solder layer on each of the one or more chips. Heat and pressure are applied to melt the solder layer and attach each lid to a corresponding solder layer. The solder layer has a thermal conductivity of ?50 W/mK.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: April 11, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yang-Che Chen, Chen-Hua Lin, Huang-Wen Tseng, Victor Chiang Liang, Chwen-Ming Liu
  • Publication number: 20230064152
    Abstract: A semiconductor device and a method for detecting a defect in a semiconductor device are provided. The semiconductor device includes a packaging structure. The packaging structure includes a redistribution layer and a detecting component disposed in the redistribution layer. The semiconductor device further includes a cooling plate over the packaging structure and a fixing component penetrating through the packaging structure and the cooling plate. The packaging structure and the cooling plate are fixed by the fixing component. The detecting component is in a chain configuration having a ring shaped structure circling around the fixing component.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Inventors: YANG-CHE CHEN, CHEN-HUA LIN, VICTOR CHIANG LIANG, HUANG-WEN TSENG, CHWEN-MING LIU
  • Patent number: 11574918
    Abstract: A non-volatile memory (NVM) cell includes a semiconductor wire including a select gate portion and a control gate portion. The NVM cell includes a select transistor formed with the select gate portion and a control transistor formed with the control gate portion. The select transistor includes a gate dielectric layer disposed around the select gate portion and a select gate electrode disposed on the gate dielectric layer. The control transistor includes a stacked dielectric layer disposed around the control gate portion, a gate dielectric layer disposed on the stacked dielectric layer and a control gate electrode disposed on the gate dielectric layer. The stacked dielectric layer includes a first silicon oxide layer disposed on the control gate portion, a charge trapping layer disposed on the first silicon oxide, and a second silicon oxide layer disposed on the charge trapping layer.
    Type: Grant
    Filed: June 7, 2021
    Date of Patent: February 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yun-Chi Wu, Yu-Wen Tseng
  • Publication number: 20220406705
    Abstract: A semiconductor package structure and method of manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a connection layer formed on a metal base layer, at least one die unit formed on the connection layer, a metal pillar connecting the metal base layer and surrounding the die unit, and an interconnect structure overlaid onto the die unit and the metal pillar. Each die unit comprises at least one die attached onto the connection layer and surrounded by a molding structure. The interconnect structure includes a first interconnect layer overlaid onto the die unit and the metal pillar and a second interconnect layer formed on the first interconnect layer. The first and second interconnect layers comprise first and second metal layers being parallel with the top surface of the die unit. A projection of the metal layers overlaps an upper surface of the die.
    Type: Application
    Filed: June 18, 2021
    Publication date: December 22, 2022
    Inventors: YANG-CHE CHEN, CHEN-HUA LIN, VICTOR CHIANG LIANG, HUANG-WEN TSENG, CHWEN-MING LIU
  • Publication number: 20220406652
    Abstract: A semiconductor isolation structure includes a silicon-on-insulator wafer, a first deep trench isolation structure and a second deep trench isolation structure. The silicon-on-insulator wafer includes a semiconductor substrate, a buried insulation layer disposed on the semiconductor substrate, and a semiconductor layer disposed on the buried insulation layer. The semiconductor layer has a functional region. The first deep trench isolation structure penetrates the semiconductor layer and the buried insulation layer, and surrounds the functional region. The second deep trench isolation structure penetrates semiconductor layer and the buried insulation layer, and surrounds the first deep trench isolation structure.
    Type: Application
    Filed: June 17, 2021
    Publication date: December 22, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Yu YANG, Po-Wei LIU, Yun-Chi WU, Yu-Wen TSENG, Chia-Ta HSIEH, Ping-Cheng LI, Tsung-Hua YANG, Yu-Chun CHANG
  • Publication number: 20220384281
    Abstract: A semiconductor package includes a semiconductor chip disposed over a first main surface of a first substrate, a package lid disposed over the semiconductor chip, and spacers extending from the package lid through corresponding holes in the first substrate. The spacers enter the holes at a first main surface of the first substrate and extend beyond an opposing second main surface of the first substrate.
    Type: Application
    Filed: August 10, 2022
    Publication date: December 1, 2022
    Inventors: Yang-Che CHEN, Chen-Hua LIN, Huang-Wen TSENG, Victor Chiang LIANG, Chwen-Ming LIU
  • Publication number: 20220376034
    Abstract: A semiconductor package structure includes a magnetic core, a molding surrounding the magnetic core, a first RDL under the magnetic core, a second RDL over the magnetic core, and a plurality of through vi as in the molding. The magnetic core has a first core surface and a second core surface opposite to the first core surface, The molding has a first molding surface and a second molding surface opposite to the first molding surface. The first molding surface is substantially aligned with the first core surface, and the second molding surface is substantially aligned with the second core surface. The first RDL includes a plurality of first conductive lines. The second RDL includes a plurality of second conductive lines. The through vias are coupled to the first conductive lines and the second conductive lines to form a coil surrounding the magnetic core.
    Type: Application
    Filed: May 14, 2021
    Publication date: November 24, 2022
    Inventors: YANG-CHE CHEN, CHEN-HUA LIN, VICTOR CHIANG LIANG, HUANG-WEN TSENG, CHWEN-MING LIU
  • Publication number: 20220375881
    Abstract: A semiconductor package includes a multilayer substrate, a device die, an insulating encapsulant, and a shielding structure. The multilayer substrate has a first surface and a second surface opposite to the first surface. The multilayer substrate includes through holes, and each of the through holes extends from the first surface to the second surface. The device die is disposed on the first surface of the multilayer substrate. The insulating encapsulant is disposed on the first surface of the multilayered substrate and encapsulating the device die. The shielding structure is disposed over the first surface of the multilayer substrate. The shielding structure includes a cover body and conductive pillars. The cover body covers the device die and the insulating encapsulant. The conductive pillars are connected to the cover body and fitted into the through holes of the multilayer substrate.
    Type: Application
    Filed: August 5, 2022
    Publication date: November 24, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yang-Che Chen, Victor Chiang Liang, Chen-Hua Lin, Chwen-Ming Liu, Huang-Wen Tseng
  • Publication number: 20220375486
    Abstract: An audio processing method includes the following steps of capturing audio data by a microphone array to compute frequency array data of the audio data; computing a power sequence of degrees by using the frequency array data; and computing a difference value between a maximum value of the power sequence of degrees and a minimum value of the power sequence of degrees to determine whether the degree corresponding to the maximum value is a source degree relative to the microphone array.
    Type: Application
    Filed: January 12, 2022
    Publication date: November 24, 2022
    Inventors: Chiung Wen TSENG, Yu Ruei LI, I Jui YU
  • Publication number: 20220367318
    Abstract: A method includes forming a solder layer on a surface of one or more chips. A lid is positioned over the solder layer on each of the one or more chips. Heat and pressure are applied to melt the solder layer and attach each lid to a corresponding solder layer. The solder layer has a thermal conductivity of ?50 W/mK.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 17, 2022
    Inventors: Yang-Che CHEN, Chen-Hua LIN, Huang-Wen TSENG, Victor Chiang LIANG, Chwen-Ming LIU
  • Publication number: 20220367494
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a silicide-containing field effect transistor disposed in a periphery region and a floating gate non-volatile memory device disposed in a memory region. The floating gate non-volatile memory device is free of silicide. The floating gate non-volatile memory device includes a second source, a third source, a fourth source, a second drain, and a third drain. The floating gate non-volatile memory device also includes a first floating gate electrode associated with the second source, the second drain, and the third source, and a second floating gate electrode associated with the second source, the third drain, and the fourth source. The second source is disposed between the first and second floating gate electrodes with a constant width. Each of the third source and the fourth source has a width larger than the constant width of the second source.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 17, 2022
    Inventors: Felix Ying-Kit Tsui, Huang-Wen Tseng
  • Publication number: 20220355094
    Abstract: The present disclosure describes a flow reversing valve, along with associated methods and systems for providing forward flow, reverse flow, and bypass flow modes of operation, and integrating them into patient treatment systems, including those used for treating and inducing hyperthermia.
    Type: Application
    Filed: September 1, 2020
    Publication date: November 10, 2022
    Inventors: John Joseph Landy, III, Alexander Rick, Tristan Dion, Skylar Nesheim, David Dumais, Yeu Wen Tseng, Chuong Vu
  • Publication number: 20220359671
    Abstract: A method for eliminating divot formation includes forming an isolation layer; forming a conduction layer which has an upper inclined boundary with the isolation layer such that the conduction layer has a portion located above a portion of the isolation layer at the upper inclined boundary; etching back the isolation layer; and etching back the conduction layer after etching back the isolation layer such that a top surface of the etched conduction layer is located at a level lower than a top surface of the etched isolation layer.
    Type: Application
    Filed: September 10, 2021
    Publication date: November 10, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Wen TSENG, Po-Wei LIU, Hung-Ling SHIH, Tsung-Yu YANG, Tsung-Hua YANG, Yu-Chun CHANG
  • Patent number: 11482461
    Abstract: A semiconductor package includes a semiconductor chip disposed over a first main surface of a first substrate, a package lid disposed over the semiconductor chip, and spacers extending from the package lid through corresponding holes in the first substrate. The spacers enter the holes at a first main surface of the first substrate and extend beyond an opposing second main surface of the first substrate.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: October 25, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yang-Che Chen, Chen-Hua Lin, Huang-Wen Tseng, Victor Chiang Liang, Chwen-Ming Liu
  • Patent number: 11450626
    Abstract: A semiconductor package includes a multilayer substrate, a device die, an insulating encapsulant, and a shielding structure. The multilayer substrate has a first surface and a second surface opposite to the first surface. The multilayer substrate includes through holes, and each of the through holes extends from the first surface to the second surface. The device die is disposed on the first surface of the multilayer substrate. The insulating encapsulant is disposed on the first surface of the multilayered substrate and encapsulating the device die. The shielding structure is disposed over the first surface of the multilayer substrate. The shielding structure includes a cover body and conductive pillars. The cover body covers the device die and the insulating encapsulant. The conductive pillars are connected to the cover body and fitted into the through holes of the multilayer substrate.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: September 20, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yang-Che Chen, Victor Chiang Liang, Chen-Hua Lin, Chwen-Ming Liu, Huang-Wen Tseng
  • Patent number: 11417670
    Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a substrate; a field effect transistor disposed in a periphery region of the substrate, the field effect transistor including a gate electrode, a first source, a first drain; a floating gate non-volatile memory device disposed in a memory region of the substrate, the floating gate non-volatile memory device including a second source, a third source, and a second drain, wherein the second source, the third source, and the second drain are disposed along an axis; and a floating gate electrode in the memory region including a first portion, a second portion, and a third portion, wherein the first portion, the second portion, and the third portion are electrically connected, wherein the first portion, the second portion and the third portion extend perpendicular to the axis.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: August 16, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Felix Ying-Kit Tsui, Huang-Wen Tseng