Abstract: Provided is an integrated fan-out package including a die, an insulating encapsulation, a redistribution circuit structure, a conductive terminal, and a barrier layer. The die is encapsulated by the insulating encapsulation. The redistribution circuit structure includes a redistribution conductive layer. The redistribution conductive layer is disposed in the insulating encapsulation and extending from a first surface of the insulating encapsulation to a second surface of the insulating encapsulation. The conductive terminal is disposed over the second surface of the insulating encapsulation. The barrier layer is sandwiched between the redistribution conductive layer and the conductive terminal. A material of the barrier layer is different from a material of the redistribution conductive layer and a material of the conductive terminal. A method of fabricating the integrated fan-out package is also provided.

Abstract: A dispatching method and system based on multiple levels of steady state production rate in working benches are provided. The dispatching method includes the following steps: receiving a plurality of real-time streaming data regarding a plurality of products being produced by a plurality of productive working benches; grouping the production rate values comprised in each real-time streaming data according to a first data binning technique, so as to produce a first steady state production rate value corresponding to each real-time streaming data; grouping the production rate values comprised in each real-time streaming data according to a second data binning technique, so as to produce a second steady state production rate value corresponding to each real-time streaming data; and determining a dispatching message of a to-be-produced product according to a portion of the first steady state production rate values and a portion of the second steady state production rate values.

Abstract: A method for screening bad columns applicable to a data storage medium is disclosed. The method for screening bad columns includes steps of: reading out written data of at least one of the data pages of at least one of the data blocks; comparing the written data with predetermined data to obtain a number of error bits in each of the columns in each of the segments in the at least one of the data pages, and accordingly calculating a total number of error bits in each of the segments; determining a segment having a largest total number of error bits from the segments, and determining and recording a column having a largest number of error bits from the segment having the largest total number of error bits as a bad column. A data storage device saving a bad column summary table is also disclosed.

Abstract: A via or pillar structure, and a method of forming, is provided. In an embodiment, a polymer layer is formed having openings exposing portions of an underlying conductive pad. A conductive layer is formed over the polymer layer, filling the openings. The dies are covered with a molding material and a planarization process is performed to form pillars in the openings. In another embodiment, pillars are formed and then a polymer layer is formed over the pillars. The dies are covered with a molding material and a planarization process is performed to expose the pillars. In yet another embodiment, pillars are formed and a molding material is formed directly over the pillars. A planarization process is performed to expose the pillars. In still yet another embodiment, bumps are formed and a molding material is formed directly over the bumps. A planarization process is performed to expose the bumps.

Abstract: A method includes providing a structure that includes a substrate; first and second gate structures over the substrate; first and second source/drain (S/D) features over the substrate; a first dielectric layer over sidewalls of the first and second gate structures and the first and second S/D features; and a second dielectric layer over the first dielectric layer. The first and second S/D features are adjacent to the first and second gate structures respectively. The first and second S/D features comprise different materials. The method further includes etching the first and second dielectric layers to expose the first and second S/D features; doping a p-type dopant to the first and second S/D features; and performing a selective etching process to the first and second S/D features after the doping of the p-type dopant. The selective etching process recesses the first S/D feature faster than it recesses the second S/D feature.

Abstract: A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first metal connect in a first active region and a second metal connect in a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes forming a first opening over the first metal connect, the STI region, and the second metal connect, and forming the third metal connect in the first opening. Forming the third metal connect over the first metal connect and the second metal connect mitigates RC coupling.

Abstract: A microLED display panel includes a substrate being divided into a plurality of sub-regions for supporting microLEDs, and a plurality of drivers being correspondingly disposed on surfaces of the sub-regions respectively. In one embodiment, a top surface of the substrate has a recess for accommodating the driver.

Abstract: An electronic device is provided, including a housing, a channel, and a flexible circuit. The housing includes a frame and a buffer structure connected to the frame by overmolding, wherein the hardness of the frame exceeds that of the buffer structure. The channel is extended along a sidewall of the frame, through the housing and adjacent to the buffer structure. The flexible circuit is disposed through the channel to connect a first circuit unit and a second circuit unit of the electronic device.

Abstract: The present invention is to provide a gel nail photocuring machine with multicolor light effects, comprising: a machine body and a control module. The machine body has a curing cavity and one or a plurality of multicolor indicator light module provided on the machine body to produce color light effects on a housing of the machine body, wherein the multicolor indicator light module has a composite light source and a uniform illumination unit provided on one side of the composite light source. The control module is provided on the machine body and is connected to the multicolor indicator light module on the machine body, wherein the control module provides a color difference control instruction to the multicolor indicator light module according to a preset instruction in order to control an output power of each of a plurality of base-color light-emitting units of the composite light source, thereby instructing the multicolor indicator light module to emit light of various colors.

Abstract: An integrated circuit package and a method of forming the same are provided. A method includes attaching a first side of an integrated circuit die to a carrier. An encapsulant is formed over and around the integrated circuit die. The encapsulant is patterned to form a first opening laterally spaced apart from the integrated circuit die and a second opening over the integrated circuit die. The first opening extends through the encapsulant. The second opening exposes a second side of the integrated circuit die. The first side of the integrated circuit die is opposite the second side of the integrated circuit die. A conductive material is simultaneously deposited in the first opening and the second opening.

Abstract: The present disclosure is directed to a semiconductor structure that includes a semiconductor substrate. A first interconnect layer is disposed over the semiconductor substrate. The first interconnect layer includes a first dielectric material having a conductive body embedded therein. The conductive body includes a first sidewall, a second sidewall, and a bottom surface. A spacer element has a sidewall which contacts the first sidewall of the conductive body and which contacts the bottom surface of the conductive body. A second interconnect layer overlies the first interconnect layer and includes a second dielectric material with at least one via therein. The at least one via is filled with a conductive material which is electrically coupled to the conductive body of the first interconnect layer.

Abstract: Formation methods of a semiconductor device structure are provided. A method includes forming a dielectric layer over a first conductive feature and a second conductive feature. The method also includes depositing a conformal layer in a first via hole and a second via hole in the dielectric layer. The method further includes removing the conformal layer in the second via hole. The dielectric layer remains covered by the conformal layer in the first via hole. In addition, the method includes etching the conformal layer in the first via hole and the dielectric layer until the first conductive feature and the second conductive feature become exposed through the first via hole and the second via hole, respectively. The method also includes forming a third conductive feature in the first via hole and a fourth conductive feature in the second via hole.

Abstract: An integrated fan-out package including an integrated circuit, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit includes an active surface, a plurality of sidewalls connected to the active surface, and a plurality of pads distributed on the active surface. The insulating encapsulation encapsulates the active surface and the sidewalls of the integrated circuit. The insulating encapsulation includes a plurality of first contact openings and a plurality of through holes, and the pads are exposed by the first contact openings. The redistribution circuit structure includes a redistribution conductive layer, wherein the redistribution conductive layer is disposed on the insulating encapsulation and is distributed in the first contact openings and the through holes. The redistribution conductive layer is electrically connected to the pads through the first contact openings. A method of fabricating the integrated fan-out package is also provided.

Abstract: A method of forming an integrated circuit device includes forming a bump structure on a substrate, wherein the bump structure has a top surface and a sidewall surface, and the substrate has a surface region exposed by the bump structure. The method further includes depositing a non-metal protection layer on the top surface and the sidewall surface of the bump structure and the surface region of the substrate. The method further includes removing the non-metal protection layer from the top surface of the bump structure, wherein a remaining portion of the non-metal protection layer forms an L-shaped protection structure, and a top surface of the remaining portion of the non-metal protection layer is farther from the substrate than a top surface of the bump structure.

Abstract: Methods of patterning a target material layer are provided herein. The method includes steps of positioning a semiconductor wafer having the target material layer thereon in an etch chamber and of providing a flow of etch gases into the etch chamber, the flow of etch gases etchant gas comprising a plurality of gases. The semiconductor wafer has a patterned hardmask feature formed from a compound on the target material layer. The method also includes steps of etching the target material layer using the patterned hardmask feature as a mask feature, wherein one of the gases chemically alters the patterned hardmask feature and at least one of the gases chemically repairs the patterned hardmask feature so that the patterned hardmask feature retains its dimensions during the etching. Associated semiconductor wafer are also provided herein.

Abstract: One or more techniques or systems for mitigating pattern collapse are provided herein. For example, a semiconductor structure for mitigating pattern collapse is formed. In some embodiments, the semiconductor structure includes an extreme low-k (ELK) dielectric region associated with a via or a metal line. For example, a first metal line portion and a second metal line portion are associated with a first lateral location and a second lateral location, respectively. In some embodiments, the first portion is formed based on a first stage of patterning and the second portion is formed based on a second stage of patterning. In this manner, pattern collapse associated with the semiconductor structure is mitigated, for example.

Abstract: A foam sealing block is provided for sealing a cable channel by which one or more cables traverse into an air-cooled compartment. The foam sealing block may folded around the cables and positioned within the cable channel. The insertion of the folded foam sealing block prevents the transfer of air from the air-cooled compartment via the cable channel, while still allowing the cables to traverse the cable channel. The top surface of the foam sealing block may formed from offset rows of protrusions, such as hemispherical shaped protrusions. The dimensions and shape of the protrusions may be selected based on the physical characteristics of the cables traversing the cable channel. The bottom surface of the foam sealing block may be formed from a perforated, rigid bracket that allows the foam sealing block to fit securely within the cable channel.

Abstract: A bias circuit for supplying a bias current to a RF power amplifier by using at least two voltage reference circuits coupled between the base terminal of a bipolar transistor and a voltage supply for generating a bias current to the RF power amplifier, wherein each of the at least two voltage reference circuits respectively clamps to a reference voltage at a corresponding terminal node of the voltage reference circuit on a conductive path having a current flowing from the voltage supply to the base terminal of the bipolar transistor, wherein when the current flowing out of the voltage supply increases, the current flowing through each of the at least two voltage reference circuits will also increases, so that the variation range of the bias current to the RF power amplifier will be kept in a smaller range compared with the variation range of the current flowing out of the power supply, thereby increasing the linearity of the RF power amplifier.

Abstract: Methods and systems for detecting properties of sample tubes in a laboratory environment include a drawer vision system that can be trained and calibrated. Images of a tube tray captured by at least one camera are analyzed to extract image patches that allow a processor to automatically determine if a tube slot is occupied, if the tube has a cap, and if the tube has a tube top cup. The processor can be trained using a random forest technique and a plurality of training image patches. Cameras can be calibrated using a three-dimensional calibration target that can be inserted into the drawer.

Abstract: A via or pillar structure, and a method of forming, is provided. In an embodiment, a polymer layer is formed having openings exposing portions of an underlying conductive pad. A conductive layer is formed over the polymer layer, filling the openings. The dies are covered with a molding material and a planarization process is performed to form pillars in the openings. In another embodiment, pillars are formed and then a polymer layer is formed over the pillars. The dies are covered with a molding material and a planarization process is performed to expose the pillars. In yet another embodiment, pillars are formed and a molding material is formed directly over the pillars. A planarization process is performed to expose the pillars. In still yet another embodiment, bumps are formed and a molding material is formed directly over the bumps. A planarization process is performed to expose the bumps.