Abstract: A method includes forming an epitaxial source/drain (S/D) feature over a semiconductor layer, where the epitaxial S/D feature includes silicon (Si) and germanium (Ge), forming a trench to expose a portion of the epitaxial S/D feature, annealing the exposed portion of the epitaxial S/D feature, where the annealing forms at a top surface of the epitaxial S/D feature a first region having a first Ge concentration and a second region disposed below the first region having a second Ge concentration that is less than the first Ge concentration, oxidizing the first region, removing the oxidized first region, and forming an S/D contact in the trench over the second region.

Abstract: A method includes providing a structure having first and second fins over a substrate and oriented lengthwise generally along a first direction and source/drain (S/D) features over the first and second fins; forming an interlayer dielectric (ILD) layer covering the S/D features; performing a first etching process at least to an area between the S/D features, thereby forming a trench in the ILD layer; depositing a dielectric material in the trench; performing a second etching process to selectively recess the dielectric material; and performing a third etching process to selectively recess the ILD layer, thereby forming a contact hole that exposes the S/D features.

Abstract: A method of semiconductor fabrication includes providing a semiconductor structure having a substrate and first, second, third, and fourth fins above the substrate. The method further includes forming an n-type epitaxial source/drain (S/D) feature on the first and second fins, forming a p-type epitaxial S/D feature on the third and fourth fins, and performing a selective etch process on the semiconductor structure to remove upper portions of the n-type epitaxial S/D feature and the p-type epitaxial S/D feature such that more is removed from the n-type epitaxial S/D feature than the p-type epitaxial S/D feature.

Abstract: A compound for inhibiting BMI-1/MCL-1 having a structure of Formula (I), wherein the various groups are as described. A pharmaceutical composition for treating cancer includes an effective amount of a compound of Formula (I).

Abstract: A via or pillar structure, and a method of forming, is provided. In an embodiment, a polymer layer is formed having openings exposing portions of an underlying conductive pad. A conductive layer is formed over the polymer layer, filling the openings. The dies are covered with a molding material and a planarization process is performed to form pillars in the openings. In another embodiment, pillars are formed and then a polymer layer is formed over the pillars. The dies are covered with a molding material and a planarization process is performed to expose the pillars. In yet another embodiment, pillars are formed and a molding material is formed directly over the pillars. A planarization process is performed to expose the pillars. In still yet another embodiment, bumps are formed and a molding material is formed directly over the bumps. A planarization process is performed to expose the bumps.

Abstract: The present invention is related to an UV LED curing apparatus, and more particularly, to an UV LED curing apparatus with improved housing and switch controller. The light reflective inner casing is preferably provided as an effective UV light reflector and as a supporting substrate of the UV LED light source while being capable of transmitting heat from the UV LED light source away for further heat dissipation to the ambient by the outer casing. The outer casing is detachably attached to the inner casing and allows a greater user interaction for decorative and entertainment purposes while also being a protective and heat dissipation means.

Abstract: The present invention relates to a semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure, an insulating stacked structure and a first conductive layer. The gate structure is disposed on the substrate, and the insulating stacked structure covers the gate structure and the substrate to define a first opening thereinto expose a portion of the gate structure and a portion of the substrate. The first conductive layer covers surfaces of the first opening to directly in contact with the portion of the substrate and the portion of the gate structure, with the first conductive layer including two outer extension wings on a top surface of the insulating stacked structure.

Abstract: A real-time communication system includes a cloud server, multiple user devices having respective real-time communication software for communicating with the cloud server, and multiple dynamic expression rendering devices one-to-one communicating with the user devices respectively. A transmitting user device encodes and transmits a transmitter data, a receiver data and a dynamic expression ID of a selected dynamic expression. The cloud server decodes and transmits the transmitter data, the receiver data and the dynamic expression ID of the selected dynamic expression to a receiver user device. Based on the received dynamic expression ID, the real-time communication software of the receiver user device finds the dynamic expression.

Abstract: A method includes aligning a first electrical connector of a first package component to a second electrical connector of a second package component. With the first electrical connector aligned to the second electrical connector, a metal layer is plated on the first and the second electrical connectors. The metal layer bonds the first electrical connector to the second electrical connector.

Abstract: The present invention relates generally to methods of treating cancer with arginine deiminase, and in particular pegylated arginine deiminase.

Abstract: The present invention provides an exchangeable-battery photocuring device, comprising a supporting frame, having a plurality of walls, wherein the plurality of walls constitutes a chamber having at least one opening; a UV LED module, disposed on the supporting frame; a outer housing, having an external opening corresponding to the opening of the supporting frame; a control module; an exchangeable battery module, disposed on the supporting frame, wherein the exchangeable battery module comprises a battery holder and a battery, and the exchangeable battery module is electrically connected to the control module, and a handle. The present invention applying an exchangeable battery module achieves that the photocuring device is used without being constrained by location and space. Furthermore, the present invention also provides an exchangeable-battery photocuring device with a slidable lid and a portable battery photocuring device with a slidable lid.

Abstract: The disclosure provides a moving apparatus for a projector. The projector includes a body, a processing unit and a projection lens. The moving apparatus includes a base having a through-base opening. At least one moving stage movably disposed on a front side surface of the base along a plane and has at least one through-stage opening aligned with the through-base opening. At least one magnetic component disposed on a carrier board, wherein a projection position of the projection lens is positioned by the at least one magnetic board through magnetic attraction. The at least one magnetic component is electrically connected to the processing unit.

Abstract: A via opening including an etch stop layer (ESL) opening and methods of forming the same are provided which can be used in the back end of line (BEOL) process of IC fabrication. A metal feature is provided with a first part within a dielectric layer and with a top surface. An ESL is formed with a bottom surface of the ESL above and in contact with the dielectric layer, and a top surface of the ESL above the bottom surface of the ESL. An opening at the ESL is formed exposing the top surface of the metal feature; wherein the opening at the ESL has a bottom edge of the opening above the bottom surface of the ESL, a first sidewall of the opening at a first side of the metal feature, and a second sidewall of the opening at a second side of the metal feature.

Abstract: A via opening including an etch stop layer (ESL) opening and methods of forming the same are provided which can be used in the back end of line (BEOL) process of IC fabrication. A metal feature is provided with a first part within a dielectric layer and with a top surface. An ESL is formed with a bottom surface of the ESL above and in contact with the dielectric layer, and a top surface of the ESL above the bottom surface of the ESL. An opening at the ESL is formed exposing the top surface of the metal feature; wherein the opening at the ESL has a bottom edge of the opening above the bottom surface of the ESL, a first sidewall of the opening at a first side of the metal feature, and a second sidewall of the opening at a second side of the metal feature.

Abstract: An integrated circuit package and a method of forming the same are provided. A method includes attaching a first side of an integrated circuit die to a carrier. An encapsulant is formed over and around the integrated circuit die. The encapsulant is patterned to form a first opening laterally spaced apart from the integrated circuit die and a second opening over the integrated circuit die. The first opening extends through the encapsulant. The second opening exposes a second side of the integrated circuit die. The first side of the integrated circuit die is opposite the second side of the integrated circuit die. A conductive material is simultaneously deposited in the first opening and the second opening.

Abstract: A device includes a substrate and at least three conducting features embedded into the substrate. Each conducting feature includes a top width x and a bottom width y, such that a top and bottom width (x1, y1) of a first conducting feature has a dimension of (x1<y1), a top and bottom width (x2, y2) of a second conducting feature has a dimension of (x2<y2; x2=y2; or x2>y2), and a top and bottom width (x3, y3) of a third conducting feature has a dimension of (x3>y3). The device also includes a gap structure isolating the first and second conducting features. The gap structure can include such things as air or dielectric.

Abstract: A bonding method of a semiconductor device is disclosed. The method includes steps of forming a plurality of holes on two bonding parts of a main substrate, respectively; disposing a semiconductor device on the main substrate, and aligning the two bonding parts with two conduction parts of the semiconductor device; aligning a laser to the conduction parts and operating the laser to emit a laser beam from a lower part of the main substrate, wherein the laser beam passes through the holes of the bonding part to strike on the conduction part, so as to melt each conduction part to bond with the bonding part. With configuration of the holes, the conduction parts and the bonding part can be smoothly bonded by using laser, so as to achieve the purpose of transferring the semiconductor device.

Abstract: A support structure for a light-emitting diode utilizes the configuration of a sacrifice structure to achieve safe separation of a light-emitting diode from a carrier substrate. Specifically, when an external force is applied on the light-emitting diode or the carrier substrate, a breaking layer of the sacrifice structure is the first layer to be broken, so that the light-emitting diode and carrier substrate will become separated from each other.

Abstract: A method to align a next generation sequencing read to a reference sequence includes: (a) receiving a sequencing read; (b) performing a first alignment of the sequencing read to a reference sequence so as to identify a target sequence within the reference sequence whereto the sequencing read maps; (c) selecting a first and a second anchor sequence; (d) attaching the first anchor sequence to the upstream region of the sequencing read and the second anchor sequence to the downstream region of the sequencing read so as to generate an extended sequencing read; (e) attaching the first anchor sequence to the upstream region of the target sequence and the second anchor sequence to the downstream region of the target sequence, so as to generate an extended target sequence; (f) performing a second alignment of the extended sequencing read to the extended target sequence, so that the second alignment is more correctly mapped to the target sequence than the first alignment; (g) identifying a position where one or more b

Abstract: An interconnection structure includes a first dielectric layer, a bottom conductive feature present in the first dielectric layer, a second dielectric layer present on the first dielectric layer, an aluminum-containing etch stop layer present between the first dielectric layer and the second dielectric layer, an upper conductive via present at least in the second dielectric layer and electrically connected to the bottom conductive feature, and at least one aluminum-containing fragment present at least at a bottom corner of the upper conductive via.