Abstract: A chip assembly includes a PCB and a chip positioned on the PCB. The PCB includes a number of first bonding pads. Each bonding pad includes two soldering balls formed thereon. The chip includes a number of second bonding pads, and each second bonding pad corresponds to a respective first bonding pad. The two soldering balls of each first bonding pad are electrically connected to a corresponding second bonding pad via two bonding wires, and the bonding wires are bonded to the second corresponding bonding pad by a wedge bonding manner.

Abstract: An optical-electrical module includes a base board, a laser diode, an integrated circuit, and a lens unit. The laser diode and the integrated circuit are both fixed on the base board. The lens unit and the base board cooperatively define a receiving space to receive the laser diode and the integrated circuit. The laser diode has a transmitting window at an end of the laser diode away from the base board. The integrated circuit drives the laser diode to transmit optical signals. The lens unit has an inner surface facing the base board, and the inner surface of the lens unit has a light transmitting area. The lens unit includes a metal film formed on the inner surface of the lens unit except on the light transmitting area.

Abstract: Sidewall protection processes are provided for Cu pillar bump technology, in which a protection structure on the sidewalls of the Cu pillar bump is formed of at least one of non-metal material layers, for example a dielectric material layer, a polymer material layer, or combinations thereof.

Abstract: A semiconductor device is disclosed. The device includes a substrate, a first dielectric layer disposed over the substrate and a metal structure disposed in the first dielectric layer and below a surface of the first dielectric layer. The metal structure has a such shape that having an upper portion with a first width and a lower portion with a second width. The second width is substantially larger than the first width. The semiconductor device also includes a sub-structure of a second dielectric positioned between the upper portion of the metal structure and the first dielectric layer.

Abstract: A connector includes a casing, a circuit board, a joint and an adapter. The casing has an accommodating space. The circuit board, located in the accommodating space, has multiple conductive contacts. The joint, assembled on the casing, is electrically connected to the circuit board. The adapter module, detachably assembled in the accommodating space, includes a first body, a second body and multiple piercing terminals. The first body has multiple insertion slots. The second body is combined with the first body. The multiple piercing terminals, located on the second body, correspond to the insertion slots and are electrically connected to the multiple conductive contacts.

Abstract: A circuit board includes a dielectric layer and a signal routing layer on the dielectric layer. The signal routing layer includes connector traces, chip traces, and signal traces connecting the two. A width of the signal traces is greater than a width of the chip traces, which is less than a width of the connector traces. The dielectric layer includes trace areas of different depths for each type of trace to achieve a uniform impedance throughout all traces.

Abstract: The present disclosure is directed to a semiconductor structure and a method of manufacturing a semiconductor structure in which a spacer element is formed adjacent to a metal body embedded in a first dielectric layer of a first interconnect layer. A via which is misaligned relative to an edge of the metal body is formed in a second dielectric material in second interconnect layer disposed over the first interconnect layer and filled with a conductive material which is electrically coupled to the metal body. The method allows for formation of an interconnect structure without encountering the various problems presented by via substructure defects in the dielectric material of the first interconnect layer, as well as eliminating conventional gap-fill metallization issues.

Abstract: A method for patterning vias in a chip comprises forming a photomask layer including a gap on a patterned hardmask layer including a plurality of trenches and in contact with a uniform layer on a substrate, wherein the gap overlaps with two or more of the trenches. The method further comprises exposing a portion of the uniform layer under the gap using a photo exposure process, etching the exposed portion of the uniform layer with the photomask layer to obtain a plurality of vias extended partially through the substrate, and further etching the vias to obtain corresponding through-substrate vias. Another method comprises patterning a plurality of vias in a plurality of trenches of a hardmask layer on a substrate using a single photo exposure step and a photomask comprising a single gap that overlaps with the trenches.

Abstract: Nonvolatile memory elements that are based on resistive switching memory element layers are provided. A nonvolatile memory element may have a resistive switching metal oxide layer. The resistive switching metal oxide layer may have one or more layers of oxide. A resistive switching metal oxide may be doped with a dopant that increases its melting temperature and enhances its thermal stability. Layers may be formed to enhance the thermal stability of the nonvolatile memory element. An electrode for a nonvolatile memory element may contain a conductive layer and a buffer layer.

Abstract: A connector includes a lower casing, a circuit board, a connecting head, multiple puncturing terminals, an upper casing and an upper lid. The lower casing includes a base and at least one support pole provided on the base. The base has an accommodating slot. The circuit board disposed in the accommodating slot. The connecting head is disposed on the base, and is electrically connected to the circuit board. The puncturing terminals are disposed on the circuit board. The upper casing includes a casing body, a cantilever structure extending from one side of the casing body and a cable holder located on the cantilever structure. The upper lid is disposed on the upper casing body. The upper lid has a release position and an open position relative to the casing body.

Abstract: A device includes a substrate and at least three conducting features embedded into the substrate. Each conducting feature includes a top width x and a bottom width y, such that a top and bottom width (x1, y1) of a first conducting feature has a dimension of (x1<y1), a top and bottom width (x2, y2) of a second conducting feature has a dimension of (x2<y2; x2=y2; or x2>y2), and a top and bottom width (x3, y3) of a third conducting feature has a dimension of (x3>y3). The device also includes a gap structure isolating the first and second conducting features. The gap structure can include such things as air or dielectric.

Abstract: The invention is related to prediction of a lost or damaged block of an enhanced spatial layer frame. A method for predicting a lost or damaged block of an enhanced spatial layer frame comprises the steps of determining an adjuvant frame in the enhanced spatial layer by help of reference information from a lower spatial layer frame corresponding said enhanced spatial layer frame, generating an information reduced block by help of said adjuvant frame and predicting the lost or damaged block by help of the information reduced block. The reference information of the corresponding lower spatial layer frame can be decoded independently from any lower spatial layer reference frame and the adjuvant enhanced spatial layer frame is already decoded. Thus, the computational effort is reduced. By generation of the information reduced block the prediction is made smoother which makes it less vivid and therefore less salient to a user.

Abstract: This description relates to an integrated circuit device including a conductive pillar formed over a substrate. The conductive pillar has a sidewall surface and a top surface. The integrated circuit device further includes an under-bump-metallurgy (UBM) layer between the substrate and the conductive pillar. The UBM layer has a surface region. The integrated circuit device further includes a protection structure on the sidewall surface of the conductive pillar and the surface region of the UBM layer. The protection structure is formed of a non-metal material.

Abstract: A computing device is electronically connected to a measurement machine and a controller. The controller is connected to a sensor installed on the measurement machine. The computing device receives spectral signal data sent from the controller and generates an intensity distribution diagram according to the spectral signal data. Furthermore, the computing device sends control commands to the measurement machine, to adjust a position of the sensor on the measurement machine according to variation of a peak value of a wave in the intensity distribution diagram.

Abstract: An optical communication module includes a substrate, an optical signal receiving unit, an optical signal emitting unit and a coupler. The substrate includes a first surface and a second surface. The substrate defines through holes passing through the first and second surfaces. The optical signal receiving unit includes optical-electrical signal converters. The optical signal emitting unit includes optical signal generators. Each of the optical-electrical signal converters and the optical signal generators is mounted on the first surface and aligned with a corresponding one of the through holes. The coupler includes coupling lenses. The coupler is fixed to the second surface. Each of the optical-electrical signal converters and the optical signal generators is aligned with a corresponding coupling lens through the corresponding through hole.

Abstract: An optical fiber coupling assembly includes a first optical fiber connector, a second optical fiber connector, and a cable. The first optical fiber connector defines a number of first blind holes receiving first focus lenses, and first through holes respectively communicating with the first blind holes. The second optical fiber connector defines a number of second blind holes receiving second focus lenses, and second through holes respectively communicating with the second blind holes. The cable includes a number of optical fibers. Each optical fiber includes a first end and a second end, and the first end is received in a corresponding one of the first through holes and aligned with the a corresponding one of the first focus lenses, and the second end is received in a corresponding one of the second through holes and aligned with a corresponding one of the second focus lenses.

Abstract: A touch display driving circuit capable of responding to CPU commands, including: a first interface for receiving pixel data and touch configuration data; a second interface for coupling with a touch display; and a control unit, which drives the touch display via the second interface to show an image according to the pixel data, and executes a touch detection procedure on the touch display via the second interface, wherein the touch detection procedure is determined according to the touch configuration data.

Abstract: A portable electronic device includes a detachable first casing, an antenna, and a first coupling element. The antenna is disposed in the detachable first casing, and the first coupling element is disposed at an inner wall of the detachable first casing. In addition, the first coupling element does not contact the antenna and overlaps the antenna in a vertical projection plane.

Abstract: A scalable video bitstream may have an H.264/AVC compatible base layer and a scalable enhancement layer, where scalability refers to color bit-depth. According to the invention, BL information is bit-depth upsampled using separate look-up tables for inverse tone mapping on two or more hierarchy levels, such as picture level, slice level or MB level. The look-up tables are differentially encoded and included in header information. Bit-depth upsampling is a process that increases the number of values that each pixel can have, corresponding to the pixels color intensity. The upsampled base layer data are used to predict the collocated enhancement layer, based on said look-up tables. The upsampling is done at the encoder side and in the same manner at the decoder side, wherein the upsampling may refer to temporal, spatial and bit depth characteristics. Thus, the bit-depth upsampling is compatible with texture upsampling.

Abstract: An optical fiber connector is positioned on a printed circuit board (PCB) and includes a main body, a number of slots, and a number of optical fibers. The main body includes a number of light transceivers. Each of the light transceivers includes a light transmitting module and a light receiving module adjacent to the light transmitting module. One end of each of the optical fibers is optically coupled to a respective one of the light emitting modules and the light receiving modules, and the other end of each of the optical fibers is mounted on a respective one of the slots.