Abstract: Disclosed is a warpage suppressing reflow oven, which comprises a reflow oven body, where a perforated steel plate circulating device comprising a perforated steel plate is disposed at a reflow-oven inner oven. A plurality of downdraft modules is arranged in the perforated steel plate, and the downdraft acting forces thereof face the upper panel. More than one air extractor is communicated with the plurality of downdraft modules via a plurality of pipelines. Under actuation of the air extractors, the downdraft modules generate downdraft acting forces to the bottom surfaces of the products, so that the products are flatly attached to the universal perforated carriers without warpage in a heat soldering process. Thereby, more uniform heating of the products and better contact of solder joints and effectively improving the yield of reflow soldering operations are achieved.

Abstract: A microLED display includes a first main substrate, microLEDs disposed above the first main substrate, a first light blocking layer disposed above the first main substrate to define emission areas, a light guiding layer disposed in the emission areas, and a plurality of connecting structures disposed in the emission areas respectively and electrically connected with the microLEDs.

Abstract: The disclosure provides a light cabinet, including multiple light boards and multiple light-board controllers. The light boards form a first light-board array of the light cabinet. The light-board controllers are arranged one-to-one on the light boards. The light-board controllers of the light boards in a first column of the first light-board array are connected in series to form a first controller string. The output terminal of the first controller string is connected electrically to an input terminal of a second controller string in a corresponding column of a second light-board array of another light cabinet. The input terminal of the first controller string is connected electrically to a first output terminal of a video data splitter (or an output terminal of a third controller string in a corresponding column of a third light-board array of yet another light cabinet).

Abstract: In an embodiment, a method includes: forming a differential contact etch stop layer (CESL) having a first portion over a source/drain region and a second portion along a gate stack, the source/drain region being in a substrate, the gate stack being over the substrate proximate the source/drain region, a first thickness of the first portion being greater than a second thickness of the second portion; depositing a first interlayer dielectric (ILD) over the differential CESL; forming a source/drain contact opening in the first ILD; forming a contact spacer along sidewalls of the source/drain contact opening; after forming the contact spacer, extending the source/drain contact opening through the differential CESL; and forming a first source/drain contact in the extended source/drain contact opening, the first source/drain contact physically and electrically coupling the source/drain region, the contact spacer physically separating the first source/drain contact from the first ILD.

Abstract: A flow stabilized chip includes a chip mainbody, a buffering chamber and two fluid delivery ports. The chip mainbody has a pipe-connection surface. The buffering chamber is disposed in the chip mainbody. The two fluid delivery ports are disposed on the pipe connection surface and connected to the buffering chamber. The chip mainbody includes, in order from the pipe-connection surface to a bottom of the chip mainbody, a first base plate, a first elastic membrane, a second base plate, a second elastic membrane and a third base plate. The first base plate includes a first opening. The second base plate includes a second opening. The third base plate includes a third opening. The first elastic membrane, the second base plate and the second elastic membrane are stacked in sequence to form the buffering chamber.

Abstract: Provided are methods and compositions for promoting tissue (e.g., muscle) regeneration using one or more activators of fatty acid oxidation, such as one or more PPAR? activators. The methods and compositions described herein are also useful for promoting tissue growth, inducing proliferation of stem cells, inducing differentiation of tissuegenic cells (e.g., myogenic cells), and treating a disease or condition associated with a tissue (e.g., muscle), such as tissue injury, degeneration or aging, in an individual.

Abstract: The present disclosure provides a geomagnetic positioning device, comprising a base assembly and a connecting assembly. The base assembly comprises a control component, a driving component, and a first geomagnetic component. The control component is electrically connected with the driving component and the first geomagnetic component. The connecting assembly is disposed at the driving component and comprises a second geomagnetic component. Wherein the control component obtains the deviation angle of the second geomagnetic component relative to the first geomagnetic component. The control component controls the driving component according to the deviation angle to adjust the relative angle of the connecting assembly relative to the base assembly.

Abstract: A semiconductor device structure includes nanostructures formed over a substrate. The structure also includes a gate structure formed over and around the nanostructures. The structure also includes a spacer layer formed over a sidewall of the gate structure over the nanostructures. The structure also includes a source/drain epitaxial structure formed adjacent to the spacer layer. The structure also includes a contact structure formed over the source/drain epitaxial structure with an air spacer formed between the spacer layer and the contact structure.

Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate, and a first inter-layer dielectric (ILD) layer formed over the fin structure. The FinFET device structure includes a gate structure formed in the first ILD layer, and a first S/D contact structure formed in the first ILD layer and adjacent to the gate structure. The FinFET device structure also includes a first air gap formed on a sidewall of the first S/D contact structure, and the first air gap is in direct contact with the first ILD layer.

Abstract: Packaged devices and methods of manufacturing the devices are described herein. The packaged devices may be fabricated using heterogeneous devices and asymmetric dual-side molding on a multi-layered redistribution layer (RDL) structure. The packaged devices may be formed with a heterogeneous three-dimensional (3D) Fan-Out System-in-Package (SiP) structure having small profiles and can be formed using a single carrier substrate.

Abstract: A via opening including an etch stop layer (ESL) opening and methods of forming the same are provided which can be used in the back end of line (BEOL) process of IC fabrication. A metal feature is provided with a first part within a dielectric layer and with a top surface. An ESL is formed with a bottom surface of the ESL above and in contact with the dielectric layer, and a top surface of the ESL above the bottom surface of the ESL. An opening at the ESL is formed exposing the top surface of the metal feature; wherein the opening at the ESL has a bottom edge of the opening above the bottom surface of the ESL, a first sidewall of the opening at a first side of the metal feature, and a second sidewall of the opening at a second side of the metal feature.

Abstract: An interconnect fabrication method is disclosed herein that utilizes a disposable etch stop hard mask over a gate structure during source/drain contact formation and replaces the disposable etch stop hard mask with a dielectric feature (in some embodiments, dielectric layers having a lower dielectric constant than a dielectric constant of dielectric layers of the disposable etch stop hard mask) before gate contact formation. An exemplary device includes a contact etch stop layer (CESL) having a first sidewall CESL portion and a second sidewall CESL portion separated by a spacing and a dielectric feature disposed over a gate structure, where the dielectric feature and the gate structure fill the spacing between the first sidewall CESL portion and the second sidewall CESL portion. The dielectric feature includes a bulk dielectric over a dielectric liner. The dielectric liner separates the bulk dielectric from the gate structure and the CESL.

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a gate structure disposed over a channel region of an active region, a drain feature disposed over a drain region of the active region; a source feature disposed over a source region of the active region, a backside source contact disposed under the source feature, an isolation feature disposed on and in contact with the source feature, a drain contact disposed over and electrically coupled to the drain feature, and a gate contact via disposed over and electrically coupled to the gate structure. A distance between the gate contact via and the drain contact is greater than a distance between the gate contact via and the isolation feature. The exemplary semiconductor structure would have a reduced parasitic capacitance and an enlarged leakage window.

Abstract: The disclosure provides a display equipment, a brightness compensation device, and a brightness compensation method. The brightness compensation device includes a variable refresh rate (VRR) detection circuit and a control circuit. The VRR detection circuit and the control circuit receive a video stream from a video source device, and the video stream includes a VRR video frame. The VRR detection circuit detects a blanking period of the VRR video frame and generates a detection result. The control circuit outputs the frame data of the VRR video frame to the display device during the valid data period of the VRR video frame. The control circuit repeatedly outputs the frame data of the VRR video frame to the display device during the blanking period of the VRR video frame according to the detection result until the blanking period ends.

Abstract: A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes a semiconductor die, an encapsulant and a redistribution structure. The encapsulant laterally encapsulates the semiconductor die. The redistribution structure is disposed on the encapsulant and electrically connected with the semiconductor die, wherein the redistribution structure comprises a first conductive via, a first conductive wiring layer and a second conductive via stacked along a stacking direction, the first conductive via has a first terminal surface contacting the first conductive wiring layer, the second conductive via has a second terminal surface contacting the first conductive wiring layer, an area of a first cross section of the first conductive via is greater than an area of the first terminal surface of the first conductive via, and an area of a second cross section of the second conductive via is greater than an area of the second terminal surface of the second conductive via.

Abstract: In an embodiment, an apparatus comprising: a heater configured to heat a wafer located on a wafer staging area of the heater, the heater comprising a heater shaft extending below the wafer staging area; and a heater lift assembly comprising: a lift shaft configured to move the heater shaft in a vertical direction; a clamp that connects the heater shaft to the lift shaft; and a damper disposed on top of the clamp.

Abstract: A transfer system adaptable to performing levelling alignment includes a transfer head that picks up micro devices, the transfer head having a plurality of pick-up heads protruded from a bottom surface of the transfer head; and a levelling fixture configured to perform levelling alignment for the transfer head, the levelling fixture having a plurality of cavities that are concave downwards to correspondingly accommodate the pick-up heads respectively.

Abstract: The disclosure provides a light cabinet, including multiple light boards and multiple light-board controllers. The light boards form a first light-board array of the light cabinet. The light-board controllers are arranged one-to-one on the light boards. The light-board controllers of the light boards in a first column of the first light-board array are connected in series to form a first controller string. The output terminal of the first controller string is connected electrically to an input terminal of a second controller string in a corresponding column of a second light-board array of another light cabinet. The input terminal of the first controller string is connected electrically to a first output terminal of a video data splitter (or an output terminal of a third controller string in a corresponding column of a third light-board array of yet another light cabinet).

Abstract: A package structure is provided. The package structure includes a redistribution structure, and the redistribution structure has multiple insulating layers and multiple conductive features. The package structure also includes a semiconductor die and a device element over opposite surfaces of the redistribution structure. The package structure further includes a first protective layer at least partially surrounding the semiconductor die. In addition, the package structure includes a second protective layer at least partially surrounding the device element. The second protective layer is thicker than the first protective layer, and the second protective layer and the first protective layer have different coefficients of thermal expansion.

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary method includes forming a fin-shaped structure extending from a front side of a substrate, recessing a source region of the fin-shaped structure to form a source opening, forming a semiconductor plug under the source opening, exposing the semiconductor plug from a back side of the substrate, selectively removing a first portion of the substrate without removing a second portion of the substrate adjacent to the semiconductor plug, forming a backside dielectric layer over a bottom surface of the workpiece, replacing the semiconductor plug with a backside contact, and selectively removing the second portion of the substrate to form a gap between the backside dielectric layer and the backside contact. By forming the gap, a parasitic capacitance between the backside contact and an adjacent gate structure may be advantageously reduced.