Patents by Inventor Wen Wu

Wen Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Dual-sided routing in 3D SiP structure
    Patent number: 11322447
    Abstract: A semiconductor package is fabricated by attaching a first component to a second component. The first component is assembled by forming a first redistribution structure over a substrate. A through via is then formed over the first redistribution structure, and a die is attached to the first redistribution structure active-side down. The second component includes a second redistribution structure, which is then attached to the through via. A molding compound is deposited between the first redistribution structure and the second redistribution structure and further around the sides of the second component.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: May 3, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Hao Tsai, Po-Yao Chuang, Meng-Liang Lin, Yi-Wen Wu, Shin-Puu Jeng, Techi Wong
  • Epitaxial Source/Drain Structure and Method
    Publication number: 20220130961
    Abstract: A method of semiconductor fabrication includes providing a semiconductor structure having a substrate and first, second, third, and fourth fins above the substrate. The method further includes forming an n-type epitaxial source/drain (S/D) feature on the first and second fins, forming a p-type epitaxial S/D feature on the third and fourth fins, and performing a selective etch process on the semiconductor structure to remove upper portions of the n-type epitaxial S/D feature and the p-type epitaxial S/D feature such that more is removed from the n-type epitaxial S/D feature than the p-type epitaxial S/D feature.
    Type: Application
    Filed: January 10, 2022
    Publication date: April 28, 2022
    Inventors: I-Wen Wu, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang, Chun-An Lin, Wei-Yuan Lu, Guan-Ren Wang, Peng Wang
  • Package structure and method of fabricating the same
    Patent number: 11302650
    Abstract: A package structure includes a redistribution structure, a first semiconductor die, a first passive component, a second semiconductor die, a first insulating encapsulant, a second insulating encapsulant, a second passive component and a global shielding structure. The redistribution structure includes dielectric layers and conductive layers alternately stacked. The first semiconductor die, the first passive component and the second semiconductor die are disposed on a first surface of the redistribution structure. The first insulating encapsulant is encapsulating the first semiconductor die and the first passive component. The second insulating encapsulant is encapsulating the second semiconductor die, wherein the second insulating encapsulant is separated from the first insulating encapsulant. The second passive component is disposed on a second surface of the redistribution structure.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: April 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Wen Wu, Shin-Puu Jeng, Shih-Ting Hung, Po-Yao Chuang
  • Parasitic capacitance reduction
    Patent number: 11302802
    Abstract: The present disclosure provides semiconductor devices and methods of forming the same. A semiconductor device according to one embodiment of the present disclosure includes a first fin-shaped structure extending lengthwise along a first direction over a substrate, a first epitaxial feature over a source/drain region of the first fin-shaped structure, a gate structure disposed over a channel region of the first fin-shaped structure and extending along a second direction perpendicular to the first direction, and a source/drain contact over the first epitaxial feature. The bottommost surface of the gate structure is closer to the substrate than a bottommost surface of the source/drain contact.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: April 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jia-Heng Wang, Chun-Han Chen, I-Wen Wu, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
  • METHOD FOR ENCODING AND/OR DECODING IMAGES ON MACROBLOCK LEVEL USING INTRA-PREDICTION
    Publication number: 20220094976
    Abstract: Conventional intra-prediction uses pixels from left and upper neighbour blocks to predict a macroblock (MB). Thus, the MBs must be sequentially processed, since reconstructed left and upper MBs must be available for prediction. In an improved method for encoding Intra predicted MBs, a MB is encoded in two steps: first, a first portion of the MB is encoded independently, without references outside the MB. Pixels of the first portion can be Intra predicted using DC mode. Then, the first portion is reconstructed. The remaining pixels of the MB, being a second portion, are intra predicted from the reconstructed pixels of the first portion and then reconstructed. The first portion comprises at least one column or one row of pixels of the MB. The encoding is applied to at least two Intra predicted MBs per slice, or per picture if no slices are used.
    Type: Application
    Filed: December 6, 2021
    Publication date: March 24, 2022
    Inventor: Yu Wen WU
  • METAL ADHESION LAYER TO PROMOTE METAL PLUG ADHESION
    Publication number: 20220084879
    Abstract: A metal adhesion layer may be formed on a bottom and a sidewall of a trench prior to formation of a metal plug in the trench. A plasma may be used to modify the phase composition of the metal adhesion layer to increase adhesion between the metal adhesion layer and the metal plug. In particular, the plasma may cause a shift or transformation of the phase composition of the metal adhesion layer to cause the metal adhesion layer to be composed of a (111) dominant phase. The (111) dominant phase of the metal adhesion layer increases adhesion between the metal adhesion layer.
    Type: Application
    Filed: September 15, 2020
    Publication date: March 17, 2022
    Inventors: Pei-Wen WU, Chun-I TSAI, Chi-Cheng HUNG, Jyh-Cherng SHEU, Yu-Sheng WANG, Ming-Hsing TSAI
  • Two-node high availability storage system
    Patent number: 11269745
    Abstract: Aspects of the present invention disclose a method for a two-node storage system. The method includes one or more processors creating a plurality of first logic unit groups in a first storage node of a storage system. The method further includes mapping each of the plurality of first logic unit groups to a number of storage slices from different storage devices in the first storage node. The method further creating a plurality of second logic unit groups in a second storage node of the storage system, by mirroring storage slices from a storage device in the first storage node to multiple storage devices in the second storage node. In response to identifying a failure of a first storage device in the first storage node, the method further includes recovering lost data based on data in the second storage node.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: March 8, 2022
    Assignee: International Business Machines Corporation
    Inventors: Long Wen Lan, Wen Wu Na, Xiang Wen Liu, Xiao Yu Wang
  • Source/drain contact having a protruding segment
    Patent number: 11264393
    Abstract: A semiconductor device includes a fin structure. A source/drain region is formed on the fin structure. A first gate structure is disposed over the fin structure. A source/drain contact is disposed over the source/drain region. The source/drain contact has a protruding segment that protrudes at least partially over the first gate structure. The source/drain contact electrically couples together the source/drain region and the first gate structure.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: March 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jui-Lin Chen, Chao-Yuan Chang, Ping-Wei Wang, Fu-Kai Yang, Ting Fang, I-Wen Wu, Shih-Hao Lin
  • Method of making a pillar structure having a non-metal sidewall protection structure and integrated circuit including the same
    Patent number: 11257714
    Abstract: An integrated circuit device includes a semiconductor substrate; and a pad region over the semiconductor substrate. The integrated circuit device further includes an under-bump-metallurgy (UBM) layer over the pad region. The integrated circuit device further includes a conductive pillar on the UBM layer, wherein the conductive pillar has a sidewall surface and a top surface. The integrated circuit device further includes a protection structure over the sidewall surface of the conductive pillar, wherein sidewalls of the UBM layer are substantially free of the protection structure, and the protection structure is a non-metal material.
    Type: Grant
    Filed: July 21, 2015
    Date of Patent: February 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien Ling Hwang, Yi-Wen Wu, Chun-Chieh Wang, Chung-Shi Liu
  • Integrated circuit packages and methods of forming same
    Patent number: 11239233
    Abstract: An integrated circuit package and a method of forming the same are provided. A method includes attaching a first side of an integrated circuit die to a carrier. An encapsulant is formed over and around the integrated circuit die. The encapsulant is patterned to form a first opening laterally spaced apart from the integrated circuit die and a second opening over the integrated circuit die. The first opening extends through the encapsulant. The second opening exposes a second side of the integrated circuit die. The first side of the integrated circuit die is opposite the second side of the integrated circuit die. A conductive material is simultaneously deposited in the first opening and the second opening.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: February 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Wen Wu, Hung-Jui Kuo, Ming-Che Ho
  • Isolation features and methods of fabricating the same
    Patent number: 11239309
    Abstract: Semiconductor devices and methods of fabricating semiconductor devices are provided. The present disclosure provides a semiconductor device that includes a first fin structure and a second fin structure each extending from a substrate; a first gate segment over the first fin structure and a second gate segment over the second fin structure; a first isolation feature separating the first and second gate segments; a first source/drain (S/D) feature over the first fin structure and adjacent to the first gate segment; a second S/D feature over the second fin structure and adjacent to the second gate segment; and a second isolation feature also disposed in the trench. The first and second S/D features are separated by the second isolation feature, and a composition of the second isolation feature is different from a composition of the first isolation feature.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: February 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: I-Wen Wu, Fu-Kai Yang, Chen-Ming B. Lee, Mei-Yun Wang, Jr-Hung Li, Bo-Cyuan Lu
  • Epitaxial source/drain structure and method
    Patent number: 11222951
    Abstract: A method of semiconductor fabrication includes providing a semiconductor structure having a substrate and first, second, third, and fourth fins above the substrate. The method further includes forming an n-type epitaxial source/drain (S/D) feature on the first and second fins, forming a p-type epitaxial S/D feature on the third and fourth fins, and performing a selective etch process on the semiconductor structure to remove upper portions of the n-type epitaxial S/D feature and the p-type epitaxial S/D feature such that more is removed from the n-type epitaxial S/D feature than the p-type epitaxial S/D feature.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: January 11, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: I-Wen Wu, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang, Chun-An Lin, Wei-Yuan Lu, Guan-Ren Wang, Peng Wang
  • Method for source/drain contact formation in semiconductor devices using common doping and common etching to n-type and p-type source/drains
    Patent number: 11217492
    Abstract: A method includes providing a structure that includes a substrate, a first gate structure and a second gate structure over the substrate, and a first source/drain (S/D) feature and a second S/D feature over the substrate. The first S/D feature is adjacent to the first gate structure, the second S/D feature is adjacent to the second gate structure, the first S/D feature is configured for an n-type transistor, and the second S/D feature is configured for a p-type transistor. The method further includes introducing a p-type dopant into both the first and the second S/D features. After the introducing of the p-type dopant, the method further includes performing an etching process to the first and the second S/D features, wherein the etching process etches the first S/D feature faster than it etches the second S/D feature.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: January 4, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shao-Ming Koh, Chen-Ming Lee, I-Wen Wu, Fu-Kai Yang, Jia-Heng Wang, Mei-Yun Wang
  • BONDING STRUCTURE OF ELECTRICAL CONTACT, BONDING METHOD OF ELECTRICAL CONTACT AND BATTERY MODULE
    Publication number: 20210408644
    Abstract: A bonding structure of an electrical contact, a bonding method of the electrical contact and a battery module are provided. The bonding structure of the electrical contact includes an electroconductive part and an electrode sheet welded to the electroconductive part. The electrode sheet is a first metal material, and the electroconductive part is a second metal material. A welding track is formed on an interface formed by combining the electrode sheet with the electroconductive part. The welding track is a mixture of the first metal material and the second metal material. The welding track substantially has no overlap. In addition, the welding track includes a moving path, and a lateral path of performing a wobble movement or an oscillation movement on lateral sides of the moving path.
    Type: Application
    Filed: April 29, 2021
    Publication date: December 30, 2021
    Inventors: YU-WEN WU, SHANG-HSIEN WU, CHUN-YAO WANG
  • PHOTOSENSITIZERS AND METHOD OF TREATING CANCER USING THE SAME
    Publication number: 20210401867
    Abstract: The present disclosure provides a heavy atom carrier and a method of treating cancer using the heavy atom carriers in conjunction with monochromatic X-ray. The heavy atom carriers are halogen-containing heavy atom carriers.
    Type: Application
    Filed: April 1, 2019
    Publication date: December 30, 2021
    Inventors: CHENG-WEN WU, ERH-HSUAN LIN, WAN-TING TSENG
  • SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING
    Publication number: 20210391317
    Abstract: Packaged devices and methods of manufacturing the devices are described herein. The packaged devices may be fabricated using heterogeneous devices and asymmetric dual-side molding on a multi-layered redistribution layer (RDL) structure. The packaged devices may be formed with a heterogeneous three-dimensional (3D) Fan-Out System-in-Package (SiP) structure having small profiles and can be formed using a single carrier substrate.
    Type: Application
    Filed: June 15, 2020
    Publication date: December 16, 2021
    Inventors: Yi-Wen Wu, Po-Yao Chuang, Meng-Liang Lin, Techi Wong, Shih-Ting Hung, Po-Hao Tsai, Shin-Puu Jeng
  • METHOD FOR FORMING PACKAGE STRUCTURE
    Publication number: 20210384125
    Abstract: A method for forming a package structure is provided. The method includes forming a first interconnect structure over a carrier substrate and disposing a first die structure over the first interconnect structure. The method includes forming a dam structure over the first die structure. The method also includes forming a protection layer over a second interconnect structure. The method further includes bonding the second interconnect structure over the dam structure. In addition, the method includes forming a package layer between the first interconnect structure and the second interconnect structure. The method also includes removing the protection layer.
    Type: Application
    Filed: August 18, 2021
    Publication date: December 9, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Hao TSAI, Techi WONG, Meng-Liang LIN, Yi-Wen WU, Po-Yao CHUANG, Shin-Puu JENG
  • Method for encoding and/or decoding images on macroblock level using intra-prediction
    Patent number: 11197022
    Abstract: Conventional intra-prediction uses pixels from left and upper neighbour blocks to predict a macroblock (MB). Thus, the MBs must be sequentially processed, since reconstructed left and upper MBs must be available for prediction. In an improved method for encoding Intra predicted MBs, a MB is encoded in two steps: first, a first portion of the MB is encoded independently, without references outside the MB. Pixels of the first portion can be Intra predicted using DC mode. Then, the first portion is reconstructed. The remaining pixels of the MB, being a second portion, are intra predicted from the reconstructed pixels of the first portion and then reconstructed. The first portion comprises at least one column or one row of pixels of the MB. The encoding is applied to at least two Intra predicted MBs per slice, or per picture if no slices are used.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: December 7, 2021
    Assignee: INTERDIGITAL VC HOLDINGS, INC.
    Inventor: Yu Wen Wu
  • SEMICONDUCTOR PACKAGE WITH IMPROVED INTERPOSER STRUCTURE
    Publication number: 20210375755
    Abstract: A semiconductor package is provided. The semiconductor package includes an encapsulating layer, a semiconductor die formed in the encapsulating layer, and an interposer structure covering the encapsulating layer. The interposer structure includes an insulating base having a first surface facing the encapsulating layer, and a second surface opposite the first surface. The interposer structure also includes insulting features formed on the first surface of the insulating base and extending into the encapsulating layer. The insulting features are arranged in a matrix and face a top surface of the semiconductor die. The interposer structure further includes first conductive features formed on the first surface of the insulating base and extending into the encapsulating layer. The first conductive features surround the matrix of the plurality of insulting features.
    Type: Application
    Filed: August 12, 2021
    Publication date: December 2, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Wen Wu, Techi Wong, Po-Hao Tsai, Po-Yao Chuang, Shih-Ting Hung, Shin-Puu Jeng
  • HEATER LIFT ASSEMBLY SPRING DAMPER
    Publication number: 20210351048
    Abstract: In an embodiment, an apparatus comprising: a heater configured to heat a wafer located on a wafer staging area of the heater, the heater comprising a heater shaft extending below the wafer staging area; and a heater lift assembly comprising: a lift shaft configured to move the heater shaft in a vertical direction; a clamp that connects the heater shaft to the lift shaft; and a damper disposed on top of the clamp.
    Type: Application
    Filed: May 8, 2020
    Publication date: November 11, 2021
    Inventors: Kai-Wen WU, Chun-Ta CHEN, Chin-Shen HSIEH, Cheng-Yi HUANG