Abstract: A digital circuit robustness verification method is provided that includes the following steps. An internal storage circuit and an external storage circuit corresponding to a circuit under test are set to store a plurality of random values and a configuration of the circuit under test for performing a predetermined function is set by a processing circuit. A driving signal corresponding to the predetermined function is transmitted to the circuit under test by a previous stage circuit, such that the circuit under test executes the predetermined function to further generate an output signal. The determination as to whether the output signal is correct or not is made by a next stage circuit, and the circuit under test is determined to pass a robustness verification when the output signal is correct.

Abstract: A method for fabricating a semiconductor transistor is disclosed. A substrate of a first conductivity type is provided. An ion well of a second conductivity type is formed in the substrate. An epitaxial channel layer of the first conductivity type is grown from the main surface of the substrate. A gate dielectric layer is formed on the epitaxial channel layer. A gate is formed on the gate dielectric layer. A source region and a drain region are then formed in the substrate. The source region and the drain region have the first conductivity type.

Abstract: The invention provides a method for adjusting the resistance value of a thin film resistor layer in a semiconductor structure, which comprises forming the thin film resistor layer, the material of the thin film resistor layer comprises titanium nitride, and the thin film resistor layer has an original resistance value, a mask layer with tensile force is formed above the thin film resistor layer, and the mask layer with tensile force changes a lattice size of the thin film resistor layer, so that the lattice size of the thin film resistor layer becomes larger and the original resistance value of the thin film resistor layer is reduced.

Abstract: A resistive memory device includes a first electrode, a second electrode, a first metal oxide layer, a second metal oxide layer, and a multilayer insulator structure. The first metal oxide layer is disposed between the first electrode and the second electrode in a vertical direction. The second metal oxide layer is disposed between the first metal oxide layer and the second electrode in the vertical direction. The multilayer insulator structure is disposed between the first metal oxide layer and the second metal oxide layer in the vertical direction. The first metal oxide layer includes first metal atoms, the second metal oxide layer includes second metal atoms, and the multilayer insulator structure includes third metal atoms. Each of the third metal atoms is identical to each of the second metal atoms, and an atomic percent of the third metal atoms in the multilayer insulator structure gradually changes in the vertical direction.

Abstract: A method of decreasing height differences of STIs includes providing a substrate comprising a peripheral circuit region. The peripheral circuit region includes a P-type transistor region and an N-type transistor region. A first STI and a third STI are respectively disposed within the N-type transistor region and the P-type transistor region. Later, a first mask is formed to cover the N-type transistor region. Then, an N-type well is formed in the P-type transistor region and part of the third STI is removed by taking the first mask as a mask. Next, the first mask is removed. After that, a second mask is formed to cover the P-type transistor region. Subsequently, a P-type well is formed in the N-type transistor region and part of the first STI is removed by taking the second mask as a mask. Finally, the second mask is removed.

Abstract: A manufacturing method of a contact structure includes the following steps. A substrate is provided, and the substrate includes a first region and a second region. A dielectric layer is formed on the substrate. A photoresist layer is formed on the dielectric layer. An exposure process is performed. The exposure process includes first exposure steps and second exposure steps. Each of the first exposure steps is performed to a part of the first region of the substrate. Each of the second exposure steps is performed to a part of the second region of the substrate. Each of the second exposure steps is performed with a first overlay shift by a first predetermined distance. A develop process is performed for forming openings in the photoresist layer.

Abstract: A space adjustment system and a control method thereof are provided. The space adjustment system includes a body, at least one door leaf, at least one motor, and a control circuit. The door leaf is movably disposed at the body. The door panel of each door leaf includes a panel. The motor can drive the motion of the door leaf. The control circuit is coupled with the panel of the door leaf and motor. The control circuit controls the motor to drive the door leaf, and adjusts the transparency or display function of the panel on the corresponding door leaf in response to a location of the door leaf. Accordingly, multiple space type can be created.

Abstract: The present invention provides a method for preparing organometallic composite material, comprising: providing PVC resin, activated calcium carbonate, plant fiber, calcium stearate, barium sulfate, paraffin, sodium bicarbonate, zinc laurate, nanometre titanium dioxide, organometallic salt, shell powder, carbon nanotube, talcum powder and stabilizer; mixing and heating; subject to first cooling after extrusion and second cooling under vacuum; towing to obtain the organometallic composite material, wherein the organometallic salt is a benzoic acid metal salt mixture. The present method can significantly reduce the processing temperature of PVC composite by 20 to 50° C., and also increase the toughness and strength of the material so as to alleviate the exudation of the composite material as in the conventional technologies and extend the lifespan of the composite material.

Abstract: A semiconductor transistor is formed on a substrate of a first conductivity type. The substrate has a main surface. An ion well of the second conductivity type is disposed in the substrate. A source region and a drain region spaced apart from the source region are disposed within the ion well. The source region and the drain region have the first conductivity type. An epitaxial channel layer of the first conductivity type is grown from the main surface of the substrate and is disposed between the source region and the drain region. A gate is disposed on the epitaxial channel layer. A gate dielectric layer is disposed between gate and the epitaxial channel layer.

Abstract: A resistive memory device includes a first electrode, a second electrode, a first metal oxide layer, a second metal oxide layer, and a multilayer insulator structure. The first metal oxide layer is disposed between the first electrode and the second electrode in a vertical direction. The second metal oxide layer is disposed between the first metal oxide layer and the second electrode in the vertical direction. The multilayer insulator structure is disposed between the first metal oxide layer and the second metal oxide layer in the vertical direction. The first metal oxide layer includes first metal atoms, the second metal oxide layer includes second metal atoms, and the multilayer insulator structure includes third metal atoms. Each of the third metal atoms is identical to each of the second metal atoms, and an atomic percent of the third metal atoms in the multilayer insulator structure gradually changes in the vertical direction.

Abstract: The present invention discloses a display panel and a display device. The display panel comprises a plurality of common electrode blocks and a plurality of display regions. During a display period, one or more common electrode blocks corresponding to one of the display regions which is to be displayed during the display period are coupled to a common voltage; and during the display period, one or more of the common electrode blocks corresponding to the display regions which are not to be displayed during the display period are kept in a floating state.

Abstract: A semiconductor device includes a patterned metal layer on a substrate, via conductors on the patterned metal layer, first inter-metal dielectric (IMD) patterns embedded in the patterned metal layer, and a second IMD pattern surrounding the patterned metal layer. Preferably, the first IMD patterns are between and without overlapping the via conductors in a top view.

Abstract: A method for forming a semiconductor device is disclosed. A semiconductor substrate having thereon an NMOS region, a PMOS region, and a non-silicide region is provided. An NMOS transistor is formed within the NMOS region and a PMOS transistor is formed within the PMOS region. A stress memorization technique (SMT) layer covering the NMOS region, the PMOS region, and the non-silicide region is formed. The SMT layer is removed from the PMOS region. A stress is transferred from the SMT layer into an N-channel of the NMOS transistor. The SMT layer is removed from the NMOS region, while leaving the SMT layer in the non-silicide region intact. A self-aligned silicidation (SAC) process is performed to form a salicide layer in the NMOS region and the PMOS region.

Abstract: A user equipment and a communication method are provided. The user equipment includes a signal transceiver, a first antenna, a second antenna, a third antenna, and a power amplifier module. The signal transceiver applies a conversion between a baseband signal and a radio frequency signal. The first antenna is a primary antenna for receiving and transmitting RF signals. The second antenna is a diversity antenna for receiving RF signals. The third antenna is a low frequency antenna for transmitting signals in a specific low frequency band. The power amplifier module is electrically connected to the signal transceiver, the first antenna, and the third antenna. The power amplifier module amplifies the RF signal output by the signal transceiver and outputs same to either the first or third antenna.

Abstract: An MIM capacitor includes a semiconductor substrate having a conductor layer thereon, a dielectric layer overlying the semiconductor substrate and the conductor layer, and a first capacitor electrode disposed on the dielectric layer. The first capacitor electrode partially overlaps with the conductor layer when viewed from above. A capacitor dielectric layer is disposed on the first capacitor electrode. A second capacitor electrode is disposed on the capacitor dielectric layer. At least one via is disposed in the dielectric layer and electrically connecting the first capacitor electrode with the conductor layer.

Abstract: A resin composition is provided. The resin composition includes a styrene-acrylonitrile based copolymer of 75 parts by weight to 90 parts by weight and rubber particles of 10 parts by weight to 25 parts by weight. The resin composition includes an oligomer trimer. The oligomer trimer includes at least one monomer unit selected from the group consisting of a styrene based monomer unit and an acrylonitrile based monomer unit. Wherein, a residual acrylonitrile based monomer is less than 5 ppm of the total weight of the resin composition. The ratio of the peak area of acetophenone to the peak area of air for the resin composition as analyzed by a thermal desorption gas chromatography mass spectrometer (TD-GC-MS) is 100 to 300.

Abstract: A signal transmission circuit is provided. A tri-state logic circuit includes an enabling terminal, an input terminal and an output terminal, and is conducted and unconducted when the enabling terminal is at a high and a low state respectively. A pull-up circuit pulls up a voltage level of the output terminal. A first and a second multiplexers respectively output an enabling signal and an output signal to the enabling terminal and the input terminal according to a first status of a selection signal and respectively output a high state signal according to a second status of the selection signal. A selection circuit generates the selection signal having the first status when the voltage level is not larger than a first threshold value, having the second status after the voltage level is larger than the first threshold value and having the first status afterwards.

Abstract: A method for depositing a metal layer on a wafer is disclosed. A PVD chamber is provide having therein a wafer chuck for holding a wafer to be processed, a target situated above the wafer chuck, a magnet positioned on a backside of the target, and a DC power supply for supplying a DC voltage to the target. The target is a metal or a metal alloy having ferromagnetism property. A paste process is performed to the PVD chamber. The paste process includes sequential steps of: admitting a working gas into the PVD chamber; and igniting the working gas in cascade stages. The wafer is then loaded into the PVD chamber and positioned onto the wafer chuck. A deposition process is then performed to deposit a metal layer sputtered from the target onto the wafer.

Abstract: A fitting assembly (100) is provided. The fitting assembly (100) comprises a holder (102) that holds one or more fluidic seal assemblies. The fluidic seal assembly comprises a fitting (104), a ferrule (110) and a tube (112), such as a chromatography column, and optionally comprises a protrusion (118) and a compliant seal material (120). Fluidic connections for a gas chromatography instrument are also provided.