Abstract: Aspects of the invention include systems and methods configured to prevent masquerading service attacks. A non-limiting example computer-implemented method includes sending, from a first server in a cloud environment, a communication request comprising an application programming interface (API) key and a first server identifier to an identity and access management (IAM) server of the cloud environment. The API key can be uniquely assigned by the IAM server to a first component of the first server. The first server receives a credential that includes a token for the first component and sends the credential to a second server. The second server sends the credential, a second server identifier, and an identifier for a second component of the second server to the IAM server. The second server receives an acknowledgment from the IAM server and sends the acknowledgment to the first server.

Abstract: A touch electronic device is provided, which includes: a display unit; a conductive film disposed on the display unit, wherein the conductive film has a surface impedance ranging from 105?/? to 109?/?; and a first polarizer disposed on the conductive film, wherein the conductive film is disposed between the display unit and the first polarizer, wherein a surface impedance of the first polarizer divided by the surface impedance of the conductive film is greater than or equal to 103 and less than or equal to 108.

Abstract: An ESD protection circuit has a driver transistor with a drain that is coupled to an I/O pad of an IC device and a source that is coupled to a first rail of a power supply in the IC device, and a diode that couples the I/O pad to the first rail and that is configured to be reverse-biased when a rated voltage is applied to the I/O pad. The rated voltage lies within a nominal operating range for voltage levels defined for the input/output pad. The ESD protection circuit has a gate pull transistor that couples a gate of the driver transistor to the I/O pad or the first rail. The gate pull transistor may be configured to present a high impedance path between the gate of the driver transistor and the I/O pad or the first rail when the rated voltage is applied to the I/O pad.

Abstract: A reticle thermal expansion calibration method includes exposing a group of wafers and generating a sub-recipe, performing data mining and data parsing to generate a plurality of overlay parameters, extracting a plurality of predetermined parameters from the plurality of overlay parameters, performing a linear regression on each of the predetermined parameters, and generating a coefficient of determination for each of the predetermined parameters.

Abstract: A method of manufacturing a metal mask includes calendering a metal material, so as to form a metal mask substrate, where the metal mask substrate includes a surface and a plurality of grooves formed in the surface, and the grooves all extend in a direction. The surface has at least one sampling region, while at least two grooves are distributed in the sampling region, where an average area ratio of the area of the grooves within the sampling region to the area of the sampling region ranges between 45% and 68%.

Abstract: Provided in the present invention is a preparation method for a nano organometallic carboxylate which effectively solves the problems of a complex washing process, and cumbersome, dangerous and uneconomical preparation of lye in traditional methods for producing organometallic carboxylates. A new method for preparing high-quality organometallic carboxylates by using a carboxylic acid, caustic soda, a metal oxide or a hydroxide as starting materials, and using ball milling to assist reaction thereof. The present invention not only efficiently utilizes lye, it also obtains high-quality organometallic carboxylates, which overcomes the technical prejudice that the prior art uses calcium chloride, sodium chloride and other salts for poor reaction efficiency. The problem in environmental pollution caused by the washing waste liquid in the existing process is fundamentally solved.

Abstract: An ESD protection circuit has a driver transistor with a drain that is coupled to an I/O pad of an IC device and a source that is coupled to a first rail of a power supply in the IC device, and a diode that couples the I/O pad to the first rail and that is configured to be reverse-biased when a rated voltage is applied to the I/O pad. The rated voltage lies within a nominal operating range for voltage levels defined for the input/output pad. The ESD protection circuit has a gate pull transistor that couples a gate of the driver transistor to the I/O pad or the first rail. The gate pull transistor may be configured to present a high impedance path between the gate of the driver transistor and the I/O pad or the first rail when the rated voltage is applied to the I/O pad.

Abstract: Methods and apparatus are provided for eyeglass lens made using a solution casting process. The method may include providing a first soluble polymer solution. The method may include providing a first dye solution including at least one dye. The method may include adding the first dye solution to the first soluble polymer solution to form a first dyed solution. The method may include casting the first dyed solution to form a first film. The method may include providing a second soluble polymer solution. The method may include providing a second dye solution comprising at least one dye. The method may include adding the second dye solution to the second soluble polymer solution to form a second dyed solution. The method may include casting the second dyed solution onto the first film to form a two-layer film. The method may include laminating or casting the two-layer film to the eyeglass lens.

Abstract: A substrate for a semiconductor package includes an array of bonding pads on a first surface of the substrate, and a plurality of raised structures adjacent to at least some of the bonding pads on the first surface of the substrate. The raised structures may be configured to control the height of solder balls contacting the array of bonding pads when the package substrate is mounted onto a support substrate. The raised structures may compensate for a deformation of the package substrate so that the co-planarity of the solder balls may be improved, thereby providing an improved solder connection between the package substrate and the support substrate.

Abstract: A resistive memory device includes a stacked structure and a copper via conductor structure. The stacked structure includes a first electrode, a second electrode, and a variable resistance layer. The second electrode is disposed above the first electrode in a vertical direction, and the variable resistance layer is disposed between the first electrode and the second electrode in the vertical direction. The copper via conductor structure is disposed under the stacked structure. The first electrode includes a tantalum nitride layer directly connected with the copper via conductor structure.

Abstract: A method for processing image data and a system thereof are provided. The method is operated in the system including an encoding system and a decoding system. In the decoding system, multiple image data packages are received from the encoding system. The image data packages include multiple encoded data that are formed by encoding the pixels of an image and the pixels are beforehand rearranged according to an arrangement order. The arrangement order is exemplarily made based on the quantity of encoding circuits of the encoding system. In the decoding system, the encoded data received from the encoding system are sequentially stored in a memory according to the arrangement order. The decoding circuits start to decode the encoded data from an initial code synchronously for enhancing decoding performance. The method can be applied to decoding of high resolution images. The image is reproduced after the decoding process.

Abstract: A method of forming semiconductor device is disclosed. A substrate having a logic circuit region and a memory cell region is provided. A first transistor with a first gate is formed in the logic circuit region and a second transistor with a second gate is formed in the memory cell region. A stressor layer is deposited to cover the first transistor in the logic circuit region and the second transistor in the memory cell region. The first transistor and the second transistor are subjected to an annealing process under the influence of the stressor layer to recrystallize the first gate and the second gate.

Abstract: Aspects include providing isolation between a plurality of containers in a pod that are each executing on a different virtual machine (VM) on a host computer. Providing the isolation includes converting a data packet into a serial format for communicating with the host computer. The converted data packet is sent to a router executing on the host computer. The router determines a destination container in the plurality of containers based at least in part on content of the converted data packet and routes the converted data packet to the destination container.

Abstract: A method of preparing a metal mask substrate includes providing a metal substrate. Next, a gloss is measured and obtained from the surface of the metal substrate. Next, the gloss is determined whether to be within a predetermined range. When the gloss is determined within the predetermined range, a photolithography process is performed to the metal substrate, where the predetermined range is between 90 GU and 400 GU.

Abstract: A semiconductor structure and a method for forming the same are disclosed. The method includes the steps of forming a first dielectric layer on a substrate, forming a plurality of first interconnecting structures in the first dielectric layer, forming at least a trench in the first dielectric layer and between the first interconnecting structures, performing a sputtering deposition process to form a second dielectric layer on the first dielectric layer, wherein the second dielectric layer at least partially seals an air gap in the trench, and forming a third dielectric layer on the second dielectric layer.

Abstract: A semiconductor transistor structure includes a substrate with a first conductivity type, a fin structure grown on the substrate, and a gate on the fin structure. The fin structure includes a first epitaxial layer having a second conductivity type opposite to the first conductivity type, a second epitaxial layer on the first epitaxial layer, and a third epitaxial layer having the second conductivity type on the second epitaxial layer.

Abstract: A method of manufacturing a metal mask includes calendering a metal material, so as to form a metal mask substrate, where the metal mask substrate includes a surface and a plurality of grooves formed in the surface, and the grooves all extend in a direction. The surface has at least one sampling region, while at least two grooves are distributed in the sampling region, where an average area ratio of the area of the grooves within the sampling region to the area of the sampling region ranges between 45% and 68%.

Abstract: A manufacturing method of a contact structure includes the following steps. A substrate is provided, and the substrate includes a first region and a second region. A dielectric layer is formed on the substrate. A photoresist layer is formed on the dielectric layer. An exposure process is performed. The exposure process includes first exposure steps and second exposure steps. Each of the first exposure steps is performed to a part of the first region of the substrate. Each of the second exposure steps is performed to a part of the second region of the substrate. Each of the second exposure steps is performed with a first overlay shift by a first predetermined distance. A develop process is performed for forming openings in the photoresist layer.

Abstract: The present disclosure provides antibodies and antigen-binding fragments thereof that bind specifically to a coronavirus spike protein and methods of using such antibodies and fragments for treating or preventing viral infections (e.g., coronavirus infections).

Abstract: The invention provides an improved semiconductor deposition method, which comprises providing a deposition machine, the deposition machine includes a chamber connected with a pipeline, putting a first wafer into the chamber, and performing a pipeline cleaning step, the pipeline cleaning step includes: cutting off the path between the pipeline and the chamber by turning off a plurality of valve switches, and introducing a gas from the pipeline to move along a first path of the pipeline. Then, a deposition step is performed on the first wafer to deposit a first material layer on the surface of the first wafer, the deposition step includes opening a plurality of valve switches to communicate the path between the pipeline and the chamber, and introducing the gas into the chamber along a second path of the pipeline.