Patents by Inventor Wen Yi

Wen Yi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Anti-SARS-CoV-2-Spike Glycoprotein Antibodies and Antigen-Binding Fragments
    Publication number: 20230348569
    Abstract: The present disclosure provides antibodies and antigen-binding fragments thereof that bind specifically to a coronavirus spike protein and methods of using such antibodies and fragments for treating or preventing viral infections (e.g., coronavirus infections).
    Type: Application
    Filed: June 29, 2023
    Publication date: November 2, 2023
    Inventors: Robert BABB, Alina BAUM, Gang CHEN, Cindy GERSON, Johanna HANSEN, Tammy HUANG, Christos KYRATSOUS, Wen-Yi LEE, Marine MALBEC, Andrew MURPHY, William OLSON, Neil STAHL, George D. YANCOPOULOS
  • Methods Of Mapping Antigen Specificity To Antibody-Secreting Cells
    Publication number: 20230349919
    Abstract: The present disclosure provides antibody capture complexes and methods of capturing a target antibody secreted by an antibody secreting cell.
    Type: Application
    Filed: March 15, 2023
    Publication date: November 2, 2023
    Inventors: Brian Klotz, Seblewongel Asrat, Marion Francis Setliff, Andrea Vecchione, Joseph Cooper Devlin, Wei Keat Lim, Samuel Davis, Hang Song, Jamie Orengo, Gurinder Atwal, Matthew Sleeman, Wen-yi Lee, Gang Chen, Kristel Velez
  • OVERLAY MARK
    Publication number: 20230350310
    Abstract: An overlay mark includes a bottom overlay mark on a bottom level, a middle overlay mark on a middle level, and a top overlay mark on a top level. The bottom overlay mark, the middle overlay mark and the top overlay mark vertically overlap with one another.
    Type: Application
    Filed: May 26, 2022
    Publication date: November 2, 2023
    Applicant: United Semiconductor (Xiamen) Co., Ltd.
    Inventors: Xia Yuan, CHENG HUA WU, WEN YI TAN
  • METHOD FOR MAKING SEMICONDUCTOR DEVICE
    Publication number: 20230352347
    Abstract: A method for fabricating a semiconductor device is disclosed. A substrate having thereon at least one metal-oxide-semiconductor (MOS) transistor is provided. A stress memorization technique (SMT) process is performed. The SMT process includes steps of depositing an SMT film covering the at least one MOS transistor on the substrate, and subjecting the SMT film to a thermal process. A lithographic process and an etching process are performed to form a patterned SMT film. A silicide layer is formed on the MOS transistor. The patterned SMT film acts as a salicide block layer when forming the silicide layer.
    Type: Application
    Filed: May 25, 2022
    Publication date: November 2, 2023
    Applicant: United Semiconductor (Xiamen) Co., Ltd.
    Inventors: LINSHAN YUAN, Guang Yang, YUCHUN GUO, JINJIAN OUYANG, Chin-Chun Huang, WEN YI TAN
  • Semiconductor structure and method for forming the same
    Patent number: 11804403
    Abstract: A semiconductor structure and a method for forming the same are disclosed. The method includes the steps of forming a first dielectric layer on a substrate, forming a plurality of first interconnecting structures in the first dielectric layer, forming at least a trench in the first dielectric layer and between the first interconnecting structures, performing a sputtering deposition process to form a second dielectric layer on the first dielectric layer, wherein the second dielectric layer at least partially seals an air gap in the trench, and forming a third dielectric layer on the second dielectric layer.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: October 31, 2023
    Assignee: United Semiconductor (Xiamen) Co., Ltd.
    Inventors: Ji He Huang, Wen Yi Tan
  • Semiconductor manufacturing process
    Publication number: 20230343651
    Abstract: The invention provides a semiconductor manufacturing process, which comprises the following steps: using a computer system to define plurality of shots on a wafer range, distributing a plurality of observation points in each shot, finding out parts of incomplete shots from all of the shots, calculating the number of observation points in each incomplete shot, eliminating the incomplete shots with the number less than 3 observation points, counting all observation points in the remaining incomplete shots, and deleting a part of observation points until the total number of observation points meets a preset total number, and uniformly distributing all observation points, and performing an overlay measurement step on the remaining observation points to generate an offset vector map.
    Type: Application
    Filed: May 24, 2022
    Publication date: October 26, 2023
    Applicant: United Semiconductor (Xiamen) Co., Ltd.
    Inventors: Dian Han Liu, Yuan-Chi Pai, WEN YI TAN
  • RESISTIVE RANDOM ACCESS MEMORY AND METHOD OF FORMING THE SAME
    Publication number: 20230345848
    Abstract: A resistive random access memory includes a first dielectric layer, a bottom electrode on the first dielectric layer, a variable-resistance layer on the bottom electrode and having a U-shaped cross-sectional profile, a top electrode on the variable-resistance layer and filling a recess in the variable-resistance layer, a second dielectric layer on the first dielectric layer and around the variable-resistance layer and the bottom electrode, and a spacer on the bottom electrode and inserting between the variable-resistance layer and the second dielectric layer.
    Type: Application
    Filed: July 5, 2023
    Publication date: October 26, 2023
    Applicant: United Semiconductor (Xiamen) Co., Ltd.
    Inventors: Dejin KONG, Jinjian OUYANG, Xiang Bo KONG, Wen Yi TAN
  • METHOD OF REMOVING HARD MASK LAYER
    Publication number: 20230317453
    Abstract: A method of removing a hard mask layer includes providing a gate. A hard mask layer covers and contacts a top surface of the gate. Two spacer structures respectively contacts two sides of the gate. Two first spacers are respectively disposed on the two spacer structures. Later, a wet etching process is performed to remove the hard mask layer and the first spacers and keep the spacer structures. An etchant is utilized in the wet etching process. A selective etching ratio of the silicon nitride to silicon oxide of the etchant is more than 90. The etchant includes Si(OH)4. A concentration of Si(OH)4.is greater than or equal to 3.95 ppm and smaller than or equal to 10 ppm.
    Type: Application
    Filed: April 6, 2022
    Publication date: October 5, 2023
    Applicant: United Semiconductor (Xiamen) Co., Ltd.
    Inventors: Sen Mao Feng, Ming Xuan Ren, Shih-Hsien Huang, Wen Yi TAN
  • Manufacturing method of resistive memory device
    Patent number: 11778930
    Abstract: A manufacturing method of a resistive memory device includes the following steps. A first electrode is formed. A first metal oxide layer is formed on the first electrode, and the first metal oxide layer includes first metal atoms. A multilayer insulator structure is formed on the first metal oxide layer. A second metal oxide layer is formed on the multilayer insulator structure. The second metal oxide layer includes second metal atoms, the multilayer insulator structure includes third metal atoms, and each of the third metal atoms is identical to each of the second metal atoms. A second electrode is formed on the second metal oxide layer. The multilayer insulator structure is disposed between the first metal oxide layer and the second metal oxide layer in a vertical direction, and an atomic percent of the third metal atoms in the multilayer insulator structure changes in the vertical direction.
    Type: Grant
    Filed: January 17, 2022
    Date of Patent: October 3, 2023
    Assignee: United Semiconductor (Xiamen) Co., Ltd.
    Inventors: Yuheng Liu, Yunfei Fu, Chih-Chien Huang, Kuo Liang Huang, Wen Yi Tan
  • Structure and formation method of chip package with protective lid
    Patent number: 11764118
    Abstract: A package structure and a formation method of a package structure are provided. The method includes disposing a chip structure over a substrate, and forming a first adhesive element over the substrate. The first adhesive element has a first electrical resistivity. The method also includes forming a second adhesive element over the substrate. The second adhesive element has a second electrical resistivity, and the second electrical resistivity is greater than the first electrical resistivity. The method further includes attaching a protective lid to the substrate through the first adhesive element and the second adhesive element. The protective lid surrounds the chip structure and covers a top surface of the chip structure.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: September 19, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wen-Yi Lin, Kuang-Chun Lee, Chien-Chen Li, Chen-Shien Chen
  • METHOD FOR ALIGNING TO A PATTERN ON A WAFER
    Publication number: 20230288346
    Abstract: A method for aligning to a pattern on a wafer is disclosed. The method includes the steps of obtaining a first inline image from a first sample wafer, obtaining a first contour pattern of an alignment mark pattern from the first inline image, using the first contour pattern to generate a first synthetic image in black and white pixels of only two grayscale levels, using the first synthetic image as a reference to recognize the alignment mark pattern on a tested wafer, and aligning to a tested pattern on the tested wafer according to a position of the alignment mark pattern on the tested wafer and a coordinate information.
    Type: Application
    Filed: May 16, 2023
    Publication date: September 14, 2023
    Applicant: United Semiconductor (Xiamen) Co., Ltd.
    Inventors: Dian Han Liu, Maohua Ren, Yuan-Chi Pai, Wen Yi TAN
  • Semiconductor device having inter-metal dielectric patterns and method for fabricating the same
    Patent number: 11749601
    Abstract: A semiconductor device includes a patterned metal layer on a substrate, via conductors on the patterned metal layer, first inter-metal dielectric (IMD) patterns embedded in the patterned metal layer, and a second IMD pattern surrounding the patterned metal layer. Preferably, the first IMD patterns are between and without overlapping the via conductors in a top view.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: September 5, 2023
    Assignee: United Semiconductor (Xiamen) Co., Ltd.
    Inventors: Bin Guo, Hailong Gu, Chin-Chun Huang, Wen Yi Tan
  • Cooling system in exposure machine and the operation method thereof
    Publication number: 20230266679
    Abstract: The invention provides a cooling system in an exposure machine, which comprises an exposure machine for performing an exposure process of a semiconductor, at least one water storage tank, wherein the water storage tank is filled with cooling water for cooling some components of the exposure machine, a water inlet valve and a water outlet valve, which are connected with the water storage tank, and an automatic controller for controlling the water inlet valve and the water outlet valve to keep the cooling water in the water storage tank at a certain water level.
    Type: Application
    Filed: March 28, 2022
    Publication date: August 24, 2023
    Applicant: United Semiconductor (Xiamen) Co., Ltd.
    Inventors: YiBin Zhou, Chiun-Show Chen, Wen Yi Tan
  • Resistive random access memory and method of forming the same
    Patent number: 11737381
    Abstract: A resistive random access memory includes a bottom electrode, a variable-resistance layer on the bottom electrode and having a U-shaped cross-sectional profile, and a top electrode on the variable-resistance layer and filling a recess in the variable-resistance layer.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: August 22, 2023
    Assignee: United Semiconductor (Xiamen) Co., Ltd.
    Inventors: Dejin Kong, Jinjian Ouyang, Xiang Bo Kong, Wen Yi Tan
  • Anti-SARS-CoV-2-spike glycoprotein antibodies and antigen-binding fragments
    Patent number: 11732030
    Abstract: The present disclosure provides antibodies and antigen-binding fragments thereof that bind specifically to a coronavirus spike protein and methods of using such antibodies and fragments for treating or preventing viral infections (e.g., coronavirus infections).
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: August 22, 2023
    Assignee: Regeneron Pharmaceuticals, Inc.
    Inventors: Robert Babb, Alina Baum, Gang Chen, Cindy Gerson, Johanna Hansen, Tammy Huang, Christos Kyratsous, Wen-Yi Lee, Marine Malbec, Andrew Murphy, William Olson, Neil Stahl, George D. Yancopoulos
  • Semiconductor testkey and test method thereof
    Publication number: 20230260857
    Abstract: The invention provides a semiconductor testkey, which comprises a testkey on a substrate, the testkey comprises a first resistor pattern, a second resistor pattern and a third resistor pattern arranged in a strip, the distance between the first resistor pattern and the second resistor pattern is defined as a first distance, and the distance between the second resistor pattern and the third resistor pattern is defined as a second distance, the first resistor pattern, the second resistor pattern and the third resistor pattern have the same pattern, and the second distance is larger than the first distance.
    Type: Application
    Filed: March 21, 2022
    Publication date: August 17, 2023
    Applicant: United Semiconductor (Xiamen) Co., Ltd.
    Inventors: LINSHAN YUAN, Yi Lu Dai, Guang Yang, JINJIAN OUYANG, Hang Liu, Chin-Chun Huang, WEN YI TAN
  • Semiconductor testkey pattern and test method thereof
    Patent number: 11721599
    Abstract: The invention provides a semiconductor testkey pattern, the semiconductor testkey pattern includes a high density device region and a plurality of resistor pairs surrounding the high density device region, wherein each resistor pair includes two mutually symmetrical resistor patterns.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: August 8, 2023
    Assignee: United Semiconductor (Xiamen) Co., Ltd.
    Inventors: Linshan Yuan, Guang Yang, Jinjian Ouyang, Jiawei Lyu, Chin-Chun Huang, Wen Yi Tan
  • Control circuit and display device
    Patent number: 11721252
    Abstract: A control circuit driving a display panel and including a transmission interface, a charging circuit, an image driving circuit, and a loading management circuit is provided. The transmission interface is configured to be coupled to the display panel. The charging circuit is configured to charge a capacitor. The image driving circuit transforms the voltage of the capacitor into a plurality of driving signals and provides the driving signals to the display panel via the transmission interface. The loading management circuit measures the charge time of the capacitor. In response to the charge time of the capacitor exceeding a threshold value, the loading management circuit asserts a flag to indicate the occurrence of an overload.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: August 8, 2023
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventors: Ta-Chin Chiu, Tu-Yiin Chang, Wen-Yi Li
  • METHOD AND SYSTEM FOR SWITCHING MULTI-FUNCTION MODES
    Publication number: 20230244436
    Abstract: A method and a system for switching multi-function modes applied in an electronic device having a plurality of hardware module functions, and includes receiving input information from a user of the electronic device; obtaining status information of the electronic device; and switching the electronic device to one of the multi-function modes according to the input information and the status information, each of the multi-function modes corresponds to at least one of the plurality of hardware module functions.
    Type: Application
    Filed: August 19, 2022
    Publication date: August 3, 2023
    Inventors: WEN-YI KUO, CHUNG-TSUNG WANG, JU-CHI HSUEH, CHENG-FENG YEH, WEI-CHENG WANG
  • TESTKEY STRUCTURE FOR SEMICONDUCTOR DEVICE
    Publication number: 20230245934
    Abstract: A testkey structure for semiconductor device includes a substrate, a gate structure disposed on the substrate, and a plurality of first dummy gate structures disposed on the substrate and arranged around the gate structure. A bottom surface of the gate structure is lower than bottom surfaces of the first dummy gate structures. A top surface of the gate structure is flush with top surfaces of the first dummy gate structures.
    Type: Application
    Filed: March 30, 2022
    Publication date: August 3, 2023
    Applicant: United Semiconductor (Xiamen) Co., Ltd.
    Inventors: Zhi Xiang Qiu, RONG HE, Hailong Gu, Chin-Chun Huang, WEN YI TAN