Abstract: A conductive strap structure in lateral contact with a top semiconductor layer is formed on an inner electrode of a deep trench capacitor. A cavity overlying the conductive strap structure is filled with a dielectric material to form a dielectric capacitor cap having a top surface that is coplanar with a topmost surface of an upper pad layer. A portion of the upper pad layer is removed to define a line cavity. A fin-defining spacer comprising a material different from the material of the dielectric capacitor cap and the upper pad layer is formed around the line cavity by deposition of a conformal layer and an anisotropic etch. The upper pad layer is removed, and the fin-defining spacer is employed as an etch mask to form a semiconductor fin that laterally contacts the conductive strap structure. An access finFET is formed employing two parallel portions of the semiconductor fin.

Abstract: A conductive strap structure in lateral contact with a top semiconductor layer is formed on an inner electrode of a deep trench capacitor. A cavity overlying the conductive strap structure is filled a dielectric material to form a dielectric capacitor cap having a top surface that is coplanar with a topmost surface of an upper pad layer. A semiconductor mandrel in lateral contact with the dielectric capacitor cap is formed. The combination of the dielectric capacitor cap and the semiconductor mandrel is employed as a protruding structure around which a fin-defining spacer is formed. The semiconductor mandrel is removed, and the fin-defining spacer is employed as an etch mask in an etch process that etches a lower pad layer and the top semiconductor layer to form a semiconductor fin that laterally wraps around the conductive strap structure. An access finFET is formed employing two parallel portions of the semiconductor fin.

Abstract: FinFETs are merged together by a metal. The method of manufacturing the FinFETs include forming a plurality of fin bodies on a substrate and merging the fin bodies with a metal. The method further includes implanting source and drain regions through the metal.

Abstract: An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.

Abstract: A method including providing fins etched from a semiconductor substrate and covered by an oxide layer and a nitride layer, the oxide layer being located between the fins and the nitride layer, removing a portion of the fins to form an opening, forming a dielectric spacer on a sidewall of the opening, and filling the opening with a fill material, wherein a top surface of the fill material is substantially flush with a top surface of the nitride layer. The method may further include forming a deep trench capacitor in-line with one of the fins, removing the nitride layer to form a gap between the fins and the fill material, wherein the fill material has re-entrant geometry extending over the gap, and removing the re-entrant geometry and causing the gap between the fins and the fill material to widen.

Abstract: A co-processing module communicates with at least one remote device via an Ethernet communication link. The co-processing module includes a first processor that executes an application of the host device via a first operating system, the application including socket system calls. A second processor executes a second operating system to execute a transport control protocol/Internet protocol stack, an Ethernet driver, and an Ethernet media access control layer, to bidirectionally communicate first data via the Ethernet communication link and further to bidirectionally communicate the first data with the first processor. The first processor bidirectionally communicates the first data with the application via the socket system calls.

Abstract: The present invention relates a technique of liquid crystal display, especially to an alignment film applied to a substrate of a liquid crystal display. The alignment film includes a plurality of alignment molecules formed by polymerizing monomers having at least a photosensitive group, and has formula e as wherein the component A and/or the component B in formula e comprise(s) terphenyl. The present invention further provides a method of fabricating the alignment film and a liquid crystal display using the same. Due to the photosensitive group of the monomers, the plurality of alignment molecules can be formed with an appropriated rate, and the alignment film formed thereby has homogeneity. Therefore, the optic quality and overall performance of the liquid crystal display are enhanced.

Abstract: The present invention relates a technique of liquid crystal display, especially to an alignment film applied to a substrate of a liquid crystal display. The alignment film includes a plurality of alignment molecules including polyamic acid and/or polyimide and a plurality of photo-sensitive molecules including terphenyl and/or substituted terphenyl, wherein a mass ratio of the plurality of alignment molecules to the plurality of photo-sensitive molecules is 3˜7%:0.0002˜2%. The present invention further provides a method of fabricating the alignment film and a liquid crystal display using the same. Due to the photosensitive group of the monomers, the plurality of alignment molecules can be formed with an appropriated rate, and the alignment film formed thereby has homogeneity. Therefore, the optic quality and overall performance of the liquid crystal display are enhanced.

Abstract: A dual epitaxial integration process for FinFET devices. First and second pluralities of fins and gates are formed, with some of the fins and gates being for NFETs and some of the fins and gates being for PFETs. A first layer of a hard mask material selected from the group consisting of titanium nitride, tungsten nitride, tantalum nitride, amorphous carbon and titanium carbide is deposited over the NFETs and PFETs. The hard mask material is removed from one of the NFETs and PFETs and a first source and drain material is epitaxially deposited on the fins. A second layer of the hard mask material is deposited over the NFETs and PFETs. The first and second layers of the hard mask material are removed from the other of the NFETs and PFETs and a second source and drain material is deposited on the fins.

Abstract: Devices and methods for sensing current are described herein. One device (100) includes a base member (102) haying a first leg (104, 106) and a second leg (104, 106), the legs (104, 106) defining an angle (108) therebetween, a first magnetic current sensor (110, 112) coupled to the base member (102) and positioned at a first location in a plane bisecting the angle (108), and a second magnetic current sensor (110, 112) coupled to the base member (102) and positioned at a second location in the plane bisecting the angle (108).

Abstract: A manufacturing method of a liquid crystal panel, including: manufacturing a first substrate and a second substrate; mixing sealant with alloy particles having low melting points, coating the mixture on the first substrate, and dropping liquid crystals on the first substrate; and bonding the first substrate and the second substrate, heating the two bonded substrates, and then cooling the substrates. Therefore, the manufacturing method can prevent the present golden balls from piercing the common electrodes and further prevent the short circuit of the circuit on the substrate, which improves the yield rate of the liquid crystal panel. Additionally, since the alloy particles are small sized, after the separate alloy particles melt, contacting points between the alloy particles and the common electrodes are increased.

Abstract: A field effect transistor device includes a gate stack disposed on a substrate a first contact portion disposed on a first distal end of the gate stack, a second contact portion disposed on a second distal end of the gate stack, the first contact portion disposed a distance (d) from the second contact portion, and a third contact portion having a width (w) disposed in a source region of the device, the distance (d) is greater than the width (w).

Abstract: The invention provides a vertical alignment liquid crystal panel, which includes a first glass substrate, a second glass substrate, and a liquid crystal layer that includes negative liquid crystal containing liquid crystal molecules having a pre-tilt angle of 0°-7°, chiral agent, and a photo- or heat-polymerizable polymer. The first glass substrate includes a liquid crystal panel driving circuit, which includes a gate driver, a source driver, a plurality of gate lines, and a plurality of data lines. The gate lines and the data lines define a plurality of pixel units, each of which includes a thin-film transistor, a common electrode, and a pixel electrode. The source driver applies a driving voltage of 0-6V via the thin-film transistor to the pixel electrode. The present invention improves elastic energy between the liquid crystal molecules and thus avoids image sticking caused by long term displaying of the same image at the same location.

Abstract: A dual epitaxial integration process for FinFET devices. First and second pluralities of fins and gates are formed, with some of the fins and gates being for NFETs and some of the fins and gates being for PFETs. A first layer of a hard mask material selected from the group consisting of titanium nitride, tungsten nitride, tantalum nitride, amorphous carbon and titanium carbide is deposited over the NFETs and PFETs. The hard mask material is removed from one of the NFETs and PFETs and a first source and drain material is epitaxially deposited on the fins. A second layer of the hard mask material is deposited over the NFETs and PFETs. The first and second layers of the hard mask material are removed from the other of the NFETs and PFETs and a second source and drain material is deposited on the fins.

Abstract: A power conversion system is disclosed including a DC bus for receiving DC power, a power converter for converting the DC power to AC power, and a controller. The controller includes an active power regulator for generating a phase angle command signal, a reactive power regulator for generating a voltage magnitude command, and an active power (P) and reactive power (Q) decoupling unit for decoupling interaction between the active and reactive power regulators. The PQ decoupling unit includes an active power compensation element and a reactive power compensation element. The active power compensation element is used for generating a phase angle compensation signal based on a reactive power error signal, to compensate the phase angle command signal. The reactive power compensation element is used for generating a voltage magnitude compensation signal based on an active power error signal, to compensate the voltage magnitude command signal.

Abstract: Clubheads for iron-type golf clubs are disclosed. An example clubhead has a front including an iron-type face. The front is forged of a material such as C455 or 17-4 PH stainless steel. A heel, sole, toe, and top-line are situated rearwardly of the face, and a rear is situated rearwardly of the heel, sole, toe, and top-line. The face has one or more of: a COR of at least 0.8, a thickness, in a thinnest portion of the face, of no greater than 2.0 mm, and an area of less than 3000 mm2.

Abstract: At least one dielectric pad layer is formed on a semiconductor-on-insulator (SOI) substrate. A deep trench is formed in the SOI substrate, and a combination of an outer electrode, a node dielectric, and an inner electrode are formed such that the top surface of the inner electrode is recessed below the top surface of a buried insulator layer of the SOI substrate. Selective epitaxy is performed to fill a cavity overlying the inner electrode with an epitaxial semiconductor material portion. A top semiconductor material layer and the epitaxial semiconductor material portion are patterned to form a fin structure including a portion of the top semiconductor material layer and a portion of the epitaxial semiconductor material portion. The epitaxial semiconductor material portion functions as a conductive strap structure between the inner electrode and a semiconductor device to be formed on the fin structure.

Abstract: Devices, methods, and systems for sensing current are described herein. One device includes a first electrode, a second electrode, and a tunneling magnetoresistance material between the first and second electrodes.

Abstract: The present invention discloses a liquid crystal composition for a polymer stabilized vertical alignment liquid crystal display (PS-VA LCD) and a liquid crystal display panel thereof; the liquid crystal composition comprises at least one type of negative liquid crystal material, a type of stabilizer and one or more type of reactive monomers; the structural formula of the reactive monomer consists of one benzene ring, two benzene rings or one naphthalene ring, the structure of two benzene rings is formed by connecting the two benzene rings directly or indirectly with a group, at least one polymerizable group is connected directly to the benzene ring and naphthalene ring, and at least one of polymerizable groups is an acrylate group. Reaction rate of the reactive monomer and uniformity of polymer bumps are improved by selecting polymerizable groups of the reactive monomer and controlling the content thereof to effectively solve quality issues of panels.

Abstract: An exemplary power conversion system is disclosed including a DC bus for receiving DC power; a line side converter electrically coupled to the DC bus for converting the DC power to AC power; and a voltage source controller to provide control signals to enable the line side converter to regulate the AC power. The voltage source controller comprises a signal generator to generate the control signals based at least in part on a power command signal and a power feedback signal. The voltage source controller further comprises a current limiter to, during a transient event, limit the control signals based at least in part on an electrical current threshold. The voltage source controller further comprises a voltage limiter to, during the transient event, limit the control signals based at least in part on a DC bus voltage feedback signal and a DC boundary voltage threshold.