Patents by Inventor Yanli Zhang

Yanli Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9455267
    Abstract: A monolithic three dimensional NAND string includes a plurality of control gate electrodes extending substantially parallel to a major surface of a substrate in at least one active region, a plurality of semiconductor channels having at least one end portion of each of the plurality of semiconductor channels extending substantially perpendicular to the major surface of the substrate, at least one memory film located between each of the plurality of control gate electrodes and each respective semiconductor channel of the plurality of semiconductor channels, and at least one first slit trench extending substantially perpendicular to the major surface of the substrate. Each of the plurality of control gate electrodes has a nonlinear side wall adjacent to the at least one first slit trench in the at least one active region.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: September 27, 2016
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yanli Zhang, Johann Alsmeier
  • Patent number: 9418625
    Abstract: Systems, devices and methods are described including determining a display type and a display mode, preparing stereoscopic image content in response to the display mode, where preparing the stereoscopic image content includes storing a full resolution left image and a full resolution right image in memory, and determining a display refresh rate in response to at least a content frame rate of the stereoscopic image content. The stereoscopic image content may then be processed for display according to the display type, the display refresh rate, and a power policy.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: August 16, 2016
    Assignee: INTEL CORPORATION
    Inventor: Yanli Zhang
  • Publication number: 20160233227
    Abstract: A stack including an alternating plurality of first material layers and second material layers is provided. A memory opening is formed and at least a contiguous semiconductor material portion including a semiconductor channel is formed therein. The contiguous semiconductor material portion includes an amorphous or polycrystalline semiconductor material. A metallic material portion is provided at a bottom surface of the semiconductor channel, at a top surface of the semiconductor channel, or on portions of an outer sidewall surface of the semiconductor channel. An anneal is performed to induce diffusion of a metal from the metallic material portion through the semiconductor channel, thereby inducing conversion of the amorphous or polycrystalline semiconductor material into a crystalline semiconductor material. The crystalline semiconductor material has a relatively large grain size due to the catalytic crystallization process, and can provide enhanced charge carrier mobility.
    Type: Application
    Filed: February 11, 2015
    Publication date: August 11, 2016
    Inventors: Yanli ZHANG, Raghuveer S. MAKALA, Johann ALSMEIER
  • Patent number: 9406569
    Abstract: A semiconductor-on-insulator (SOI) substrate comprises a bulk semiconductor substrate, a buried insulator layer formed on the bulk substrate and an active semiconductor layer formed on the buried insulator layer. Impurities are implanted near the interface of the buried insulator layer and the active semiconductor layer. A diffusion barrier layer is formed between the impurities and an upper surface of the active semiconductor layer. The diffusion barrier layer prevents the impurities from diffusing therethrough.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: August 2, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Gregory G. Freeman, Kam Leung Lee, Chengwen Pei, Geng Wang, Yanli Zhang
  • Publication number: 20160211023
    Abstract: Methods for performing memory operations on a memory array that includes inverted NAND strings are described. The memory operations may include erase operations, read operations, programming operations, program verify operations, and erase verify operations. An inverted NAND string may include a string of inverted floating gate transistors or a string of inverted charge trap transistors. In one embodiment, an inverted floating gate transistor may include a tunneling layer between a floating gate of the inverted floating gate transistor and a control gate of the inverted floating gate transistor. The arrangement of the tunneling layer between the floating gate and the control gate allows electrons to be added to or removed from the floating gate via F-N tunneling between the floating gate and the control gate. The inverted NAND string may be formed above a substrate and oriented such that the inverted NAND string is orthogonal to the substrate.
    Type: Application
    Filed: March 28, 2016
    Publication date: July 21, 2016
    Applicant: SANDISK TECHNOLOGIES INC.
    Inventors: Yanli Zhang, George Samachisa, Johann Alsmeier, Jian Chen
  • Publication number: 20160211272
    Abstract: A first blocking dielectric layer is formed in a memory opening through a stack of an alternating plurality of material layers and insulator layers. A spacer with a bottom opening is formed over the first blocking dielectric layer by deposition of a conformal material layer and an anisotropic etch. A horizontal portion of the first blocking dielectric layer at a bottom of the memory opening can be etched by an isotropic etch process that minimizes overetch into the substrate. An optional additional blocking dielectric layer, at least one charge storage element, a tunneling dielectric, and a semiconductor channel can be sequentially formed in the memory opening to provide a three-dimensional memory stack.
    Type: Application
    Filed: January 20, 2015
    Publication date: July 21, 2016
    Inventors: Sateesh Koka, Senaka Kanakamedala, Raghuveer S. Makala, Rahul Sharangpani, Yanli Zhang, Yao-Sheng Lee, George Matamis
  • Patent number: 9397107
    Abstract: A method of making a three dimensional NAND string includes providing a stack of alternating first material layers and second material layers over a substrate. The method further includes forming a front side opening in the stack, forming a tunnel dielectric in the front side opening, forming a semiconductor channel in the front side opening over the tunnel dielectric and forming a back side opening in the stack. The method also includes selectively removing the second material layers through the back side opening to form back side recesses between adjacent first material layers, forming a metal charge storage layer in the back side opening and in the back side recesses and forming discrete charge storage regions in the back side recesses by removing the metal charge storage layer from the back side opening and selectively recessing the metal charge storage layer in the back side recesses.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: July 19, 2016
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Raghuveer S. Makala, Yao-Sheng Lee, Senaka Krishna Kanakamedala, Yanli Zhang, George Matamis, Johann Alsmeier
  • Patent number: 9397111
    Abstract: A fabrication process for a 3D memory structure provides a single crystal silicon channel for a drain-side select gate (SGD) transistor using a laser thermal anneal (LTA). The 3D memory structure includes a stack formed from an array of alternating conductive and dielectric layers. A NAND string is formed by filling a memory hole with memory films, including a charge trapping material, a tunnel oxide and a polysilicon channel. In one case, a separate oxide and polysilicon forms the SGD transistor gate oxide and channel respectively, where LTA is performed on the polysilicon. In another case, the same oxide and polysilicon are used for the SGD transistor and the memory cells. A portion of the polysilicon is converted to single crystal silicon. A back side of the single crystal silicon is subject to epitaxial growth and thermal oxidation via a void in a control gate layer.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: July 19, 2016
    Assignee: SanDisk Technologies LLC
    Inventors: Murshed Chowdhury, Yanli Zhang, Jin Liu, Raghuveer S Makala, Johann Alsmeier
  • Publication number: 20160204117
    Abstract: Alignment between memory openings through multiple tier structures can be facilitated employing a temporary landing pad. The temporary landing pad can have a greater area than the horizontal cross-sectional area of a first memory opening through a first tier structure including a first alternating stack of first insulating layers and first spacer material layers. An upper portion of a first memory film is removed, and a sidewall of an insulating cap layer that defines the first memory opening can be laterally recessed to form a recessed cavity. A sacrificial fill material is deposited in the recessed cavity to form a sacrificial fill material portion, which functions as the temporary landing pad for a second memory opening that is subsequently formed through a second tier structure including second insulating layers and second spacer material layers. A memory stack structure can be formed through the first and second tier structures.
    Type: Application
    Filed: March 24, 2016
    Publication date: July 14, 2016
    Inventors: Jin Liu, Yanli Zhang, Murshed Chowdhury, Raghuveer S. Makala, Johann Alsmeier
  • Patent number: 9379132
    Abstract: Methods of making monolithic three-dimensional memory devices include performing a first etch to form a memory opening and a second etch using a different etching process to remove a damaged portion of the semiconductor substrate from the bottom of the memory opening. A single crystal semiconductor material is formed over the substrate in the memory opening using an epitaxial growth process. Additional embodiments include improving the quality of the interface between the semiconductor channel material and the underlying semiconductor layers in the memory opening which may be damaged by the bottom opening etch, including forming single crystal semiconductor channel material by epitaxial growth from the bottom surface of the memory opening and/or oxidizing surfaces exposed to the bottom opening etch and removing the oxidized surfaces prior to forming the channel material. Monolithic three-dimensional memory devices formed by the embodiment methods are also disclosed.
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: June 28, 2016
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Sateesh Koka, Raghuveer S. Makala, Yanli Zhang, Senaka Kanakamedala, Rahul Sharangpani, Yao-Sheng Lee, George Matamis
  • Publication number: 20160163729
    Abstract: A memory stack structure includes a cavity including a back gate electrode, a back gate dielectric, a semiconductor channel, and at least one charge storage element. In one embodiment, a line trench can be filled with a memory film layer, and a plurality of semiconductor channels can straddle the line trench. The back gate electrode can extend along the lengthwise direction of the line trench. In another embodiment, an isolated memory opening overlying a patterned conductive layer can be filled with a memory film, and the back gate electrode can be formed within a semiconductor channel and on the patterned conductive layer. A dielectric cap portion electrically isolates the back gate electrode from a drain region. The back gate electrode can be employed to bias the semiconductor channel, and to enable sensing of multinary bits corresponding to different amounts of electrical charges stored in a memory cell.
    Type: Application
    Filed: December 9, 2014
    Publication date: June 9, 2016
    Inventors: Yanli ZHANG, Johann ALSMEIER, Yingda DONG, Akira MATSUDAIRA
  • Publication number: 20160163389
    Abstract: A memory stack structure includes a cavity including a back gate electrode, a back gate dielectric, a semiconductor channel, and at least one charge storage element. In one embodiment, a line trench can be filled with a memory film layer, and a plurality of semiconductor channels can straddle the line trench. The back gate electrode can extend along the lengthwise direction of the line trench. In another embodiment, an isolated memory opening overlying a patterned conductive layer can be filled with a memory film, and the back gate electrode can be formed within a semiconductor channel and on the patterned conductive layer. A dielectric cap portion electrically isolates the back gate electrode from a drain region. The back gate electrode can be employed to bias the semiconductor channel, and to enable sensing of multinary bits corresponding to different amounts of electrical charges stored in a memory cell.
    Type: Application
    Filed: December 9, 2014
    Publication date: June 9, 2016
    Inventors: Yanli ZHANG, Johann ALSMEIER, Yinda DONG, Akira MATSUDAIRA
  • Patent number: 9356014
    Abstract: Semiconductor structures and methods of manufacture are disclosed herein. Specifically, disclosed herein are methods of manufacturing a high-voltage metal-oxide-semiconductor field-effect transistor and respective structures. A method includes forming a field-effect transistor (FET) on a substrate in a FET region, forming a high-voltage FET (HVFET) on a dielectric stack over a over lightly-doped diffusion (LDD) drain in a HVFET region, and forming an NPN on the substrate in an NPN region.
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: May 31, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: William F. Clark, Jr., Qizhi Liu, John J. Pekarik, Yun Shi, Yanli Zhang
  • Patent number: 9355727
    Abstract: A memory stack structure includes a cavity including a back gate electrode, a back gate dielectric, a semiconductor channel, and at least one charge storage element. In one embodiment, a line trench can be filled with a memory film layer, and a plurality of semiconductor channels can straddle the line trench. The back gate electrode can extend along the lengthwise direction of the line trench. In another embodiment, an isolated memory opening overlying a patterned conductive layer can be filled with a memory film, and the back gate electrode can be formed within a semiconductor channel and on the patterned conductive layer. A dielectric cap portion electrically isolates the back gate electrode from a drain region. The back gate electrode can be employed to bias the semiconductor channel, and to enable sensing of multinary bits corresponding to different amounts of electrical charges stored in a memory cell.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: May 31, 2016
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Yanli Zhang, Johann Alsmeier, Yinda Dong, Akira Matsudaira
  • Publication number: 20160125788
    Abstract: Techniques related to image dithering are described herein. The techniques include receiving an image to be displayed at a display device and entering a content adaptive backlight control mode. The image is dithered during the content adaptive backlight control mode. The dithering is disabled during a panel self-refresh mode.
    Type: Application
    Filed: November 4, 2014
    Publication date: May 5, 2016
    Inventors: Yanli Zhang, Seh Kwa
  • Patent number: 9330763
    Abstract: Methods for performing memory operations on a memory array that includes inverted NAND strings are described. The memory operations may include erase operations, read operations, programming operations, program verify operations, and erase verify operations. An inverted NAND string may include a string of inverted floating gate transistors or a string of inverted charge trap transistors. In one embodiment, an inverted floating gate transistor may include a tunneling layer between a floating gate of the inverted floating gate transistor and a control gate of the inverted floating gate transistor. The arrangement of the tunneling layer between the floating gate and the control gate allows electrons to be added to or removed from the floating gate via F-N tunneling between the floating gate and the control gate. The inverted NAND string may be formed above a substrate and oriented such that the inverted NAND string is orthogonal to the substrate.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: May 3, 2016
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Yanli Zhang, George Samachisa, Johann Alsmeier, Jian Chen
  • Patent number: 9331090
    Abstract: A NAND device has at least a 3×3 array of vertical NAND strings in which the control gate electrodes are continuous in the array and do not have an air gap or a dielectric filled trench in the array. The NAND device is formed by first forming a lower select gate level having separated lower select gates, then forming plural memory device levels containing a plurality of NAND string portions, and then forming an upper select gate level over the memory device levels having separated upper select gates.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: May 3, 2016
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Johann Alsmeier, Raghuveer S. Makala, Xiying Costa, Yanli Zhang
  • Publication number: 20160118397
    Abstract: Methods of making monolithic three-dimensional memory devices include performing a first etch to form a memory opening and a second etch using a different etching process to remove a damaged portion of the semiconductor substrate from the bottom of the memory opening. A single crystal semiconductor material is formed over the substrate in the memory opening using an epitaxial growth process. Additional embodiments include improving the quality of the interface between the semiconductor channel material and the underlying semiconductor layers in the memory opening which may be damaged by the bottom opening etch, including forming single crystal semiconductor channel material by epitaxial growth from the bottom surface of the memory opening and/or oxidizing surfaces exposed to the bottom opening etch and removing the oxidized surfaces prior to forming the channel material. Monolithic three-dimensional memory devices formed by the embodiment methods are also disclosed.
    Type: Application
    Filed: October 24, 2014
    Publication date: April 28, 2016
    Inventors: Sateesh KOKA, Raghuveer S. MAKALA, Yanli ZHANG, Senaka KANAKAMEDALA, Rahul SHARANGPANI, Yao-Sheng LEE, George MATAMIS
  • Patent number: 9305932
    Abstract: A method of making a monolithic three dimensional NAND string includes providing a first stack of alternating first material layers and second material layers over a major surface of a substrate. The first material layers include first silicon oxide layers, the second material layers include second silicon oxide layers, and the first silicon oxide layers have a different etch rate from the second silicon oxide when exposed to the same etching medium. The first stack includes a back side opening, a front side opening, and at least a portion of a floating gate layer, a tunnel dielectric and a semiconductor channel located in the front side opening. The method also includes selectively removing the first material layers through the back side opening to form back side control gate recesses between adjacent second material layers.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: April 5, 2016
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Senaka Krishna Kanakamedala, Yanli Zhang, Raghuveer S. Makala, Yao-Sheng Lee, Johann Alsmeier, George Matamis
  • Patent number: 9305849
    Abstract: A monolithic three dimensional NAND string includes a semiconductor channel, an end part of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate, a charge storage material layer located between the plurality of control gate electrodes and the semiconductor channel, a tunnel dielectric located between the charge storage material layer and the semiconductor channel, and a blocking dielectric containing a plurality of clam-shaped portions each having two horizontal portions connected by a vertical portion. Each of the plurality of control gate electrodes are located at least partially in an opening in the clam-shaped blocking dielectric, and a plurality of discrete cover oxide segments embedded in part of a thickness of the charge storage material layer and located between the blocking dielectric and the charge storage material layer.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: April 5, 2016
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Masanori Tsutsumi, Shigehiro Fujino, Sateesh Koka, Senaka Kanakamedala, Yanli Zhang, Raghuveer S. Makala, Rahul Sharangpani, George Matamis, Wei Zhao