Patents by Inventor Yasuhiro Okamoto
Yasuhiro Okamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10243070Abstract: A property of a semiconductor device (high electron mobility transistor) is improved. A semiconductor device having a buffer layer, a channel layer, an electron supply layer, a mesa type cap layer, a source electrode, a drain electrode and a gate insulating film covering the cap layer, and a gate electrode formed on the gate insulating film, is configured as follows. The cap layer and the gate electrode are separated from each other by the gate insulating film, and side surfaces of the cap layer, the side surfaces being closer to the drain electrode and the source electrode, have tapered shapes. For example, a taper angle (?1) of the side surface of the cap layer (mesa portion) is equal to or larger than 120 degrees. By this configuration, a TDDB life can be effectively improved, and variation in an ON-resistance can be effectively suppressed.Type: GrantFiled: March 20, 2017Date of Patent: March 26, 2019Assignee: Renesas Electronics CorporationInventors: Hironobu Miyamoto, Yasuhiro Okamoto, Hiroshi Kawaguchi, Tatsuo Nakayama
-
Publication number: 20190074174Abstract: Characteristics of a semiconductor device are improved. A method of manufacturing a semiconductor device of the invention includes a step of forming a gate insulating film over a nitride semiconductor layer. The step includes steps of forming a crystalline Al2O3 film on the nitride semiconductor layer, forming a SiO2 film on the Al2O3 film, and forming an amorphous Al2O3 film on the SiO2 film. The step further includes steps of performing heat treatment on the amorphous Al2O3 to crystallize the amorphous Al2O3, thereby forming a crystalline Al2O3 film, and forming a SiO2 film on the crystalline Al2O3 film. In this way, since a film stack, which is formed by alternately stacking the crystalline Al2O3 films and the SiO2 films from a bottom side, is used as the gate insulating film, threshold voltage can be cumulatively increased.Type: ApplicationFiled: August 2, 2018Publication date: March 7, 2019Inventors: Yasuhiro OKAMOTO, Takashi IDE
-
Publication number: 20190051740Abstract: In a manufacturing method of a semiconductor device according to the present invention, a buffer layer including a first nitride semiconductor layer, a channel layer including a second nitride semiconductor layer, and a barrier layer including a third nitride semiconductor layer are sequentially laminated, and a fourth nitride semiconductor layer is further laminated thereover. Then, a laminate of a gate insulating film and a gate electrode is formed over a first region of the fourth nitride semiconductor layer, and a silicon nitride film is formed over the fourth nitride semiconductor layer and the laminate. By bringing the fourth nitride semiconductor layers on both sides of the gate electrode into contact with the silicon nitride film in this way, the function of suppressing 2DEG can be lowered, and the 2DEG that has been eliminated after the formation of the fourth nitride semiconductor layer can be restored.Type: ApplicationFiled: July 5, 2018Publication date: February 14, 2019Inventor: Yasuhiro OKAMOTO
-
Patent number: 10199476Abstract: A mesa portion of a semiconductor device, which includes a channel base layer formed of a first nitride semiconductor layer, a channel layer formed of a second nitride semiconductor layer, a barrier layer formed of a third nitride semiconductor layer, a mesa-type fourth nitride semiconductor layer, a gate insulating film that covers the mesa portion, and a gate electrode formed over the gate insulating film, is used as a co-doped layer. The mesa portion is used as the co-doped layer, so that interface charges generated at an interface between the gate insulating film and the mesa portion can be cancelled by p-type impurity or n-type impurity in the co-doped layer and a threshold potential can be improved. Further, the fourth nitride semiconductor layer is n-type until the gate insulating film is formed, and the fourth nitride semiconductor layer is made neutral or p-type after the gate insulating film is formed.Type: GrantFiled: December 14, 2017Date of Patent: February 5, 2019Assignee: Renesas Electronics CorporationInventors: Tatsuo Nakayama, Hironobu Miyamoto, Yasuhiro Okamoto
-
Patent number: 10188265Abstract: An insertion apparatus includes an elongated inserting section having a curving section, an input section which is provided in an operating section, receives an arbitrary input to curve the curving section in a movable range including a first range that includes the neutral input position and a second range that has an operation amount from the neutral input position exceeding the first range, a first actuator, a detecting section, a second actuator which gives a force towards the neutral position to the input section, and a control section which operates the first actuator and the second actuator, when the input amount to the input section is in the second range, thereby giving a force to the input section so that an input amount to the input section is in the first range.Type: GrantFiled: December 18, 2015Date of Patent: January 29, 2019Assignee: OLYMPUS CORPORATIONInventor: Yasuhiro Okamoto
-
Patent number: 10172600Abstract: An insertion apparatus according to an aspect of the present invention includes: an insertion portion to be inserted into a subject; a bending operation apparatus to be moved by an operator to input an operation instruction; a bending drive section that generates a drive force based on the movement of the bending operation apparatus; a pulling member to be pulled by the drive force from the bending drive section; a bending portion provided in the insertion portion, the bending portion being connected to the pulling member and being bent upon the pulling member being pulled; and a haptic section that connects the pulling member and the bending operation apparatus via an elastic portion.Type: GrantFiled: May 20, 2014Date of Patent: January 8, 2019Assignee: OLYMPUS CORPORATIONInventors: Yasuhiro Okamoto, Hiroki Moriyama, Hiroaki Miyoshi, Yutaka Masaki
-
Publication number: 20190006500Abstract: Characteristics of a semiconductor device are improved. A semiconductor device includes a sequential stack of a buffer layer, a channel layer, and a barrier layer, and includes a mesa part including a fourth nitride semiconductor layer formed over the stack, and a side part formed on both sides of the mesa part and including a thin film part of the fourth nitride semiconductor layer. Generation of 2DEG is suppressed below the mesa part while being unsuppressed below the side part. In this way, the side part that disables the 2DEG suppression effect is provided on an end portion of the mesa part, thereby a distance from an end portion of the side part to the gate electrode is increased, making it possible to suppress leakage caused by a current path passing through an undesired channel formed between a gate insulating film and the mesa part.Type: ApplicationFiled: May 22, 2018Publication date: January 3, 2019Inventors: Takehiro UEDA, Yasuhiro OKAMOTO
-
Publication number: 20180342589Abstract: Characteristics of a semiconductor device using a nitride semiconductor are improved. A semiconductor device of the present invention includes a buffer layer, a channel layer, a barrier layer, a mesa-type 2DEG dissolving layer, a source electrode, a drain electrode, a gate insulating film formed on the mesa-type 2DEG dissolving layer, and an overlying gate electrode. The gate insulating film of the semiconductor device includes a sputtered film formed on the mesa-type 2DEG dissolving layer and a CVD film formed on the sputtered film. The sputtered film is formed in a non-oxidizing atmosphere by a sputtering process using a target including an insulator. This makes it possible to reduce positive charge amount at a MOS interface and in gate insulating film and increase a threshold voltage, and thus improve normally-off characteristics.Type: ApplicationFiled: April 30, 2018Publication date: November 29, 2018Applicant: Renesas Electronics CorporationInventors: Hironobu MIYAMOTO, Tatsuo NAKAYAWA, Yasuhiro OKAMOTO, Atsushi TSUBOI
-
Patent number: 10134908Abstract: A MISFET is formed to include: a co-doped layer that is formed over a substrate and has an n-type semiconductor region and a p-type semiconductor region; and a gate electrode formed over the co-doped layer via a gate insulation film. The co-doped layer contains a larger amount of Mg, a p-type impurity, than that of Si, an n-type impurity. Accordingly, the carriers (electrons) resulting from the n-type impurities (herein, Si) in the co-doped layer are canceled by the carriers (holes) resulting from p-type impurities (herein, Mg), thereby allowing the co-doped layer to serve as the p-type semiconductor region. Mg can be inactivated by introducing hydrogen into, of the co-doped layer, a region where the n-type semiconductor region is to be formed, thereby allowing the region to serve as the n-type semiconductor region. By thus introducing hydrogen into the co-doped layer, the p-type semiconductor region and the n-type semiconductor region can be formed in the same layer.Type: GrantFiled: November 29, 2016Date of Patent: November 20, 2018Assignee: Renesas Electronics CorporationInventors: Tatsuo Nakayama, Hironobu Miyamoto, Yasuhiro Okamoto
-
Patent number: 10117567Abstract: An endoscope includes a bending section being disposed in an insertion section, a plurality of towing members disposed in the insertion section and in an operation section from the bending section, a disk member turnably provided in the operation section and configured to turn to tow and loosen the plurality of towing members, the plurality of towing members being suspended in an outer circumference of the disk member, operation members turnably disposed in the operation section and configured to turn the disk member to bend the bending section, and a turning shaft configured to turnably axially support the disk member and the operation members with respect to the operation section in a position decentered to the distal end side by a predetermined distance d with respect to a center of the disk member in an initial state in which the bending section is linear.Type: GrantFiled: August 31, 2016Date of Patent: November 6, 2018Assignee: OLYMPUS CORPORATIONInventor: Yasuhiro Okamoto
-
Patent number: 10105038Abstract: An insertion apparatus includes: a flexible tube; an electric driving source arranged on a proximal end side of the flexible tube; a driven portion arranged on a distal end of the flexible tube; and a single driving force transmitting member inserted in the flexible tube and formed by being wound in a coil shape. For the driving force transmitting member, first torsional rigidity in a first rotating state of being rotated in a direction of being wound in the coil shape is set higher than second torsional rigidity in a second rotating state of being rotated in an opposite direction; and the driven portion performs a first motion by the first rotating state and performs a second motion requiring a larger amount of force than the first motion by the second rotating state.Type: GrantFiled: April 5, 2017Date of Patent: October 23, 2018Assignee: OLYMPUS CORPORATIONInventor: Yasuhiro Okamoto
-
Publication number: 20180235440Abstract: An endoscope includes a flexible tube section including coiled tubes, a motor disposed on a proximal side of the flexible tube section, a driving force transmission unit disposed on a distal side of the flexible tube section, and a drive shaft provided inside the flexible tube section along a long axis, the drive shaft being caused to perform rotation around the long axis by a driving force of the motor and to transmit the rotation of the motor to the driving force transmission unit, where torsional resistance of the flexible tube section around the long axis is set higher than torsional resistance between a relay gear of the motor and a drive gear of the driving force transmission unit through the drive shaft.Type: ApplicationFiled: April 23, 2018Publication date: August 23, 2018Applicant: OLYMPUS CORPORATIONInventor: Yasuhiro OKAMOTO
-
Publication number: 20180233590Abstract: In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a short channel effect). For example, when applying the present invention to a GaN-type field effect transistor, besides GaN of a channel layer, a composition-modulated (composition-gradient) AlGaN layer in which aluminum composition reduces toward a top gradually or stepwise is used as a buffer layer (hetero buffer).Type: ApplicationFiled: March 16, 2018Publication date: August 16, 2018Inventors: Takashi Inoue, Tatsuo Nakayama, Yuji Ando, Yasuhiro Murase, Kazuki Ota, Hironobu Miyamoto, Katsumi Yamanoguchi, Naotaka Kuroda, Akio Wakejima, Yasuhiro Okamoto
-
Patent number: 10050142Abstract: The characteristics of a semiconductor device are improved. A semiconductor device has a potential fixed layer containing a p type impurity, a channel layer, and a barrier layer, formed over a substrate, and a gate electrode arranged in a trench penetrating through the barrier layer, and reaching some point of the channel layer via a gate insulation film. Source and drain electrodes are formed on opposite sides of the gate electrode. The p type impurity-containing potential fixed layer has an inactivated region containing an inactivating element such as hydrogen between the gate and drain electrodes. Thus, while raising the p type impurity (acceptor) concentration of the potential fixed layer on the source electrode side, the p type impurity of the potential fixed layer is inactivated on the drain electrode side. This can improve the drain-side breakdown voltage while providing a removing effect of electric charges by the p type impurity.Type: GrantFiled: October 20, 2017Date of Patent: August 14, 2018Assignee: Renesas Electronics CorporationInventors: Tatsuo Nakayama, Hironobu Miyamoto, Ichiro Masumoto, Yasuhiro Okamoto, Shinichi Miyake, Hiroshi Kawaguchi
-
Publication number: 20180219089Abstract: A mesa portion of a semiconductor device, which includes a channel base layer formed of a first nitride semiconductor layer, a channel layer formed of a second nitride semiconductor layer, a barrier layer formed of a third nitride semiconductor layer, a mesa-type fourth nitride semiconductor layer, a gate insulating film that covers the mesa portion, and a gate electrode formed over the gate insulating film, is used as a co-doped layer. The mesa portion is used as the co-doped layer, so that interface charges generated at an interface between the gate insulating film and the mesa portion can be cancelled by p-type impurity or n-type impurity in the co-doped layer and a threshold potential can be improved. Further, the fourth nitride semiconductor layer is n-type until the gate insulating film is formed, and the fourth nitride semiconductor layer is made neutral or p-type after the gate insulating film is formed.Type: ApplicationFiled: December 14, 2017Publication date: August 2, 2018Applicant: Renesas Electronics CorporationInventors: Tatsuo NAKAYAMA, Hironobu MIYAMOTO, Yasuhiro OKAMOTO
-
Patent number: 10014403Abstract: A semiconductor device includes a first nitride semiconductor layer formed over a substrate, a second nitride semiconductor layer formed over the first nitride semiconductor layer, a third nitride semiconductor layer formed over the second nitride semiconductor layer, a fourth nitride semiconductor layer formed over the third nitride semiconductor layer, a trench that penetrates the fourth nitride semiconductor layer and reaches as far as the third nitride semiconductor layer, a gate electrode disposed by way of a gate insulation film in the trench, a first electrode and a second electrode formed respectively over the fourth nitride semiconductor layer on both sides of the gate electrode, and a coupling portion for coupling the first electrode and the first nitride semiconductor layer.Type: GrantFiled: February 21, 2017Date of Patent: July 3, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Tatsuo Nakayama, Hironobu Miyamoto, Yasuhiro Okamoto, Yoshinao Miura, Takashi Inoue
-
Publication number: 20180151377Abstract: A semiconductor device includes a first nitride semiconductor layer formed over a substrate, a second nitride semiconductor layer formed over the first nitride semiconductor layer and having a band gap wider than a band gap of the first nitride semiconductor layer, a trench penetrating through the second nitride semiconductor layer and reaching an inside of the first nitride semiconductor layer, a gate electrode placed in the trench over a gate insulating film, and a first electrode and a second electrode formed over the second nitride semiconductor layer on both sides of the gate electrode, respectively.Type: ApplicationFiled: January 29, 2018Publication date: May 31, 2018Inventors: Takashi Inoue, Tatsuo Nakayama, Yasuhiro Okamoto, Hiroshi Kawaguchi, Toshiyuki Takewaki, Nobuhiro Nagura, Takayuki Nagai, Yoshinao Miura, Hironobu Miyamoto
-
Patent number: 9985108Abstract: An electrode comes in ohmic contact with an AlGaN layer. A semiconductor device SD has a nitride semiconductor layer GN2, and an AlxGa(1-x)N layer AGN (hereinafter referred to as “AlGaN layer AGN), and Al electrodes DE, SE. in the AlGaN layer AGN, 0<x?0.2 is satisfied. Also, both of a concentration of a p-type impurity and a concentration of an n-type impurity in the AlGaN layer AGN are 1×1016 cm?3 or lower. In this example, the p-type impurity is exemplified by, for example, Be, C, and Mg, and the n-type impurity is exemplified by Si, S, and Se. Also, the Al electrodes DE and SE are connected to the AlGaN layer AGN. Because a composition ratio of Al is limited to the above-mentioned range, the Al electrodes DE and SE are brought into ohmic contact with the AlGaN layer AGN.Type: GrantFiled: July 14, 2014Date of Patent: May 29, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Tatsuo Nakayama, Masaaki Kanazawa, Yasuhiro Okamoto, Takashi Inoue, Hironobu Miyamoto, Ryohei Nega
-
Patent number: 9984884Abstract: A method of manufacturing a semiconductor device includes forming a first nitride semiconductor layer, forming thereover a second nitride semiconductor layer having a band gap wider than that of the first nitride semiconductor layer, and thereby forming a stacked body, etching the stacked body with a first film placed over the stacked body and including a first opening portion as a mask to form a trench penetrating through the second nitride semiconductor layer and reaching an inside of the first nitride semiconductor layer, causing an end portion of the first film to retreat from an end portion of the trench, forming a second film over the first film including the inside of the trench, and forming a gate electrode over the second film.Type: GrantFiled: December 20, 2016Date of Patent: May 29, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Takashi Inoue, Tatsuo Nakayama, Yasuhiro Okamoto, Hiroshi Kawaguchi, Toshiyuki Takewaki, Nobuhiro Nagura, Takayuki Nagai, Yoshinao Miura, Hironobu Miyamoto
-
Patent number: 9954087Abstract: In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a short channel effect). For example, when applying the present invention to a GaN-type field effect transistor, besides GaN of a channel layer, a composition-modulated (composition-gradient) AlGaN layer in which aluminum composition reduces toward a top gradually or stepwise is used as a buffer layer (hetero buffer).Type: GrantFiled: August 27, 2014Date of Patent: April 24, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Takashi Inoue, Tatsuo Nakayama, Yuji Ando, Yasuhiro Murase, Kazuki Ota, Hironobu Miyamoto, Katsumi Yamanoguchi, Naotaka Kuroda, Akio Wakejima, Yasuhiro Okamoto