Patents by Inventor Yasuhiro Okamoto
Yasuhiro Okamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9831339Abstract: The characteristics of a semiconductor device are improved. A semiconductor device has a potential fixed layer containing a p type impurity, a channel layer, and a barrier layer, formed over a substrate, and a gate electrode arranged in a trench penetrating through the barrier layer, and reaching some point of the channel layer via a gate insulation film. Source and drain electrodes are formed on opposite sides of the gate electrode. The p type impurity-containing potential fixed layer has an inactivated region containing an inactivating element such as hydrogen between the gate and drain electrodes. Thus, while raising the p type impurity (acceptor) concentration of the potential fixed layer on the source electrode side, the p type impurity of the potential fixed layer is inactivated on the drain electrode side. This can improve the drain-side breakdown voltage while providing a removing effect of electric charges by the p type impurity.Type: GrantFiled: June 26, 2017Date of Patent: November 28, 2017Assignee: Renesas Electronics CorporationInventors: Tatsuo Nakayama, Hironobu Miyamoto, Ichiro Masumoto, Yasuhiro Okamoto, Shinichi Miyake, Hiroshi Kawaguchi
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Publication number: 20170294538Abstract: The characteristics of a semiconductor device are improved. A semiconductor device has a potential fixed layer containing a p type impurity, a channel layer, and a barrier layer, formed over a substrate, and a gate electrode arranged in a trench penetrating through the barrier layer, and reaching some point of the channel layer via a gate insulation film. Source and drain electrodes are formed on opposite sides of the gate electrode. The p type impurity-containing potential fixed layer has an inactivated region containing an inactivating element such as hydrogen between the gate and drain electrodes. Thus, while raising the p type impurity (acceptor) concentration of the potential fixed layer on the source electrode side, the p type impurity of the potential fixed layer is inactivated on the drain electrode side. This can improve the drain-side breakdown voltage while providing a removing effect of electric charges by the p type impurity.Type: ApplicationFiled: June 26, 2017Publication date: October 12, 2017Applicant: Renesas Electronics CorporationInventors: Tatsuo NAKAYAMA, Hironobu MIYAMOTO, Ichiro MASUMOTO, Yasuhiro OKAMOTO, Shinichi MIYAKE, Hiroshi KAWAGUCHI
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Publication number: 20170288046Abstract: A property of a semiconductor device (high electron mobility transistor) is improved. A semiconductor device having a buffer layer, a channel layer, an electron supply layer, a mesa type cap layer, a source electrode, a drain electrode and a gate insulating film covering the cap layer, and a gate electrode formed on the gate insulating film, is configured as follows. The cap layer and the gate electrode are separated from each other by the gate insulating film, and side surfaces of the cap layer, the side surfaces being closer to the drain electrode and the source electrode, have tapered shapes. For example, a taper angle (?1) of the side surface of the cap layer (mesa portion) is equal to or larger than 120 degrees. By this configuration, a TDDB life can be effectively improved, and variation in an ON-resistance can be effectively suppressed.Type: ApplicationFiled: March 20, 2017Publication date: October 5, 2017Applicant: Renesas Electronics CorporationInventors: Hironobu MIYAMOTO, Yasuhiro OKAMOTO, Hiroshi KAWAGUCHI, Tatsuo NAKAYAMA
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Patent number: 9763564Abstract: The introducing apparatus comprises the operating section, which is easy to grip and easy to operate, mounted therein by providing the dial of the operation element to perform a bending operation of the bending section and a part of the rotary mechanism alone while avoiding an operation range of the operating section for fingers of a gripping hand.Type: GrantFiled: January 7, 2016Date of Patent: September 19, 2017Assignee: OLYMPUS CORPORATIONInventors: Yasuhiro Okamoto, Keijiro Omoto
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Patent number: 9761682Abstract: In order to improve the characteristics of a semiconductor device including: a channel layer and a barrier layer formed above a substrate; and a gate electrode arranged over the barrier layer via a gate insulating film, the semiconductor device is configured as follows. A silicon nitride film is provided over the barrier layer between a source electrode and the gate electrode, and is also provided over the barrier layer between a drain electrode and the gate electrode GE. The surface potential of the barrier layer is reduced by the silicon nitride film, thereby allowing two-dimensional electron gas to be formed. Thus, by selectively forming two-dimensional electron gas only in a region where the silicon nitride film is formed, a normally-off operation can be performed even if a trench gate structure is not adopted.Type: GrantFiled: December 7, 2015Date of Patent: September 12, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Yasuhiro Okamoto
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Patent number: 9748225Abstract: The ringing of a switching waveform of a semiconductor device is restrained. For example, an interconnect (L5) is laid which functions as a source of a power transistor (Q3) and a cathode of a diode (D4), and further functioning as a drain of a power transistor (Q4) and an anode of a diode (D3). In other words, a power transistor and a diode coupled to this power transistor in series are formed in the same semiconductor chip; and further an interconnect functioning as a drain of the power transistor and an interconnect functioning as an anode of the diode are made common to each other. This structure makes it possible to decrease a parasite inductance between the power transistor and the diode coupled to each other in series.Type: GrantFiled: December 16, 2015Date of Patent: August 29, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yoshinao Miura, Hironobu Miyamoto, Yasuhiro Okamoto
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Patent number: 9722062Abstract: The characteristics of a semiconductor device are improved. A semiconductor device has a potential fixed layer containing a p type impurity, a channel layer, and a barrier layer, formed over a substrate, and a gate electrode arranged in a trench penetrating through the barrier layer, and reaching some point of the channel layer via a gate insulation film. Source and drain electrodes are formed on opposite sides of the gate electrode. The p type impurity-containing potential fixed layer has an inactivated region containing an inactivating element such as hydrogen between the gate and drain electrodes. Thus, while raising the p type impurity (acceptor) concentration of the potential fixed layer on the source electrode side, the p type impurity of the potential fixed layer is inactivated on the drain electrode side. This can improve the drain-side breakdown voltage while providing a removing effect of electric charges by the p type impurity.Type: GrantFiled: August 27, 2015Date of Patent: August 1, 2017Assignee: Renesas Electronics CorporationInventors: Tatsuo Nakayama, Hironobu Miyamoto, Ichiro Masumoto, Yasuhiro Okamoto, Shinichi Miyake, Hiroshi Kawaguchi
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Publication number: 20170202440Abstract: An insertion apparatus includes: a flexible tube; an electric driving source arranged on a proximal end side of the flexible tube; a driven portion arranged on a distal end of the flexible tube; and a single driving force transmitting member inserted in the flexible tube and formed by being wound in a coil shape. For the driving force transmitting member, first torsional rigidity in a first rotating state of being rotated in a direction of being wound in the coil shape is set higher than second torsional rigidity in a second rotating state of being rotated in an opposite direction; and the driven portion performs a first motion by the first rotating state and performs a second motion requiring a larger amount of force than the first motion by the second rotating state.Type: ApplicationFiled: April 5, 2017Publication date: July 20, 2017Applicant: OLYMPUS CORPORATIONInventor: Yasuhiro OKAMOTO
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Publication number: 20170186880Abstract: A MISFET is formed to include: a co-doped layer that is formed over a substrate and has an n-type semiconductor region and a p-type semiconductor region; and a gate electrode formed over the co-doped layer via a gate insulation film. The co-doped layer contains a larger amount of Mg, a p-type impurity, than that of Si, an n-type impurity. Accordingly, the carriers (electrons) resulting from the n-type impurities (herein, Si) in the co-doped layer are canceled by the carriers (holes) resulting from p-type impurities (herein, Mg), thereby allowing the co-doped layer to serve as the p-type semiconductor region. Mg can be inactivated by introducing hydrogen into, of the co-doped layer, a region where the n-type semiconductor region is to be formed, thereby allowing the region to serve as the n-type semiconductor region. By thus introducing hydrogen into the co-doped layer, the p-type semiconductor region and the n-type semiconductor region can be formed in the same layer.Type: ApplicationFiled: November 29, 2016Publication date: June 29, 2017Applicant: Renesas Electronics CorporationInventors: Tatsuo NAKAYAMA, Hironobu MIYAMOTO, Yasuhiro OKAMOTO
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Publication number: 20170172386Abstract: An endoscope operation mechanism includes: a dial operating an endoscope function; a detection sensor that has a sensor rotation shaft to which rotation of a dial rotation shaft of the dial is transmitted and detects the rotation amount, and that outputs an electrical signal in accordance with the detected rotation amount to a control portion performing driving control of a driving source of the endoscope function; an initial position reversion mechanism applying a rotational force to the dial rotation shaft in an opposite direction to the direction in which the dial rotation shaft is rotated, to thereby cause the rotational position of the dial to return to an initial position; and a switching mechanism switchable between a first state in which a rotational force from the initial position reversion mechanism is applied to the dial rotation shaft, and a second state in which the rotational force is not applied.Type: ApplicationFiled: March 2, 2017Publication date: June 22, 2017Applicant: OLYMPUS CORPORATIONInventor: Yasuhiro OKAMOTO
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Publication number: 20170162683Abstract: A semiconductor device includes a first nitride semiconductor layer formed over a substrate, a second nitride semiconductor layer formed over the first nitride semiconductor layer, a third nitride semiconductor layer formed over the second nitride semiconductor layer, a fourth nitride semiconductor layer formed over the third nitride semiconductor layer, a trench that penetrates the fourth nitride semiconductor layer and reaches as far as the third nitride semiconductor layer, a gate electrode disposed by way of a gate insulation film in the trench, a first electrode and a second electrode formed respectively over the fourth nitride semiconductor layer on both sides of the gate electrode, and a coupling portion for coupling the first electrode and the first nitride semiconductor layer.Type: ApplicationFiled: February 21, 2017Publication date: June 8, 2017Inventors: Tatsuo NAKAYAMA, Hironobu MIYAMOTO, Yasuhiro OKAMOTO, Yoshinao MIURA, Takashi INOUE
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Patent number: 9660045Abstract: The characteristics of a semiconductor device are improved. A semiconductor device is formed so as to have a channel layer formed over a substrate, a barrier layer, a trench penetrating through the barrier layer in an opening region, and reaching some point of the channel layer, a gate electrode arranged in the trench via a gate insulation film, and an insulation film formed over the barrier layer outside the opening region. Then, the insulation film has a lamination structure of a Si-rich silicon nitride film, and a N-rich silicon nitride film situated thereunder. Thus, the upper layer of the insulation film is set as the Si-rich silicon nitride film. This enables the improvement of the breakdown voltage, and further, enables the improvement of the etching resistance. Whereas, the lower layer of the insulation film is set as the N-rich silicon nitride film. This can suppress collapse.Type: GrantFiled: March 24, 2016Date of Patent: May 23, 2017Assignee: Renesas Electronics CorporationInventors: Takashi Inoue, Toshiyuki Takewaki, Tatsuo Nakayama, Yasuhiro Okamoto, Hironobu Miyamoto
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Patent number: 9636001Abstract: An introduction device applies urging force linearly generated by a spring to a nut portion screwed to a drive shaft to convert the urging force to the rotation direction of the drive shaft. This conversion returns an RL operation dial provided at the end of the drive shaft in a direction opposite to the rotation direction in which the RL operation dial is operated, and then returns the RL operation dial to an original neutral position.Type: GrantFiled: February 4, 2015Date of Patent: May 2, 2017Assignee: OLYMPUS CORPORATIONInventor: Yasuhiro Okamoto
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Publication number: 20170103898Abstract: A method of manufacturing a semiconductor device includes forming a first nitride semiconductor layer, forming thereover a second nitride semiconductor layer having a band gap wider than that of the first nitride semiconductor layer, and thereby forming a stacked body, etching the stacked body with a first film placed over the stacked body and including a first opening portion as a mask to form a trench penetrating through the second nitride semiconductor layer and reaching an inside of the first nitride semiconductor layer, causing an end portion of the first film to retreat from an end portion of the trench, forming a second film over the first film including the inside of the trench, and forming a gate electrode over the second film.Type: ApplicationFiled: December 20, 2016Publication date: April 13, 2017Inventors: Takashi INOUE, Tatsuo Nakayama, Yasuhiro Okamoto, Hiroshi Kawaguchi, Toshiyuki Takewaki, Nobuhiro Nagura, Takayuki Nagai, Yoshinao Miura, Hironobu Miyamoto
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Patent number: 9601609Abstract: Characteristics of a semiconductor device are improved. A semiconductor device includes a potential fixing layer, a channel underlayer, a channel layer, and a barrier layer formed above a substrate, a trench that penetrates the barrier layer and reaches as far as a middle of the channel layer, a gate electrode disposed by way of an insulation film in the trench, and a source electrode and a drain electrode formed respectively over the barrier layer on both sides of the gate electrode. A coupling portion inside the through hole that reaches as far as the potential fixing layer electrically couples the potential fixing layer and the source electrode. This can reduce fluctuation of the characteristics such as a threshold voltage and an on-resistance.Type: GrantFiled: December 12, 2014Date of Patent: March 21, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Tatsuo Nakayama, Hironobu Miyamoto, Yasuhiro Okamoto, Yoshinao Miura, Takashi Inoue
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Publication number: 20170054014Abstract: The semiconductor device includes a trench that penetrates a barrier layer, and reaches a middle portion of a channel layer among an n+ layer, an n-type layer, a p-type layer, the channel layer, and the barrier layer which are formed above a substrate, a gate electrode arranged within the groove through a gate insulating film, and a source electrode and a drain electrode which are formed above the barrier layer on both sides of the gate electrode. The n-type layer and the drain electrode are electrically coupled by a connection portion that reaches the n+ layer. The p-type layer and the source electrode are electrically coupled by a connection portion that reaches the p-type layer. A diode including a p-type layer and an n-type layer is provided between the source electrode and the drain electrode, to thereby prevent the breaking of an element caused by an avalanche breakdown.Type: ApplicationFiled: November 8, 2016Publication date: February 23, 2017Inventors: Tatsuo Nakayama, Hironobu Miyamoto, Yasuhiro Okamoto, Yoshinao Miura, Takashi Inoue
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Publication number: 20170028945Abstract: A wire harness to be installed in a vehicle includes an electric wire and a protective tube that protects the electric wire. The electric wire is provided at the lower part of a vehicle body of the vehicle and the protective tube covers the electric wire and includes ferromagnetic materials.Type: ApplicationFiled: July 27, 2016Publication date: February 2, 2017Inventors: Osamu Kimura, Yoshinori Matsushita, Yasuhiro Okamoto
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Patent number: 9559183Abstract: To provide a semiconductor device having improved characteristics. The semiconductor device has a substrate and thereon a buffer layer, a channel layer, a barrier layer, a trench penetrating therethrough and reaching the inside of the channel layer, a gate electrode placed in the trench via a gate insulating film, and drain and source electrodes on the barrier layer on both sides of the gate electrode. The gate insulating film has a first portion made of a first insulating film and extending from the end portion of the trench to the side of the drain electrode and a second portion made of first and second insulating films and placed on the side of the drain electrode relative to the first portion. The on resistance can be reduced by decreasing the thickness of the first portion at the end portion of the trench on the side of the drain electrode.Type: GrantFiled: May 6, 2014Date of Patent: January 31, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Takashi Inoue, Tatsuo Nakayama, Yasuhiro Okamoto, Hiroshi Kawaguchi, Toshiyuki Takewaki, Nobuhiro Nagura, Takayuki Nagai, Yoshinao Miura, Hironobu Miyamoto
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Publication number: 20170005189Abstract: A semiconductor device includes a first semiconductor layer, a second semiconductor layer formed over the first semiconductor layer, a third semiconductor layer formed over the second semiconductor layer, a gate electrode formed over the third semiconductor layer, and a gate insulating film formed between the third semiconductor layer and the gate electrode. The second semiconductor layer includes an Aly?1-yN layer (? includes Ga or In, and 0?y<1), and the third semiconductor layer includes an Alz?1-zN layer (0?z<1). y of the Aly?1-yN layer forming the second semiconductor layer increases from the third semiconductor layer to the first semiconductor layer at least in a region under the gate electrode. There is a relationship “z>y” at an interface between the second nitride semiconductor layer and the third nitride semiconductor layer.Type: ApplicationFiled: September 14, 2016Publication date: January 5, 2017Inventors: Yasuhiro OKAMOTO, Tatsuo NAKAYAMA, Takashi INOUE, Hironobu MIYAMOTO
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Patent number: 9536978Abstract: To improve performance of a semiconductor device. For example, on the assumption that a superlattice layer is inserted between a buffer layer and a channel layer, a concentration of acceptors introduced into nitride semiconductor layers forming a part of the superlattice layer is higher than a concentration of acceptors introduced into nitride semiconductor layers forming the other part of the superlattice layer. That is, the concentration of acceptors introduced into the nitride semiconductor layers having a small band gap is higher than the concentration of acceptors introduced into the nitride semiconductor layers having a large band gap.Type: GrantFiled: March 5, 2014Date of Patent: January 3, 2017Assignee: Renesas Electronics CorporationInventors: Tatsuo Nakayama, Hironobu Miyamoto, Yasuhiro Okamoto, Ryohei Nega, Masaaki Kanazawa, Takashi Inoue