Abstract: The present disclosure generally relates to processing speech or text using rank-reduced token representation. In one example process, speech input is received. A sequence of candidate words corresponding to the speech input is determined. The sequence of candidate words includes a current word and one or more previous words. A vector representation of the current word is determined from a set of trained parameters. A number of parameters in the set of trained parameters varies as a function of one or more linguistic characteristics of the current word. Using the vector representation of the current word, a probability of a next word given the current word and the one or more previous words is determined. A text representation of the speech input is displayed based on the determined probability.

Abstract: A light-emitting device includes a substrate having a first surface and an opposing second surface, and an epitaxial structure having a first surface and an opposing second surface. The second surface of the epitaxial structure is positioned in proximity with the first surface of the substrate. The light-emitting device includes a first metal layer having a first surface and an opposing second surface. The light-emitting device further includes at least one light confinement structure configured to confine light produced within the epitaxial structure. The at least one light confinement structure provides a low-refraction index boundary that confines the light in a mesa structure that is at least partially surrounded by the at least one light confinement structure. The at least one light confinement structure can also be arranged to create separate confinement regions to serve as bandwidth enhancement coupled cavities for the active region of the light-emitting device.

Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a high voltage metal-oxide-semiconductor (HVMOS) device is integrated with a high voltage junction termination (HVJT) device. In some embodiments, a first drift well and a second drift well are in a substrate. The first and second drift wells border in a ring-shaped pattern and have a first doping type. A peripheral well is in the substrate and has a second doping type opposite the first doping type. The peripheral well surrounds and separates the first and second drift wells. A body well is in the substrate and has the second doping type. Further, the body well overlies the first drift well and is spaced from the peripheral well by the first drift well. A gate electrode overlies a junction between the first drift well and the body well.

Abstract: A method for hoisting and transporting assemblies in an underground nuclear power plant, the method including: 1) pouring concrete onto a reactor cavern to form a rock anchor beam; hoisting a circular bridge crane to the reactor cavern through a hoist shaft on a top of the reactor cavern; mounting the circular bridge crane on the rock anchor beam by using a truck crane; 2) installing a containment cylinder and a track beam of a polar crane in the reactor cavern using the circular bridge crane; hoisting a gantry crane on one end of a polar crane girder and sending the polar crane girder to the reactor cavern; hoisting the other end of the polar crane girder using the circular bridge crane; allowing the polar crane girder to be horizontal; and mounting the polar crane girder on the track beam.

Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a high voltage metal-oxide-semiconductor (HVMOS) device is integrated with a high voltage junction termination (HVJT) device. In some embodiments, a first drift well and a second drift well are in a substrate. The first and second drift wells border in a ring-shaped pattern and have a first doping type. A peripheral well is in the substrate and has a second doping type opposite the first doping type. The peripheral well surrounds and separates the first and second drift wells. A body well is in the substrate and has the second doping type. Further, the body well overlies the first drift well and is spaced from the peripheral well by the first drift well. A gate electrode overlies a junction between the first drift well and the body well.

Abstract: The present disclosure describes a leakage handling device and a method for handling a fluid leakage in a semiconductor manufacturing apparatus. The semiconductor manufacturing apparatus can include a lithography apparatus with a chuck configured to hold a substrate, and a photoresist feeder configured to dispatch a coating material on one or more areas of the substrate. The photoresist feeder can include a photoresist cartridge configured to output the coating material, a conduit fluidly connected to the photoresist cartridge, and a fluid leakage handling device disposed above the chuck, where the conduit can be configured to fluidly transport the coating material and circulate a coolant and the fluid leakage handling device can be configured to detect a fluid leakage from the conduit.

Abstract: A circuit and method of measuring capacitance are disclosed. The capacitance measuring circuit includes an integrator circuit, a first control circuit, a second control circuit and a processor circuit. The capacitance measuring method includes steps of: using a current source and a charging/discharging time to generate a first charge amount related to a second charge amount of a capacitor to be detected; generating a third charge amount and generating a fourth charge amount according to the first charge amount and the third charge amount; generating a fifth charge amount and generating a remaining charge amount according to the fifth charge amount and fourth charge amount; using an integrator to convert the remaining charge amount into a first voltage and generating a judging result according to whether the first voltage meets a second voltage; and calculating the judging result to obtain a capacitance variation of the capacitor to be detected.

Abstract: A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET.

Abstract: Provided herein are particles assemblies including a shell surrounding a core. The shell includes a particle-stabilizing random copolymer. The core includes a core random copolymer. The particle assemblies have a biomimetic design in which the polymeric components containing discrete chemical and biological functionalities are designed to spontaneously self-assemble into particles. Also provided herein are random copolymers having conjugated therapeutic agents that can be cleaved from the copolymers by an enzyme or water.

Abstract: An interconnect structure includes a dielectric layer and a conductor embedded in the dielectric layer. A top surface of the conductor is flush with a top surface of the dielectric layer. A cobalt cap layer is deposited on the top surface of the conductor. A nitrogen-doped cobalt layer is disposed on the cobalt cap layer.

Abstract: A semiconductor structure and method for manufacturing thereof are provided. The semiconductor structure includes a silicon substrate having a first surface, a III-V layer on the first surface of the silicon substrate and over a first active region, and an isolation region in a portion of the III-V layer extended beyond the first active region. The first active region is in proximal to the first surface. The method includes the following operations. A silicon substrate having a first device region and a second device region is provided, a first active region is defined in the first device region, a III-V layer is formed on the silicon substrate, an isolation region is defined across a material interface in the III-V layer by an implantation operation, and an interconnect penetrating through the isolation region is formed.

Abstract: This disclosure relates to techniques for a wireless device to indicate a preferred bandwidth part and duty cycle in a cellular communication system. A wireless device and a cellular base station may establish a radio resource control connection. The wireless device may transmit an indication of a preferred bandwidth part, or a preferred communication duty cycle, or both, to the cellular base station. The cellular base station may select a bandwidth part, or communication duty cycle, or both, based at least in part on the indication provided by the wireless device, and may transmit an indication of the selected bandwidth part, communication duty cycle, or both, to the wireless device. The cellular base station and the wireless device may perform cellular communication using the selected bandwidth part, communication duty cycle, or both.

Abstract: A device includes a first transistor having a first source terminal, a first drain terminal, and a first gate terminal; and a second transistor having a second source terminal, a second drain terminal, and a second gate terminal. The second source terminal is coupled to the first gate terminal and the first source terminal is coupled to the second gate terminal. The first transistor has a first threshold voltage, and the second transistor has a second threshold voltage different from the first threshold voltage.

Abstract: Certain embodiments of a semiconductor device and a method of forming a semiconductor device comprise forming a high-k gate dielectric layer over a short channel semiconductor fin. A work function metal layer is formed over the high-k gate dielectric layer. A seamless metal fill layer is conformally formed over the work function metal layer.

Abstract: In one general aspect, a device can include a first trench disposed in a semiconductor region, a second trench disposed in the semiconductor region, and a recess disposed in the semiconductor region between the first trench and the second trench. The recess has a sidewall and a bottom surface. The device also includes a Schottky interface along a sidewall of the recess and the bottom surface of the recess excludes a Schottky interface.

Abstract: A resin composition is provided. The resin composition includes a styrene-acrylonitrile based copolymer of 75 parts by weight to 90 parts by weight and rubber particles of 10 parts by weight to 25 parts by weight. The resin composition includes an oligomer trimer. The oligomer trimer includes at least one monomer unit selected from the group consisting of a styrene based monomer unit and an acrylonitrile based monomer unit. Wherein, a residual acrylonitrile based monomer is less than 5 ppm of the total weight of the resin composition. The ratio of the peak area of acetophenone to the peak area of air for the resin composition as analyzed by a thermal desorption gas chromatography mass spectrometer (TD-GC-MS) is 100 to 300.

Abstract: Embodiments of the present disclosure pertain to network based machine learning generated simulations. In one embodiment, the present disclosure includes a computer implemented method comprising sending first code comprising a programmable calculator from a server system to a client system across a network. A data request is sent to a database, the data request configured to retrieve data from the database comprising a plurality of fields and a target field. The retrieved data is processed using a machine learning algorithm to produce a weight for each field of the plurality of fields and a scoring data structure. The fields and the scoring data structure are sent to the client system across the network. A user selects values for the plurality of fields and the programmable calculator is configured based on the scoring data structure to generate a simulated value for the target field based on the user selected values.

Abstract: A trench metal-oxide-semiconductor field-effect transistor (MOSFET) device comprises an active cell area including a plurality of superjunction trench power MOSFETs, and a Schottky diode area including a plurality of Schottky diodes formed in the drift region having the superjunction structure.