Abstract: A method of forming a transistor comprises disposing a planar platform (or pedestal, or layer) of silicon atop a support structure of oxide which is atop a substrate; forming gate structures both atop and beneath the planar platform; and forming source and drain diffusions within the planar platform. The gate structures which are formed beneath the planar platform may smaller than the planar platform, and may be aligned with the gate structures which are formed atop the planar platform. A transistor formed by the method is also disclosed.

Abstract: An RSD FET device with a recessed channel is formed with a raised silicon sources and drains and a gate electrode structure formed on an SOI structure (a Si layer formed on a substrate) by the steps as follows. Form a SiGe layer over the Si layer and a RSD layer over the SiGe. Etch through the RSD layer and the SiGe to form a gate electrode space reaching down the Si layer. Form a pair of RSD regions separated by the gate electrode space. Line the walls of the gate electrode space with an internal etch stop layer and an inner sidewall spacers. Form a gate electrode inside the inner sidewall spacers on the Si layer. Form external sidewall spacers adjacent to the gate electrode between the RSD regions next to the inner sidewall spacers, and dope the RSD regions, whereby a recessed channel is formed in the SOI silicon layer between the raised source/drain regions thereabove and below the level of the SiGe layer.

Abstract: Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater flexibility of channel depth control while avoiding floating body effects characteristic of SOI technology. The profile or cross-sectional shape of the discontinuous film may be controlled to an ogee or staircase shape to improve short channel effects and reduce source/drain and extension resistance without increase of capacitance. Materials for the discontinuous film may also be chosen to impose stress on the transistor channel from within the substrate or layer and provide increased levels of such stress to increase carrier mobility. Carrier mobility may be increased in combination with other meritorious effects.

Abstract: A first aspect of the present invention is a method of forming an isolation structure including: (a) providing a semiconductor substrate; (b) forming a buried N-doped region in the substrate; (c) forming a vertical trench in the substrate, the trench extending into the N-doped region; (d) removing the N-doped region to form a lateral trench communicating with and extending perpendicular to the vertical trench; and (e) at least partially filling the lateral trench and filling the vertical trench with one or more insulating materials.

Abstract: Described is a method for making thin channel silicon-on-insulator structures. The inventive method comprises forming a set of thin spacer abutting a gate region in a first device and a second device region; forming a raised source/drain region on either side of the gate region in the first device region and the second device region, implanting dopants of a first conductivity type into the raised source drain region in the first device region to form a first dopant impurity region, where the second device region is protected by a second device region block mask; implanting dopants of a second conductivity type into the raised source/drain region in the second device region to form a second dopant impurity region, where the first device region is protected by a first device region block mask; and activating the first dopant impurity region and the second dopant impurity region to provide a thin channel MOSFET.

Abstract: A first aspect of the present invention is a method of forming an isolation structure including: (a) providing a semiconductor substrate; (b) forming a buried N-doped region in the substrate; (c) forming a vertical trench in the substrate, the trench extending into the N-doped region; (d) removing the N-doped region to form a lateral trench communicating with and extending perpendicular to the vertical trench; and (e) at least partially filling the lateral trench and filling the vertical trench with one or more insulating materials.

Abstract: A method and device providing a strained Si film with reduced defects is provided, where the strained Si film forms a fin vertically oriented on a surface of a non-conductive substrate. The strained Si film or fin may form a semiconductor channel having relatively small dimensions while also having few defects. The strained Si fin is formed by growing Si on the side of a relaxed SiGe block. A dielectric gate, such as, for example, an oxide, a high “k” material, or a combination of the two, may be formed on a surface of the strained Si film. Additionally, without substantially affecting the stress in the strained Si film, the relaxed SiGe block may be removed to allow a second gate oxide to be formed on the surface previously occupied by the relaxed SiGe block.

Abstract: Described is a method for making thin channel silicon-on-insulator structures. The inventive method comprises forming a set of thin spacer abutting a gate region in a first device and a second device region; forming a raised source/drain region on either side of the gate region in the first device region and the second device region, implanting dopants of a first conductivity type into the raised source drain region in the first device region to form a first dopant impurity region, where the second device region is protected by a second device region block mask; implanting dopants of a second conductivity type into the raised source/drain region in the second device region to form a second dopant impurity region, where the first device region is protected by a first device region block mask; and activating the first dopant impurity region and the second dopant impurity region to provide a thin channel MOSFET.

Abstract: Disclosed is an optical waveguide having an optical confinement layer.

Abstract: A field effect device is disclosed which has a body formed of a crystalline semiconductor material and has at least one vertically oriented section and at least one horizontally oriented section. The device is produced in SOI technology by fabricating first a formation of the device in masking insulators, and then transferring this formation through several etching steps into the SOI layer. The segmented field effect device combines FinFET, or fully depleted silicon-on-insulator FETs, type devices with fully depleted planar devices. This combination allows device width control with FinFET type devices. The segmented field effect device gives high current drive for a given layout area. The segmented field effect devices allow for the fabrication of high performance processors.

Abstract: Context-based user feedback is gathered regarding searches performed on a search mechanism. The search mechanism is monitored for user behavior data regarding an interaction of a user with the search mechanism. The response data provided by the search mechanism is also monitored. Context data (describing the search) and user feedback data (the user's feedback on the search—either explicit or implicit) are determined. This can be used, for example, to evaluate a search mechanism or to check a relevance model.

Abstract: A field effect transistor (FET), integrated circuit (IC) chip including the FETs and a method of forming the FETS. Each FET includes a device gate along one side of a semiconductor (e.g., silicon) fin and a back bias gate along an opposite of the fin. Back bias gate dielectric differs from the device gate dielectric either in its material and/or thickness. Device thresholds can be adjusted by adjusting back bias gate voltage.

Abstract: A method for manufacturing a device including an n-type device and a p-type device. In an aspect of the invention, the method involves doping a portion of a semiconductor substrate and forming a gap in the semiconductor substrate by removing at least a portion of the doped portion of the semiconductor substrate. The method further involves growing a strain layer in at least a portion of the gap in the semiconductor substrate. For the n-type device, the strain layer is grown on at least a portion which is substantially directly under a channel of the n-type device. For the p-type device, the strain layer is grown on at least a portion which is substantially directly under a source region or drain region of the p-type device and not substantially under a channel of the p-type device.

Abstract: An RSD FET device with a recessed channel is formed with a raised silicon S/D and a gate electrode structure on an SOI structure by the steps as follows. Form a SiGe layer over the silicon layer and a RSD layer over the SiGe. Etch through the RSD layer and the SiGe to form a gate electrode space reaching down the silicon layer. Form a pair of RSD regions separated by the gate electrode space. Line the walls of the gate electrode space with an internal etch stop layer and an inner sidewall spacers. Form a gate electrode inside the inner sidewall spacers on the silicon layer. Form external sidewall spacers adjacent to the gate electrode between the RSD regions next to the inner sidewall spacers, and dope the RSD regions, whereby a recessed channel is formed in the SOI silicon layer between the raised source/drain regions above the SiGe layer.

Abstract: A SRAM cell fabricated in SSOI (selective silicon on insulator) comprises cross coupled PFET pull-up devices P1, P2 and NFET pull-down devices N1, N2, with the P1, P2 devices being connected to the power supply and the N1, N2 devices being connected to the ground. A first passgate NL is coupled between a first bitline and the junction of the devices P1 and N1, with its gate coupled to a wordline, and a second passgate NR is coupled between a second bitline and the junction of devices P2 and N2, with its gate coupled to the wordline. Each of the pull-up devices P1, P2, the pull-down devices N1, N2, and the first and second passgates NL, NR are fabricated with selective SOI, with buried oxide being selectively provided under the drains of the pull-up devices P1 and P2, the drains of the pull-down devices N1 and N2, and the sources and drains of the passgate devices NL and NR.

Abstract: The invention relates generally to lithographic patterning of very small features. In particular, the invention relates generally to patterning of semiconductor circuit features smaller than lithographically defined using either conventional optical lithography or next generation lithography techniques. The invention relates more particularly, but not by way of limitation, to lateral trimming of photoresist images.

Abstract: A method of fabricating an electronic chip on a wafer in which a first mask at a predetermined lower resolution is developed on the wafer and then etched under a first set of conditions for a predetermined period to achieve a mask that is below the resolution limit of current lithography. The etched mask is then used as a hard mask for etching material on a lower layer.

Abstract: Described is a method for making thin channel silicon-on-insulator structures. The inventive method comprises forming a set of thin spacer abutting a gate region in a first device and a second device region; forming a raised source/drain region on either side of the gate region in the first device region and the second device region, implanting dopants of a first conductivity type into the raised source drain region in the first device region to form a first dopant impurity region, where the second device region is protected by a second device region block mask; implanting dopants of a second conductivity type into the raised source/drain region in the second device region to form a second dopant impurity region, where the first device region is protected by a first device region block mask; and activating the first dopant impurity region and the second dopant impurity region to provide a thin channel MOSFET.

Abstract: An alignment system includes a first module having a plurality of emitters and a first receiver configuration located on the face of the first module. A second module has a second plurality of emitters and a second receiver configuration located on the face of the second module. First and second trigger signal generators fire the first and second plurality of the emitters. The generated signals are sensed by at least some of the receivers. A converter arrangement obtain and convert the received signals into digital data representative of the readings received by selected receivers. A processing system computes at least one of an absolute six degree offset or a relative six degree offset between the faces. The offset information is then used to achieve a desired alignment between the face of the first module and the face of the second module.

Abstract: A first aspect of the present invention is a method of forming an isolation structure including: (a) providing a semiconductor substrate; (b) forming a buried N-doped region in the substrate; (c) forming a vertical trench in the substrate, the trench extending into the N-doped region; (d) removing the N-doped region to form a lateral trench communicating with and extending perpendicular to the vertical trench; and (e) at least partially filling the lateral trench and filling the vertical trench with one or more insulating materials.