Patents by Inventor Ying Zhang

Ying Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080315459
    Abstract: An article is provided that includes a mold comprising a pattern, a metal-containing layer in contact with the pattern, and a release agent that includes a functionalized perfluoropolyether bonded to the metal-containing layer. Also provided is a method of replication that includes the mold.
    Type: Application
    Filed: June 21, 2007
    Publication date: December 25, 2008
    Inventors: Jun-Ying Zhang, Mark J. Pellerite, Suresh Iyer, Thomas P. Klun
  • Publication number: 20080310212
    Abstract: An SRAM having asymmetrical FET pass gates and a method of fabricating an SRAM having asymmetrical FET pass gates. The pass gates are asymmetrical with respect to current conduction from the drain to the source of the pass gate being different from current conduction from the source to the drain of the pass gate.
    Type: Application
    Filed: June 15, 2007
    Publication date: December 18, 2008
    Inventors: Brian Joseph Greene, Chun-Yung Sung, Clement Wann, Robert Chi-Foon Wong, Ying Zhang
  • Publication number: 20080303069
    Abstract: A two-step nitrogen plasma method is used for stripping a photoresist layer from over a substrate. A first step within the two-step nitrogen plasma method uses a nitrogen plasma with ion activation to form from the photoresist layer over the substrate a treated photoresist layer over the substrate. A second step within the two-step nitrogen plasma method uses a second nitrogen plasma without ion activation to remove the treated photoresist layer from over the substrate. The method is particularly useful for stripping a patterned photoresist layer that is used for forming a gate electrode from a gate electrode material layer.
    Type: Application
    Filed: June 11, 2007
    Publication date: December 11, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nicholas C.M. Fuller, Solomon Assefa, Ying Zhang
  • Publication number: 20080305437
    Abstract: A method for forming a patterned structure within a microelectronic structure uses a non-directly imageable organic material layer located over a substrate and a directly imageable inorganic material layer located upon the non-directly imageable organic material layer. The directly imageable inorganic material layer is directly imaged to form a patterned inorganic material layer. The patterned inorganic material layer is used as a first etch mask within a first etch method that etches the non-directly imageable organic material layer to form a patterned organic material layer. At least the patterned organic material layer is used as a second etch mask within a second etch method that etches the substrate to form a patterned structure within the substrate.
    Type: Application
    Filed: June 11, 2007
    Publication date: December 11, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nicholas C.M. Fuller, Michael A. Guillorn, Francois Pagette, Balasubramanian Pranatharthiharan, Ying Zhang
  • Publication number: 20080291024
    Abstract: One embodiment of the present invention provides a system that locates a set of target transmitting mechanism using a mobile sensing infrastructure. During operation, the system determines a reference frame of a sensing mechanism by detecting signals from at least two transmitting mechanisms. The system further determines locations of the target transmitting mechanism relative to the reference frame using the sensing mechanism. In addition, the system produces a result to indicate the locations of the target transmitting mechanisms.
    Type: Application
    Filed: May 25, 2007
    Publication date: November 27, 2008
    Inventors: Ying Zhang, James E. Reich
  • Publication number: 20080283824
    Abstract: A semiconductor device includes a semiconductor substrate having at least one gap, extending under a portion of the semiconductor substrate. A gate stack is on the semiconductor substrate. A strain layer is formed in at least a portion of the at least one gap. The strain layer is formed only under at least one of a source region and a drain region of the semiconductor device.
    Type: Application
    Filed: July 15, 2008
    Publication date: November 20, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION,
    Inventors: An L. STEEGEN, Haining S. Yang, Ying Zhang
  • Publication number: 20080286972
    Abstract: A chemical composition and method for providing uniform and consistent etching of gate stacks on a semiconductor wafer, whereby the composition includes an etchant and an added ballast gas added. The gate stacks are formed using this combined etchant and ballast gas composition. The ballast gas may either be similar to, or the equivalent of, a gaseous byproduct generated within the processing chamber. The ballast gas is added in either an overload amount, or in an amount sufficient to compensate for varying pattern factor changes across the water. This etchant and added ballast gas form a substantially homogeneous etchant across the entire wafer, thereby accommodating for or compensating for these pattern factor differences. When etching the wafer using this homogeneous etchant, a passivation layer is formed on exposed wafer surfaces. The passivation layer protects the lateral sidewalls of the gate stacks during etch to result in straighter gate stacks.
    Type: Application
    Filed: July 10, 2008
    Publication date: November 20, 2008
    Applicant: International Business Machines Corporation
    Inventors: Timothy J. Dalton, Wesley C. Natzle, Paul W. Pastel, Richard S. Wise, Hongwen Yan, Ying Zhang
  • Patent number: 7452761
    Abstract: Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater flexibility of channel depth control while avoiding floating body effects characteristic of SOI technology. The profile or cross-sectional shape of the discontinuous film may be controlled to an ogee or staircase shape to improve short channel effects and reduce source/drain and extension resistance without increase of capacitance. Materials for the discontinuous film may also be chosen to impose stress on the transistor channel from within the substrate or layer and provide increased levels of such stress to increase carrier mobility. Carrier mobility may be increased in combination with other meritorious effects.
    Type: Grant
    Filed: October 11, 2007
    Date of Patent: November 18, 2008
    Assignee: International Business Machines Corporation
    Inventors: Huilong Zhu, Philip J. Oldiges, Bruce B. Doris, Xinlin Wang, Oleg Gluschenkov, Huajie Chen, Ying Zhang
  • Publication number: 20080277726
    Abstract: FET device structures are disclosed with the PFET and NFET devices having high-k dielectric gate insulators and metal containing gates. The metal layers of the gates in both the NFET and PFET devices have been fabricated from a single common metal layer. As a consequence of using a single layer of metal for the gates of both type of devices, the terminal electrodes of NFETs and PFETs can be butted to each other in direct physical contact. The FET device structures further contain stressed device channels, and gates with effective workfunctions of n+ Si and p+ Si values.
    Type: Application
    Filed: May 8, 2007
    Publication date: November 13, 2008
    Inventors: Bruce B. Doris, Eduard Albert Cartier, Barry Paul Linder, Vijay Narayanan, Vamsi Paruchuri, Mark Todhunter Robson, Michelle L. Steen, Ying Zhang
  • Publication number: 20080280404
    Abstract: A method for forming a microelectronic structure uses a mask layer located over a target layer. The target layer may be etched while using the mask layer as an etch mask to form an end tapered target layer from the target layer. An additional target layer may be formed over the end tapered target layer and masked with an additional mask layer. The additional target layer may be etched to form a patterned additional target layer separated from the end tapered target layer and absent an additional target layer residue adjacent the end tapered target layer. The method is useful for fabricating CMOS structures including nFET and pFET gate electrodes comprising different NFET and pFET gate electrode materials.
    Type: Application
    Filed: May 10, 2007
    Publication date: November 13, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael Chudzik, Bruce B. Doris, William K. Henson, Hongwen Yan, Ying Zhang
  • Publication number: 20080254577
    Abstract: A field effect device is disclosed which has a body formed of a crystalline semiconductor material and has at least one vertically oriented section and at least one horizontally oriented section. The device is produced in SOI technology by fabricating first a formation of the device in masking insulators, and then transferring this formation through several etching steps into the SOI layer. The segmented field effect device combines FinFET, or fully depleted silicon-on-insulator FETs, type devices with fully depleted planar devices. This combination allows device width control with FinFET type devices. The segmented field effect device gives high current drive for a given layout area. The segmented field effect devices allow for the fabrication of high performance processors.
    Type: Application
    Filed: June 20, 2008
    Publication date: October 16, 2008
    Applicant: International Business Machines Corporation
    Inventors: Ying Zhang, Bruce B. Doris, Thomas Safron Kanarsky, Meikei Ieong, Jakub Tadeusz Kedzierski
  • Patent number: 7435652
    Abstract: Multiple integration schemes for manufacturing dual gate semiconductor structures are disclosed. By employing the novel integration schemes, polysilicon gate MOSFETs and high-k dielectric metal gate MOSFETs are formed on the same semiconductor substrate despite differences in the composition of the gate stack and resulting differences in the etch rates. A thin polysilicon layer is used for one type of gate electrodes and a silicon-containing layer are used for the other type of gate electrodes in these integration schemes to balance the different etch rates and to enable etching of the two different gate stacks.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: October 14, 2008
    Assignee: International Business Machines Corporation
    Inventors: Tze-chiang Chen, Bruce B. Doris, Rangarajan Jagannathan, Hongwen Yan, Qingyun Yang, Ying Zhang
  • Patent number: 7435671
    Abstract: A trilayer resist (TLR) patterning scheme is provided to enable gate conductors, particularly polySi gate conductors, with critical dimensions (CDs) of less than 40 nm and minimal LER and LWR. In accordance with the present invention, the inventive patterning scheme utilizes an organic/inorganic/organic multilayer stack instead of an organic layer used in the prior art. The top organic layer of the inventive TLR is a photoresist material such as a 193 nm photoresist that is located atop an antireflective coating (ARC), which is also comprised of an organic material. The middle inorganic layer of the TLR comprises any oxide layer such as, for example, a low temperature (less than or equal to 250° C.) chemical vapor deposited (CVD) oxide, an oxide derived from TEOS (tetraethylorthosilicate), silicon oxide, a silane oxide, or a Si-containing ARC material.
    Type: Grant
    Filed: August 18, 2006
    Date of Patent: October 14, 2008
    Assignee: International Business Machines Corporation
    Inventors: Nicholas C. Fuller, Timothy J. Dalton, Ying Zhang
  • Publication number: 20080242070
    Abstract: Multiple integration schemes for manufacturing dual gate semiconductor structures are disclosed. By employing the novel integration schemes, polysilicon gate MOSFETs and high-k dielectric metal gate MOSFETs are formed on the same semiconductor substrate despite differences in the composition of the gate stack and resulting differences in the etch rates. A thin polysilicon layer is used for one type of gate electrodes and a silicon-containing layer are used for the other type of gate electrodes in these integration schemes to balance the different etch rates and to enable etching of the two different gate stacks.
    Type: Application
    Filed: March 30, 2007
    Publication date: October 2, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Tze-chiang Chen, Bruce B. Doris, Rangarajan Jagannathan, Hongwen Yan, Qingyun Yang, Ying Zhang
  • Publication number: 20080242069
    Abstract: Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater flexibility of channel depth control while avoiding floating body effects characteristic of SOI technology. The profile or cross-sectional shape of the discontinuous film may be controlled to an ogee or staircase shape to improve short channel effects and reduce source/drain and extension resistance without increase of capacitance. Materials for the discontinuous film may also be chosen to impose stress on the transistor channel from within the substrate or layer and provide increased levels of such stress to increase carrier mobility. Carrier mobility may be increased in combination with other meritorious effects.
    Type: Application
    Filed: June 4, 2008
    Publication date: October 2, 2008
    Inventors: Huilong Zhu, Philip J. Oldiges, Bruce B. Doris, Xinlin Wang, Oleg Gluschenkov, Huajie Chen, Ying Zhang
  • Patent number: 7429752
    Abstract: A semiconductor device includes a semiconductor substrate having at least one gap, extending under a portion of the semiconductor substrate. A gate stack is on the semiconductor substrate. A strain layer is formed in at least a portion of the at least one gap. The strain layer is formed only under at least one of a source region and a drain region of the semiconductor device.
    Type: Grant
    Filed: September 22, 2006
    Date of Patent: September 30, 2008
    Assignee: International Business Machines Corporation
    Inventors: An L Steegen, Haining S. Yang, Ying Zhang
  • Publication number: 20080233242
    Abstract: The present invention discloses the composition of antioxidant of bamboo leaves (AOB) and its use. The purpose of present invention is to provide a new food additive which is natural, nutritional, and muti-functional, and which is of rich resources, safety, good effect, and low cost. AOB is yellow or brown powders or particles obtained from bamboo leaves, wherein the main antioxidative components include flavones, lactones, phenolic acids. AOB can either inhibit lipid autoxidation chain reaction, or chelate transitional metal ions, and can be used as primary and second antioxidant. AOB can eliminate nitrite and inhibit the synthesis of N-nitrosamine, and has anti-bacteria, bacteriostatic, deodorizing, aroma enhancing etc. functions. AOB can be commonly used in oil-containing food, meat product, fishery product, expanded food etc. food systems.
    Type: Application
    Filed: October 8, 2004
    Publication date: September 25, 2008
    Inventors: Ying Zhang, Xiaoqin Wu, Zhuoyu Yu, Dingding Luo, Boyi Lu, Yu Zhang
  • Publication number: 20080224238
    Abstract: An advanced method of patterning a gate stack including a high-k gate dielectric that is capped with a high-k gate dielectric capping layer such as, for example, a rare earth metal (or rare earth like)-containing layer is provided. In particular, the present invention provides a method in which a combination of wet and dry etching is used in patterning such gate stacks which substantially reduces the amount of remnant high-k gate dielectric capping material remaining on the surface of a semiconductor substrate to a value that is less than 1010 atoms/cm2, preferably less than about 109 atoms/cm2.
    Type: Application
    Filed: March 13, 2007
    Publication date: September 18, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Siva Kanakasabapathy, Ying Zhang, Edmund M. Sikorski, Hongwen Yan, Vijay Narayanan, Vamsi K. Paruchuri, Bruce B. Doris
  • Patent number: 7413941
    Abstract: A field effect device is disclosed which has a body formed of a crystalline semiconductor material and has at least one vertically oriented section and at least one horizontally oriented section. The device is produced in SOI technology by fabricating first a formation of the device in masking insulators, and then transferring this formation through several etching steps into the SOI layer. The segmented field effect device combines FinFET, or fully depleted silicon-on-insulator FETs, type devices with fully depleted planar devices. This combination allows device width control with FinFET type devices. The segmented field effect device gives high current drive for a given layout area. The segmented field effect devices allow for the fabrication of high performance processors.
    Type: Grant
    Filed: May 13, 2006
    Date of Patent: August 19, 2008
    Assignee: International Business Machines Corporation
    Inventors: Ying Zhang, Bruce B. Doris, Thomas Safron Kanarsky, Meikei Ieong, Jakub Tadeusz Kedzierski
  • Publication number: 20080194112
    Abstract: A method for improving across-wafer etch uniformity of semiconductor devices in an etching chamber, wherein the method includes: introducing a first flow of gas mixtures from a central gas distribution plate manifold; introducing a second flow of gas mixtures from an auxiliary gas feed; and controlling process parameters including one or more of: duration, power, pressure, and gas flow rates for the first and second flow of gas mixtures; wherein the central gas distribution plate manifold is positioned above the semiconductor wafer; wherein the auxiliary gas feed is positioned around the perimeter of the semiconductor wafer; and wherein the controlling of the process parameters of the central gas distribution plate manifold and the auxiliary gas feed is facilitated by independent controls.
    Type: Application
    Filed: February 9, 2007
    Publication date: August 14, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Qingyun Yang, Joyce C. Liu, Hongwen Yan, Ying Zhang