Abstract: A method of selectively and electrolessly depositing a metal onto a substrate having a metallic patterned-nanostructure surface is disclosed. The method includes providing a tool having a patterned-nanostructure surface, the patterned-nanostructure surface having surface regions having a nanostructured surface, replicating the tool patterned-nanostructure surface onto a substrate to form a substrate patterned-nanostructure surface, disposing a metal layer on the substrate patterned-nanostructure surface to form a metallic patterned-nanostructure surface region, forming a self-assembled monolayer on the metallic patterned-nanostructure surface region, exposing the self-assembled monolayer to an electroless plating solution comprising a deposit metal, and depositing electrolessly the deposit metal selectively on the surface regions having a metallic nanostructured surface. Articles formed from this method are also disclosed.

Abstract: A semiconductor device includes a semiconductor substrate having at least one gap, extending under a portion of the semiconductor substrate. A gate stack is on the semiconductor substrate. A strain layer is formed in at least a portion of the at least one gap. The strain layer is formed only under at least one of a source region and a drain region of the semiconductor device.

Abstract: A braided comb-shaped salt-resistant thickening agent for tertiary oil extraction from class I oil reservoir is disclosed. The agent is polymerized with monomer (A) and monomer (B), and monomer (A) is one or multiple water soluble non-saturated compound(s) with alkenyl chain, while monomer (B) is at least one compound with the following formula: Monomer (A) is preferably acrylamide, ethenyl pyrrolidone, 2-acrylamide-2 methylpropane sulfonic acid, and acrylic acid or the mixture of the above said compounds, and in the formula of monomer (B), A is COOH, OH, SO3H, R1 and R2 are H or C1-C12 alkyl, R3 and R4 represent C1-C12 alkyl, C1-C12 alkylaryl, C1-C12 alkyl ether or C1-C12 alkyl ester group. This thickening agent has fine water solubility and good property to thicken water medium. The polymer's molecules present a braided comb-shaped structure in water solution with fine salt-resistant performances.

Abstract: A method for manufacturing a device including an n-type device and a p-type device. In an aspect of the invention, the method involves doping a portion of a semiconductor substrate and forming a gap in the semiconductor substrate by removing at least a portion of the doped portion of the semiconductor substrate. The method further involves growing a strain layer in at least a portion of the gap in the semiconductor substrate. For the n-type device, the strain layer is grown on at least a portion which is substantially directly under a channel of the n-type device. For the p-type device, the strain layer is grown on at least a portion which is substantially directly under a source region or drain region of the p-type device and not substantially under a channel of the p-type device.

Abstract: A field effect device is disclosed which has a body formed of a crystalline semiconductor material and has at least one vertically oriented section and at least one horizontally oriented section. The device is produced in SOI technology by fabricating first a formation of the device in masking insulators, and then transferring this formation through several etching steps into the SOI layer. The segmented field effect device combines FinFET, or fully depleted silicon-on-insulator FETs, type devices with fully depleted planar devices. This combination allows device width control with FinFET type devices. The segmented field effect device gives high current drive for a given layout area. The segmented field effect devices allow for the fabrication of high performance processors.

Abstract: A method of forming a transistor comprises disposing a planar platform (or pedestal, or layer) of silicon atop a support structure of oxide which is atop a substrate; forming gate structures both atop and beneath the planar platform; and forming source and drain diffusions within the planar platform. The gate structures which are formed beneath the planar platform may smaller than the planar platform, and may be aligned with the gate structures which are formed atop the planar platform. A transistor formed by the method is also disclosed.

Abstract: A method for making dual pre-doped gate stacks used in semiconductor applications such as complementary metal oxide semiconductor (CMOS) devices and metal oxide semiconductor field effect transistors (MOSFETs) is provided. The method involves providing at least one pre-doped conductive layer, such as poly silicon (poly-Si), on a gate stack and etching by exposing the conductive layer to an etching composition comprising at least one carbon containing gas. The carbon containing gas can be selected from gases having the general formula CxHy, such as, for example, CH4, C2H2, C2H4, and C2H6. The carbon containing gas can further be selected from gases having the general formula CxHyA, wherein a can represent one or more additional substituents selected from O, N, P, S, F, Cl, Br, and I. The processes can result in dual pre-doped gate stacks having essentially vertical sidewalls and further having a width of at least about 3 nm, such as from about 5 nm to about 150 nm.

Abstract: A field effect transistor (FET), integrated circuit (IC) chip including the FETs and a method of forming the FETS. Each FET includes a device gate along one side of a semiconductor (e.g., silicon) fin and a back bias gate along an opposite of the fin. Back bias gate dielectric differs from the device gate dielectric either in its material and/or thickness. Device thresholds can be adjusted by adjusting back bias gate voltage.

Abstract: A chemical composition and method for providing uniform and consistent etching of gate stacks on a semiconductor wafer, whereby the composition includes an etchant and an added ballast gas added. The gate stacks are formed using this combined etchant and ballast gas composition. The ballast gas may either be similar to, or the equivalent of, a gaseous byproduct generated within the processing chamber. The ballast gas is added in either an overload amount, or in an amount sufficient to compensate for varying pattern factor changes across the water. This etchant and added ballast gas form a substantially homogeneous etchant across the entire wafer, thereby accommodating for or compensating for these pattern factor differences. When etching the wafer using this homogeneous etchant, a passivation layer is formed on exposed wafer surfaces. The passivation layer protects the lateral sidewalls of the gate stacks during etch to result in straighter gate stacks.

Abstract: A lateral trench in a semiconductor substrate is formed by the following steps. Form a lateral implant mask (LIM) over a top surface of the semiconductor substrate. Implant a heavy dopant concentration into the substrate through the LIM to form a lateral implant region (LIR) in the substrate. Strip the LIM exposing the top surface of the substrate. Form an epitaxial silicon layer over the top surface of the substrate burying the LIR. Form a trench mask over the epitaxial layer. Etch a trench reaching through the epitaxial layer and the LIR. Form oxidized trench sidewalls, an oxidized trench bottom and oxidized sidewalls of the LIR. Etch the oxidized sidewalls of the LIR until the LIR is exposed. Form laterally extending trenches by etching away the LIR.

Abstract: The present invention is directed to methods for improving the efficiency of processes for the recovery of natural gas liquids from a gas feed, e.g., raw natural gas or a refinery or petrochemical plant gas stream. These methods may be employed with most, if not all, conventional separation methods using distillation towers, e.g., a demethanizer and/or deethanizer column. The methods of the present invention involve installing an internal refrigeration system consisting of an open cycle refrigerant withdrawn from a distillation column and a closed cycle refrigerant derived from the open cycle refrigeration system. A separator is installed downstream of the recycle compressor discharge cooler in the open cycle refrigeration scheme. At least a portion of liquid withdrawn from this separator is used as a closed cycle refrigerant by indirect heat exchange with the inlet gas or other process streams. Thus a closed refrigeration cycle enhances the performance of the open refrigeration cycle.

Abstract: The invention relates to a composition containing total triterpenoid sapogenins extracted from bamboo, the preparation method and use thereof. These total triterpenoid sapogenins are extracted from many parts of bamboo such as bamboo shavings in Gramineae by CO2 Supercritical Fluid Extraction technique. In the extract, the content of total triterpenoid sapogenins is 10-90%, while the contents of friedelin and lupenone are 5-35% and 1-10%, respectively. The extract in the invention has good physiological and pharmacological activities such as anti-free radical, anti-oxidation, anti-tumor and anti-hypertension. It can be used in medicines or functional foods for the treatment or prevention of cardiovascular and cerebrovascular diseases and tumor. It is also useful in cosmetics field.

Abstract: A network routing method and system may include initializing the network by determining, for each node of the network, a number of hops to a root node and delaying forwarding to the root node, for each node, a packet received, wherein the delay in forwarding the packet received to the root node from a forwarding node depends upon the number of hops separating the root node from the forwarding node. A network routing method and system may include initializing the network by determining, for each node of the network, a number of hops to a root node, determining, for a forwarding node that receives a packet from a sending node, whether to forward the packet to a root node, determining a delay after which the packet is to be forwarded to the root node and determining a probability of forwarding the packet to the root node.

Abstract: A method is presented for patterning a MOSFET gate which includes the steps of: forming a layer of gate material over a gate dielectric, depositing an amorphous Si layer over the gate material, depositing a nitride cap-layer on top of the amorphous Si layer, patterning the nitride cap-layer and the amorphous Si layer which results in exposed sidewalls on the amorphous Si layer, growing oxide strips on the sidewalls, removing the patterned nitride cap-layer and the amorphous Si layer while leaving the oxide strips in place, and using the oxide strips as masks in the patterning of the gate material.

Abstract: A system analyzes data from a search engine. A User Search Bundler analyzes User Searches groups similar User Searches into User Search Bundles, and an Intent Processor produces Intents based on the User Search Bundles. A Factor Generator considers User Searches and related information to produce Factors, where each Factor is with regard to a particular Result from a set of Search Results. A Relevance Classifier receives the Factors and operates based thereon to produce a Judgment for each Result. A Metric Generator produces Metrics based on the Factors and the Judgments, and, a data synthesizer formats extracted data into databases.

Abstract: The present invention provides methods of preparing and identifying antibodies against a loop domain of a protein, such as an extracellular loop (ECL) domain of a transmembrane protein. Cyclic and end-to-end cyclized peptides corresponding to loop domains are employed in the present invention. Transmembrane proteins contemplated by the invention include the G-coupled protein receptor or a viral envelope protein.

Abstract: An optical equalizer circuit for a light source, the optical equalizer circuit comprising M optical couplers linked by differential delay lines, wherein coupling ratios for the respective M optical couplers of the equalizer circuit are calculated based on an input signal from the light source and a designed profile the optical input is to be equalized to.

Abstract: A multi-gate device has a high-k dielectric layer for a top channel of the gate and a protective layer for use in a finFET device. The high-k dielectric layer is placed on the top surface of the channel of the finFET and may reduce or eliminate silicon consumption in the channel. The use of the high-k dielectric layer on the top surface reduces hysteresis and mobility degradation associated with high-k dielectrics. The protection layer may protect the high-k dielectric layer during an etching process.

Abstract: A lateral trench in a semiconductor substrate is formed by the following steps. Form a lateral implant mask (LIM) over a top surface of the semiconductor substrate. Implant a heavy dopant concentration into the substrate through the LIM to form a lateral implant region (LIR) in the substrate. Strip the LIM exposing the top surface of the substrate. Form an epitaxial silicon layer over the top surface of the substrate burying the LIR. Form a trench mask over the epitaxial layer. Etch a trench reaching through the epitaxial layer and the LIR. Form oxidized trench sidewalls, an oxidized trench bottom and oxidized sidewalls of the LIR. Etch the oxidized sidewalls of the LIR until the LIR is exposed. Form laterally extending trenches by etching away the LIR.

Abstract: An optical waveguide assembly has integral alignment features. The waveguide assembly is formed by fabricating a waveguide on a substrate prior to forming the alignment features, removing a portion of the waveguide to reveal the substrate, and forming the alignment feature in the substrate.