Abstract: A method of forming a complementary metal oxide semiconductor (CMOS) device includes forming an oxide layer on sidewalls and a top surface of a patterned gate conductor, and on sidewalls of a gate insulating layer formed on a semiconductor substrate; forming a first carbon-based layer over the gate conductor, gate insulating layer, and substrate; etching the first carbon-based layer so as to create a first set of carbon spacers; forming a second carbon-based layer over the gate conductor, gate insulating layer, substrate, and first set of carbon spacers; etching the second carbon-based layer so as to create a second set of carbon spacers; forming silicide contacts on the gate conductor, and on source and drain regions formed in the substrate; removing the first and second sets of carbon spacers; and forming a stress-inducing nitride layer over the substrate, silicide contacts, gate conductor, and gate insulating layer.

Abstract: A CMOS structure and a method for fabricating the CMOS structure include a first transistor located within a first semiconductor substrate region having a first polarity. The first transistor includes a first gate electrode that includes a first metal containing material layer and a first silicon containing material layer located upon the first metal containing material layer. The CMOS structure also includes a second transistor located within a laterally separated second semiconductor substrate region having a second polarity that is different than the first polarity The second transistor includes a second gate electrode comprising a second metal containing material layer of a composition that is different than the first metal containing material layer, and a second silicon containing material layer located upon the second metal containing material layer. The first silicon containing material layer and the first semiconductor substrate region comprise different materials.

Abstract: A method is provided of making a gated semiconductor device. Such method can include patterning a single-crystal semiconductor region of a substrate to extend in a lateral direction parallel to a major surface of a substrate and to extend in a direction at least substantially vertical and at least substantially perpendicular to the major surface, the semiconductor region having a first side and a second side opposite, e.g., remote from the first side. A first gate may be formed overlying the first side, the first gate having a first gate length in the lateral direction. A second gate may be formed overlying the second side, the second gate having a second gate length in the lateral direction which is different from the first gate length. In one embodiment, the second gate length may be shorter than the first gate length. In one embodiment, the first gate may consist essentially of polycrystalline silicon germanium and the second gate may consist essentially of polysilicon.

Abstract: Network pages are identified based on whether the pages include image alternative text that indicates that the network pages contain links to pages that are translations of each other. A plurality of pages and a plurality of respective uniform resource locators are downloaded from a server associated with the domain name of the identified network pages. The uniform resource locators are used to identify a set of candidate parallel page pairs and a set of features are created for each candidate parallel page pair. The sets of features are used to identify parallel page pairs, wherein the pages in a parallel page pair are translations of each other.

Abstract: An optical microresonator device is described including an optical waveguide and an optical microresonator positioned so as to optically couple to the waveguide. The waveguide includes a core and a metal cladding layer on at least part of one boundary of the core.

Abstract: A field effect device is disclosed which has a body formed of a crystalline semiconductor material and has at least one vertically oriented section and at least one horizontally oriented section. The device is produced in SOI technology by fabricating first a formation of the device in masking insulators, and then transferring this formation through several etching steps into the SOI layer. The segmented field effect device combines FinFET, or fully depleted silicon-on-insulator FETs, type devices with fully depleted planar devices. This combination allows device width control with FinFET type devices. The segmented field effect device gives high current drive for a given layout area. The segmented field effect devices allow for the fabrication of high performance processors.

Abstract: A multi-gate device has a high-k dielectric layer for a top channel of the gate and a protective layer for use in a finFET device. The high-k dielectric layer is placed on the top surface of the channel of the finFET and may reduce or eliminate silicon consumption in the channel. The use of the high-k dielectric layer on the top surface reduces hysteresis and mobility degradation associated with high-k dielectrics. The protection layer may protect the high-k dielectric layer during an etching process.

Abstract: Disclosed are a flexible polymer, particles made from same, and a process for preparing the particles. This flexible polymer is obtained from copolymerizing monomer (A) and monomer (B), wherein monomer (A) is one or more water-insoluble unsaturated diene monomers; monomer (B) is at least one compound with the general formula of wherein R is C1-C12alkyl, C1-C12 alkyl aryl, C1-C12 alkyl ether or C1-C12alkyl ester. Monomer (A) is in an amount of 60-90% by weight of the total combined weight of monomer (A) and monomer (B). Monomer (B) is in an amount of 10-40% by weight of the total combined weight of monomer (A) and monomer (B). The flexible polymer particles show excellent flexibility, deformability, elasticity as well as stability. They can be used in oilfields in nearby wellbore profile control and in-depth profile control or as in-depth flooding fluid diverting agents.

Abstract: One embodiment of the present invention provides a system that performs a query-based convergecast scheduling in a convergecast network, which includes a base-station and a plurality of nodes. During operation, the system receives a convergecast tree for the convergecast network. Each node in the convergecast tree is associated with a hop-count to the base-station through a specific branch and each node can generate zero or more packets to transmit. Next, the system initializes a query from the base-station, wherein the query is successively propagated to the nodes through the branches. In response to the query, the system computes distributed-timing-information indicating a packet transmission schedule for the nodes. The system next aggregates the distributed-timing-information associated with the nodes toward the base-station through the branches. The system then forwards the aggregated distributed-timing-information to the plurality of nodes.

Abstract: Techniques are provided for efficient information dissemination and discovery in large scale networks such as ad-hoc networks, sensor networks, vehicle networks, virtual networks and the like. The spatial information for a plurality of network elements within a network is determined and an interesting node identified. A variable resolution communication structure of inter-connected nodes is determined based on spatial information for the interesting node and a map. The map may be based on an equation, a formula, coordinates or other methods of extensibly specifying spaces. Information about the interesting node is propagated via the inter-connected nodes of the variable resolution communication structure.

Abstract: Context-based user feedback is gathered regarding searches performed on a search mechanism. The search mechanism is monitored for user behavior data regarding an interaction of a user with the search mechanism. The response data provided by the search mechanism is also monitored. Context data (describing the search) and user feedback data (the user's feedback on the search—either explicit or implicit) are determined. This can be used, for example, to evaluate a search mechanism or to check a relevance model.

Abstract: Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater flexibility of channel depth control while avoiding floating body effects characteristic of SOI technology. The profile or cross-sectional shape of the discontinuous film may be controlled to an ogee or staircase shape to improve short channel effects and reduce source/drain and extension resistance without increase of capacitance. Materials for the discontinuous film may also be chosen to impose stress on the transistor channel from within the substrate or layer and provide increased levels of such stress to increase carrier mobility. Carrier mobility may be increased in combination with other meritorious effects.

Abstract: A gated semiconductor device is provided, in which the body has a first dimension extending in a lateral direction parallel to a major surface of a substrate, and second dimension extending in a direction at least substantially vertical and at least substantially perpendicular to the major surface, the body having a first side and a second side opposite the first side. The gated semiconductor device includes a first gate overlying the first side, and having a first gate length in the lateral direction. The gated semiconductor device further includes a second gate overlying the second side, the second gate having a second gate length in the lateral direction which is different from, and preferably shorter than the first gate length. In one embodiment, the first gate and the second gate being electrically isolated from each other. In another embodiment the first gate consists essentially of polycrystalline silicon germanium and the second gate consists essentially of polysilicon.

Abstract: A multi-gate device has a high-k dielectric layer for a top channel of the gate and a protective layer for use in a finFET device. The high-k dielectric layer is placed on the top surface of the channel of the finFET and may reduce or eliminate silicon consumption in the channel. The use of the high-k dielectric layer on the top surface reduces hysteresis and mobility degradation associated with high-k dielectrics. The protection layer may protect the high-k dielectric layer during an etching process.

Abstract: A method for making dual pre-doped gate stacks used in semiconductor applications such as complementary metal oxide semiconductor (CMOS) devices and metal oxide semiconductor field effect transistors (MOSFETs) is provided. The method involves providing at least one pre-doped conductive layer, such as poly silicon (poly-Si), on a gate stack and etching by exposing the conductive layer to an etching composition comprising at least one carbon containing gas. The carbon containing gas can be selected from gases having the general formula CxHy, such as, for example, CH4, C2H2, C2H4, and C2H6. The carbon containing gas can further be selected from gases having the general formula CxHyA, wherein A can represent one or more additional substituents selected from O, N, P, S, F, Cl, Br, and I. The processes can result in dual pre-doped gate stacks having essentially vertical sidewalls and further having a width of at least about 3 nm, such as from about 5 nm to about 150 nm.

Abstract: A sorbent media protective device includes an enclosure having a gas inlet, gas outlet and a thin-film multilayer indicator. The thin-film multilayer indicator is proximate sorbent media that can sorb a vapor of interest flowing from the gas inlet towards the gas outlet. The indicator includes a porous detection layer whose optical thickness changes in the presence of the vapor, located between a semireflective layer and a reflective layer permeable to the vapor. With equilibration at the applied vapor concentration between at least a portion of the media and the vapor, the vapor can pass through the reflective layer into the detection layer and change the detection layer optical thickness sufficiently to cause a visibly discernible change in the indicator appearance if viewed through the semireflective layer.

Abstract: An optical interleaver comprising a first optical 3×3 coupler for receiving a broadband optical signal at one input port thereof, a second 3×3 optical coupler, three differential delay lines connected in parallel port-to-port between output ports of the first optical 3×3 coupler and input ports of the second optical 3×3 coupler, an infinite impulse response (IIR) element disposed in each of two of the delay lines, and wherein optical signals travelling in the respective delay lines interfere at the second 3×3 coupler to produce three frequency shifted transmission channel output signals at respective output ports of the second 3×3 coupler.

Abstract: A trilayer resist (TLR) patterning scheme is provided to enable gate conductors, particularly polySi gate conductors, with critical dimensions (CDs) of less than 40 nm and minimal LER and LWR. In accordance with the present invention, the inventive patterning scheme utilizes an organic/inorganic/organic multilayer stack instead of an organic layer used in the prior art. The top organic layer of the inventive TLR is a photoresist material such as a 193 nm photoresist that is located atop an antireflective coating (ARC), which is also comprised of an organic material. The middle inorganic layer of the TLR comprises any oxide layer such as, for example, a low temperature (less than or equal to 250° C.) chemical vapor deposited (CVD) oxide, an oxide derived from TEOS (tetraethylorthosilicate), silicon oxide, a silane oxide, or a Si-containing ARC material.

Abstract: A first aspect of the present invention is a method of forming an isolation structure including: (a) providing a semiconductor substrate; (b) forming a buried N-doped region in the substrate; (c) forming a vertical trench in the substrate, the trench extending into the N-doped region; (d) removing the N-doped region to form a lateral trench communicating with and extending perpendicular to the vertical trench; and (e) at least partially filling the lateral trench and filling the vertical trench with one or more insulating materials.