Abstract: An interconnect structure for use in semiconductor devices and a method for fabricating the same is described. The method includes positioning a substrate in a vacuum processing chamber, wherein the substrate comprises a copper layer having an exposed surface and a low-k dielectric layer having an exposed surface, forming a metal layer over the exposed surface of the copper layer, wherein the exposed surface of the low-k dielectric layer is free from the metal layer, and forming a metal-based dielectric layer over the metal layer and over at least part of the exposed low-k dielectric surface, wherein the metal-based dielectric layer comprises an aluminum compound.

Abstract: Methods are disclosed for depositing a thin film of compound material on a substrate. In some embodiments, a method of depositing a layer of compound material on a substrate include: flowing a reactive gas into a plasma processing chamber having a substrate to be sputter deposited disposed therein in opposition to a sputter target comprising a metal; exciting the reactive gas into a reactive gas plasma to react with the sputter target and to form a first layer of compound material thereon; flowing an inert gas into the plasma processing chamber; and exciting the inert gas into a plasma to sputter a second layer of the compound material onto the substrate directly from the first layer of compound material. The cycles of target poisoning and sputtering may be repeated until a compound material layer of appropriate thickness has been formed on the substrate.

Abstract: Embodiments of apparatus for physical vapor deposition are provided. In some embodiments, a target assembly for use in a substrate processing system to process a substrate includes a plate having a first side and an opposing second side, wherein the second side comprises a target supporting surface extending from the second side in a direction normal to the second side, wherein the target supporting surface has a first diameter and is bounded by a first edge; and a target having a first side bonded to the target supporting surface, wherein a diameter of the target is greater than the first diameter of the target supporting surface.

Abstract: In some embodiments a method of processing a substrate disposed atop a substrate support in a physical vapor deposition process chamber includes: (a) depositing a dielectric layer to a first thickness atop a first surface of the substrate via a physical vapor deposition process; (b) providing a first plasma forming gas to a processing region of the physical vapor deposition process chamber, wherein the first plasma forming gas comprises hydrogen but not carbon; (c) providing a first amount of bias power to a substrate support to form a first plasma from the first plasma forming gas within the processing region of the physical vapor deposition process chamber; (d) exposing the dielectric layer to the first plasma; and (e) repeating (a)-(d) to deposit the dielectric film to a final thickness.

Abstract: In some embodiments, a method of forming an interconnect structure includes selectively depositing a barrier layer atop a substrate having one or more exposed metal surfaces and one or more exposed dielectric surfaces, wherein a thickness of the barrier layer atop the one or more exposed metal surfaces is greater than the thickness of the barrier layer atop the one or more exposed dielectric surfaces. In some embodiments, a method of forming an interconnect structure includes depositing an etch stop layer comprising aluminum atop a substrate via a physical vapor deposition process; and depositing a barrier layer atop the etch stop layer via a chemical vapor deposition process, wherein the substrate is transferred from a physical vapor deposition chamber after depositing the etch stop layer to a chemical vapor deposition chamber without exposing the substrate to atmosphere.

Abstract: An interconnect structure for use in semiconductor devices and a method for fabricating the same is described. The method includes positioning a substrate in a vacuum processing chamber. The substrate has an exposed copper surface and an exposed low-k dielectric surface. A metal layer is formed over the copper surface but not over the low-k dielectric surface. A metal-based dielectric layer is formed over the metal layer and the low-k dielectric layer.

Abstract: The present disclosure provides an interconnect formed on a substrate and methods for forming the interconnect on the substrate. In one embodiment, the method for forming an interconnect on a substrate includes depositing a barrier layer on the substrate, depositing a transition layer on the barrier layer, and depositing an etch-stop layer on the transition layer, wherein the transition layer shares a common element with the barrier layer, and wherein the transition layer shares a common element with the etch-stop layer.

Abstract: In some embodiments a method of processing a substrate disposed atop a substrate support in a physical vapor deposition process chamber includes: (a) depositing a dielectric layer to a first thickness atop a first surface of the substrate via a physical vapor deposition process; (b) providing a first plasma forming gas to a processing region of the physical vapor deposition process chamber, wherein the first plasma forming gas comprises hydrogen but not carbon; (c) providing a first amount of bias power to a substrate support to form a first plasma from the first plasma forming gas within the processing region of the physical vapor deposition process chamber; (d) exposing the dielectric layer to the first plasma; and (e) repeating (a)-(d) to deposit the dielectric film to a final thickness.

Abstract: Methods for depositing a layer on a substrate are provided herein. In some embodiments, a method of depositing a metal-containing layer on a substrate in a physical vapor deposition (PVD) chamber may include applying RF power at a VHF frequency to a target comprising a metal disposed in the PVD chamber above the substrate to form a plasma from a plasma-forming gas; optionally applying DC power to the target; sputtering metal atoms from the target using the plasma while maintaining a first pressure in the PVD chamber sufficient to ionize a predominant portion of the sputtered metal atoms; and controlling the potential on the substrate to be the same polarity as the ionized metal atoms to deposit a metal-containing layer on the substrate.

Abstract: A multifunctional all-terrain walking-type hydraulic excavator includes a multifunctional working apparatus (2), a cab (3), a slew assembly (4), a slewing bearing (6), and a walking-type chassis (5). By means of a hydraulic capstan (5.9) arranged at the forward end of the chassis (5), the excavator is able to perform self-rescue and towing assistance. The walking-type chassis (5) adapts to terrain through adjustments of the swing angles of the forward and rear legs (5.2, 5.4, 5.5, 5.6) and thus is able to walk and operate in difficult terrain.

Abstract: In some embodiments, a substrate carrier for holding a plurality of substrates comprises a disk formed of a continuous material to a nominal dimension which is approximately a multiple of a nominal dimension of a standard substrate size used in the manufacture of light emitting diode devices. In an embodiment, the disk is formed symmetrically about a central axis and defines a substantially planar upper surface. A first pair of pockets is defined in the upper surface of the disk, wherein the disk and each of the first pair of pockets are bisected by a first reference plane passing through the central axis. A second pair of pockets is defined in the upper surface of the disk, wherein the disk and each of the second pair of pockets are bisected by a second reference plane passing through the central axis.

Abstract: The embodiments herein provides methods for forming a PVD silicon oxide or silicon rich oxide, or PVD SiN or silicon rich SiN, or SiC or silicon rich SiC, or combination of the preceding including a variation which includes controlled doping of hydrogen into the compounds heretofore referred to as SiOxNyCz:Hw, where w, x, y, and z can vary in concentration from 0% to 100%, is produced as a hardmask with optical properties that are substantially matched to the photo-resists at the exposure wavelength. Thus making the hardmask optically planarized with respect to the photo-resist. This allows for multiple sequences of litho and etches in the hardmask while the photo-resist maintains essentially no optical topography or reflectivity variations.

Abstract: Interconnect structures and methods of formation of such interconnect structures are provided herein. In some embodiments, a method of forming an interconnect includes: depositing a silicon-aluminum oxynitride (SiAlON) layer atop a first layer of a substrate, wherein the first layer comprises a first feature filled with a first conductive material; depositing a dielectric layer over the silicon-aluminum oxynitride (SiAlON) layer; and forming a second feature in the dielectric layer and the silicon-aluminum oxynitride (SiAlON) layer to expose the first conductive material.

Abstract: A multifunctional continuous phase transition extraction apparatus comprises an extraction system, a desorption system and a solvent recovery system. The extraction system comprises a first heat exchanger and an extraction tank. The desorption system comprises a second heat exchanger, a first desorption tank, a second desorption tank, a first purification column and a second purification column. The solvent recovery system comprises a first condenser, a second condenser, a first solvent tank and a second solvent tank. Two extraction loops can be formed in the present invention. During the overall extraction process, the phase transition process of the extracting agent is real-time and continuous. The extracting agent goes through continuous phase-transitions and is cyclically re-used. The overall process is operated in an airtight and low-pressure condition, and is multifunctional, safe, reliable, and suitable for the extraction for most natural products.

Abstract: The present invention provides a data processing method, including: acquiring historical data, where the historical data belongs to a first level and a second level, and data corresponding to the first level comprises data corresponding to the second level; generating, from the historical data, a first-granularity data set according to a first granularity, and generating, from the historical data, a second-granularity data set according to a second granularity, where the first granularity and the second granularity respectively correspond to the first level and the second level; performing modeling for a second-granularity forecasting model according to the first-granularity data set and the second-granularity data set; and performing forecasting by using the second-granularity forecasting model to obtain second-granularity forecast data. The present invention enables obtained forecast data of different granularities to be consistent.

Abstract: In some embodiments, a substrate carrier for holding a plurality of substrates comprises a disk formed of a continuous material to a nominal dimension which is approximately a multiple of a nominal dimension of a standard substrate size used in the manufacture of light emitting diode devices. In an embodiment, the disk is formed symmetrically about a central axis and defines a substantially planar upper surface. A first pair of pockets is defined in the upper surface of the disk, wherein the disk and each of the first pair of pockets are bisected by a first reference plane passing through the central axis. A second pair of pockets is defined in the upper surface of the disk, wherein the disk and each of the second pair of pockets are bisected by a second reference plane passing through the central axis.

Abstract: Methods for forming a passivation protection structure on a metal line layer formed in an insulating material in an interconnection structure are provided. In one embodiment, a method for forming passivation protection on a metal line in an interconnection structure for semiconductor devices includes selectively forming a metal capping layer on a metal line bounded by a dielectric bulk insulating layer in an interconnection structure formed on a substrate in a processing chamber incorporated in a multi-chamber processing system, in-situ forming a barrier layer on the substrate in the processing chamber; wherein the barrier layer is a metal dielectric layer, and forming a dielectric capping layer on the barrier layer in the multi-chamber processing system.

Abstract: A liquid crystal lens includes a liquid crystal layer and at least two driving electrode plates. The liquid crystal layer is arranged between the driving electrode plates. Each of the driving electrode plates includes a transparent substrate, a circuit layer, an insulating layer, an electrode layer, at least a conducting pillar and an alignment layer. The transparent substrate has a surface, and the circuit layer is atop the surface. The conducting pillar is arranged in the insulating layer and connected to the electrode layer and the circuit layer. The alignment layer contacts the liquid layer. The electrode layer is interposed between the alignment layer and the insulating layer. The electrode layer in at least one of the driving electrode plates includes at least two ring-shaped electrodes.

Abstract: The embodiments herein provides methods for forming a PVD silicon oxide or silicon rich oxide, or PVD SiN or silicon rich SiN, or SiC or silicon rich SiC, or combination of the preceding including a variation which includes controlled doping of hydrogen into the compounds heretofore referred to as SiOxNyCz:Hw, where w, x, y, and z can vary in concentration from 0% to 100%, is produced as a hardmask with optical properties that are substantially matched to the photo-resists at the exposure wavelength. Thus making the hardmask optically planarized with respect to the photo-resist. This allows for multiple sequences of litho and etches in the hardmask while the photo-resist maintains essentially no optical topography or reflectivity variations.

Abstract: Firmware updates at an information handling system flash memory device, such as provisioning information stored on a USB device, are securely performed by using a buffer memory and a secured code. An application running on a CPU generates a firmware update and a security code, such as a ciphered hash code based on the firmware update, stores the firmware update and security code in a buffer, and informs a management processor of the update. The management processor analyzes the firmware update to authorize copying of the update from the buffer to the flash memory device. For instance, the management processor creates the security code from the firmware update and compares the created code with the security code stored in the buffer to validate the firmware update.