Abstract: A display device includes a display panel including a display area and non-display areas surrounding the display area; an encapsulation substrate disposed on the display panel and including melting patterns formed in regions overlapping the non-display areas; a sealing member disposed between the display panel and the encapsulation substrate to couple the display panel with the encapsulation substrate; and fusing patterns disposed across the sealing member and the encapsulation substrate. The display panel further includes a metal line layer disposed in at least a portion of the non-display areas, at least a portion of the sealing member is disposed on the metal line layer in the non-display areas, the melting patterns are disposed to overlap the metal line layer in a thickness direction, and the fusing patterns are disposed not to overlap the metal line layer in the thickness direction.

Abstract: Disclosed are semiconductor memory devices and methods of fabricating the same. The semiconductor memory devices may include a plurality of layers sequentially stacked on a substrate in a vertical direction, each of the plurality of layers including a bit line extending in a first direction and a semiconductor pattern extending from the bit line in a second direction traversing the first direction, a gate electrode extending through the plurality of layers and including a vertical portion extending through the semiconductor patterns and a first horizontal portion extending from the vertical portion and facing a first surface of one of the semiconductor patterns, and a data storing element electrically connected to the one of the semiconductor patterns. The data storing element includes a first electrode electrically connected to the one of the semiconductor patterns, a second electrode on the first electrode, and a dielectric layer between the first and second electrodes.

Abstract: An electronic component-embedded substrate includes a wiring structure including a plurality of insulating layers and a plurality of wiring layers and having a cavity penetrating through at least one of the plurality of insulating layers, a first electronic component disposed in the cavity, a dam structure disposed on the wiring structure and having a through-portion, a first insulating material disposed in at least a portion of each of the cavity and the through-portion, and covering at least a portion of each of the wiring structure and the first electronic component, and a first circuit layer disposed on the first insulating material.

Abstract: A semiconductor memory device including first-first conductive lines on a substrate; second-first conductive lines on the first-first conductive lines; first contacts connected to the first-first conductive lines; and second contacts connected to the second-first conductive lines, wherein the first-first conductive lines protrude in a first direction beyond the second-first conductive lines; the first-first conductive lines include first regions having a first thickness, second regions having a second thickness, the second thickness being greater than the first thickness, and third regions having a third thickness, the third thickness being smaller than the first thickness and smaller than the second thickness, and the second regions of the first-first conductive lines are between the first regions of the first-first conductive lines and the third regions of the first-first conductive lines.

Abstract: The inventive concept relates to an apparatus for treating a substrate. The apparatus includes a support unit that supports the substrate and a nozzle unit having a nozzle that dispenses a chemical onto the substrate, in which the nozzle is connected with a ground line, and a variable resistor is provided on the ground line.

Abstract: Disclosed are semiconductor memory devices and methods of fabricating the same. The semiconductor memory device comprises a first semiconductor pattern that is on a substrate and that includes a first end and a second end that face each other, a first conductive line that is adjacent to a lateral surface of the first semiconductor pattern between the first and second ends and that is perpendicular to a top surface of the substrate, a second conductive line that is in contact with the first end of the first semiconductor pattern, is spaced part from the first conductive line, and is parallel to the top surface of the substrate, and a data storage pattern in contact with the second end of the first semiconductor pattern. The first conductive line has a protrusion that protrudes adjacent to the lateral surface of the first semiconductor pattern.

Abstract: Disclosed are semiconductor memory devices and methods of fabricating the same. The method including forming a mold structure by alternately stacking a plurality of first insulating layers and a plurality of second insulating layers on a substrate, patterning the mold structure to form a first trench that exposes a first inner sidewall of the mold structure, growing a vertical semiconductor layer in the first trench such that a vertical semiconductor layer covers the first inner sidewall, using the substrate as a seed to, patterning the mold structure to form a second trench that exposes a second inner sidewall of the mold structure, forming a plurality of recesses by selectively removing the second insulating layers from the mold structure through the second trench, and horizontally growing a plurality of horizontal semiconductor layers in corresponding recesses, using the vertical semiconductor layer as a seed may be provided.

Abstract: A semiconductor memory device may include a bit line extending in a first direction, a first conductive pattern extending in a second direction intersecting the first direction, a semiconductor pattern connecting the bit line and the first conductive pattern, a second conductive pattern including an insertion portion in the first conductive pattern, and a dielectric layer between the first conductive pattern and the second conductive pattern. The insertion portion of the second conductive pattern may have a width which increases as a distance from the semiconductor pattern increases.

Abstract: A substrate structure and electronic device provide improved power integrity and simplified manufacturing. The substrate structure includes a first printed circuit board, having a first side and a second side opposing each other, and a plurality of passive components embedded in the first printed circuit board. The plurality of passive components includes a first group, including a plurality of first passive components disposed adjacent to each other, and a second group, including a plurality of second passive components disposed adjacent to each other. A smallest distance between the first and second groups is greater than at least one of a smallest distance between adjacent first passive components and a smallest distance between adjacent second passive components.

Abstract: A tiled display includes a plurality of display devices, where a display area and a non-display area surrounding the display area are defined in each of the plurality of display devices, and a pad area is defined in the non-display area. The plurality of display devices includes a first display device and a second display device disposed adjacent to the first display device in a first direction, and the pad area of the first display device overlaps the display area of the second display device in a thickness direction.

Abstract: Method for diagnosing a pneumatic control valve by using a positioner model includes: establishing relational expression for outputting valve stem displacement according to control pressure, the relational expression including parameters for the characteristics of a positioner, an actuator, and a valve, determining initial parameter value by adjusting the values of the parameters until the difference between a measured value for a normal operation of the pneumatic control valve and output value obtained by the relational expression is smaller than predetermined error limit, determining diagnostic parameter value by adjusting the values of the parameters until the difference between a measured value for a diagnostic operation of the pneumatic control valve and an output value obtained by the relational expression is smaller than a predetermined error limit, and comparing the initial parameter value and the diagnostic parameter value so as to determine whether the pneumatic control valve has abnormality.

Abstract: A printed circuit board includes: an insulating layer; a first circuit pattern embedded in one surface of the insulating layer; and a second circuit pattern disposed on the one surface of the insulating layer and including a first metal layer and a second metal layer disposed on the first metal layer. An average width of the first metal layer is wider than an average width of the second metal layer.

Abstract: A manufacturing method of a window includes providing a window including a first non-folding portion, a second non-folding portion, and a folding portion disposed between the first and second non-folding portions and irradiating a laser beam to a front surface of the folding portion of the window to form a first groove in the front surface of the folding portion. The first and second non-folding portions and the folding portion are arranged in the window in a first direction, first processing areas extending in a second direction intersecting the first direction and arranged in the first direction are defined in the front surface of the folding portion, and the laser beam is irradiated at least once to each of the first processing areas in the second direction.

Abstract: A semiconductor device includes a bit line extending in a first direction, a gate electrode extending in a second direction, and a semiconductor pattern extending in a third direction and connected to the bit line, and a capacitor. The capacitor includes a first electrode connected to the semiconductor pattern and a dielectric film between the first and second electrodes. The first or the second direction is perpendicular to an upper surface of the substrate. The first electrode includes an upper and a lower plate region parallel to the upper surface of the substrate, and a connecting region which connects the upper and the lower plate regions. The upper and the lower plate regions of the first electrode include an upper and a lower surface facing each other. The dielectric film extends along the upper and the lower surfaces of the upper and lower plate regions of the first electrode.

Abstract: Disclosed are semiconductor memory devices and methods of fabricating the same. The semiconductor memory devices may include a plurality of layers sequentially stacked on a substrate in a vertical direction, each of the plurality of layers including a bit line extending in a first direction and a semiconductor pattern extending from the bit line in a second direction traversing the first direction, a gate electrode extending through the plurality of layers and including a vertical portion extending through the semiconductor patterns and a first horizontal portion extending from the vertical portion and facing a first surface of one of the semiconductor patterns, and a data storing element electrically connected to the one of the semiconductor patterns. The data storing element includes a first electrode electrically connected to the one of the semiconductor patterns, a second electrode on the first electrode, and a dielectric layer between the first and second electrodes.

Abstract: The present invention relates to a composition containing as an active ingredient at least one selected from the group consisting of Akkermansia muciniphila cells, a culture thereof, a lysate thereof, and an extract of the lysate or culture, and to an anti-aging method including administering the composition.

Abstract: Provided are a display device and a method of manufacturing a display device. The display device includes a first substrate in which a display area and a non-display area disposed outside the display area are defined; a second substrate which faces the first substrate and comprises an area recessed in a thickness direction and a contact area disposed outside the recessed area; and a cell seal which bonds the first substrate and the second substrate together, wherein the cell seal comprises a bonding filament which is disposed between the contact area and the non-display area to connect the contact area and the first substrate and a frit seal which is disposed between the recessed area and the non-display area.

Abstract: An apparatus for estimating contact distribution to quickly estimate contact spot distribution from a contact surface image using a deep learning model based on a convolution neural network (CNN) and a method thereof are disclosed. A method for estimating contact distribution to estimate contact spot distribution between a first contact spot and a second contact spot includes inputting a contact surface image of at least one of the first contact surface and the second contact surface to a deep learning model based on a CNN and estimating contact spot distribution between the first contact surface and the second contact surface from an output of the deep learning model.

Abstract: A connection structure embedded substrate includes a printed circuit board including a first insulating body and a plurality of first wiring layers disposed on at least one of an external region or an internal region of the first insulating body; and a connection structure embedded in the first insulating body and including first and second substrates. The first and second substrates are disposed adjacent to each other.

Abstract: A method of inhibiting degradation of an extractant by utilizing several auxiliary means in the DSX process: includes (a) preparing adjustment of the concentration of an extractant of a DSX solvent to a certain range; (b) extracting a metal contained in a pregnant leached solution by adjusting the ratio of the extractant and the diluent in the DSX solvent to a certain range; (c) measuring the pH of the aqueous phase solution by separating mixture into the aqueous phase solution and the organic phase solvent using a settler after step of extracting; (d) controlling the pH by adding soda ash (Na2CO3) so as to maintain the pH of the aqueous phase solution to be 3 to 7; and (e) scrubbing with scrubbing solution having a zinc concentration of 2 to 20 g/L by zinc sulfate (ZnSO4) to remove the manganese from the organic phase solvent containing the extracted metal.