Abstract: A housing assembly includes: a support including a peripheral side wall and a lug, the peripheral side wall defining a first accommodating space configured to accommodate a dual-camera assembly, and the lug being connected to an outer peripheral side of the peripheral side wall away from the first accommodating space; and a middle frame having a second accommodating space and a groove in communication with the second accommodating space, the support being accommodated in the second accommodating space, and the lug being fitted with the groove. The present disclosure further provides a dual-camera module and a mobile terminal.

Abstract: A bracket assembly for use in a mobile terminal includes a metal support and a multi-contact spring. The metal support is configured to support an electronic component of the mobile terminal. The multi-contact spring includes a first pressure contact part, a second pressure contact part, a first elastic part, a second elastic part, and a fixing part. The multi-contact spring is fixed to a frame of the mobile terminal by a fastener extending through the fixing part into the frame. The first elastic part is connected to the first pressure contact part and the fixing part and is configured to provide a first restoring force to the first pressure contact part such that the first pressure contact part abuts against a metal cover of the mobile terminal and is grounded.

Abstract: A switching power converter is provided that cycles a power switch during a group pulse mode of operation to produce a train of pulses within a group period responsive to a control voltage being within a group mode control voltage range. Depending upon the control voltage, the number of pulses in each train of pulses is varied to provide a linear power delivery to the load.

Abstract: A method for fabricating a Fin-FET device includes forming a plurality of discrete fin structures on a substrate with a bottom portion of the sidewall surfaces covered in an isolation layer, and forming a dielectric layer on the isolation layer and the fin structures with an opening formed across the fin structures and exposing a portion of the isolation layer and the fin structures. The method further includes forming a first oxidation layer on the exposed surfaces of the fin structures, and then forming a second oxidation layer between the first oxidation layer and the surfaces of the fin structures through a first annealing process. The method then includes forming a gate dielectric layer on the first oxidation layer, forming a sacrificial adsorption layer on the gate dielectric layer, performing a second annealing process, and then forming a gate electrode layer to fill the opening formed in the dielectric layer.

Abstract: The present disclosure provides N-type fin field-effect transistors. An N-type fin field-effect transistor includes a semiconductor substrate; at least one fin having a first side surface and a second side surface formed over the semiconductor substrate; a gate structure crossing over the fin and formed over the semiconductor substrate; and a source region and a drain region respectively formed on top of the fin at two sides of the gate structure by an ion implantation process on one of the first side surface and the second side surface of the fin at two sides of the gate structure and a thermal annealing process to diffuse doping ions into the other of the first side surface and the second side surface of the fin.

Abstract: Embodiments presented herein provide techniques for optimizing parallel data flows of a batch processing job using a profile of the processing job. An application retrieves a job profile for a processing job. The processing job has a plurality of processing stages specified in an execution profile. The job profile includes statistical data for at least one of the processing stages obtained during prior executions of the job. The application modifies properties of the execution profile based on the job profile to optimize the execution of the job. The application executes the processing job with the modified execution profile.

Abstract: Timing parameters that influence an install time interval for installing a product on computing machines in a test environment in accordance with an installation configuration option are identified. A test value of the timing parameter and a test value of the install time are determined for each of the computing machines. The test values of the timing parameter and the install time determined for the sample computing machines are analyzed to determine an install time calculation expression for the installation configuration option. For installation in accordance with the installation configuration option in a normal operating environment, a current value of each of the timing parameters of the predetermined install time calculation expression for the installation configuration option. The install time interval in the normal operating environment is estimated based on the current value of the timing parameters and the install time calculation expression.

Abstract: A method for controlling the rotational speed of a fan of an LED lamp, comprising: presetting a corresponding relationship between a voltage, a current and a temperature for an LED chip in the LED lamp in the controller, as well as presetting a corresponding relationship between the temperature of LED chip and the speed of the fan in the controller, measuring the voltage and current of the LED chip, obtaining the current calculated temperature of the LED chip through the measured voltage and current, and further determining the current desired fan speed through the obtained current calculated temperature, using the controller to control the fan to rotate at the current desired speed, thereby cooling the LED chip. Additionally a corresponding system for controlling the rotational speed of the fan of an LED lamp and an LED lamp including the system.

Abstract: A method for fabricating a semiconductor device includes forming a gate dielectric layer on a base substrate including an N-type logic region, a P-type logic region, a first pull down transistor (PDT) region, a second PDT region, and a pass gate transistor (PGT) region, forming a first work function layer (WFL) in the first N-type threshold-voltage (TV) region, the P-type logic region, the second PDT region, and the PGT region, forming a second WFL on the first WFL in the first P-type TV region, and forming a third WFL on the second WFL in the first P-type TV region, the first WFL in the second P-type TV region, and the gate dielectric layer in the second N-type TV region and the first PDT region. The thickness of the third WFL is smaller than the thickness of the first WFL. The method further includes forming a fourth WFL on the substrate.

Abstract: A method for fabricating an SRAM device includes providing a base substrate including a pull up transistor (PUT) region and a pull down transistor (PDT) region, forming a gate dielectric layer, forming a first work function (WF) layer using a P-type WF material, removing the first WF layer formed in the PDT region, forming a second WF layer using a P-type WF material on the first WF layer in the PUT region and on the gate dielectric layer in the PDT region, removing the second WF layer formed in the PDT region, forming a third WF layer using an N-type WF material on the top and the sidewall surfaces of the second WF layer in the PUT region, the sidewall surface of the first WF layer in the PUT region, and the gate dielectric layer in the PDT region, and forming a gate electrode layer on the third WF layer.

Abstract: A semiconductor structure, a method for fabricating the semiconductor structure and a static random access memory are provided. The method includes providing a base substrate including a substrate and a plurality of discrete fins on the substrate. The substrate includes a pull-up transistor region and a pull-down transistor region. The method also includes forming a gate structure on each fin; and forming pull-up doped epitaxial layers, in the fin on both sides of the gate structure in the pull-up transistor region. In addition, the method includes forming a first pull-down doped region connected to an adjacent pull-up doped epitaxial layer in the fin on one side of the gate structure in the pull-down transistor region. Further, the method includes forming a second pull-down doped region by performing an ion-doped non-epitaxial layer process on the fin on another side of the gate structure in the pull-down transistor region.

Abstract: A two-level latch mechanism for an operation mechanism of a circuit breaker is provided. The operation mechanism includes: a tripping component, a left side plate, a right side plate, a latch, a half shaft, a lever, and a main shaft. The tripping component, the latch and the lever are mounted between the left side plate and the right side plate. The half shaft and the main shaft penetrate through the left side plate and the right side plate, and extend out of the left side plate and the right side plate. The tripping component, the latch, the half shaft, the lever, and the main shaft move in linkage. The tripping component includes a tripping buckle and a latch surface is disposed on a second end of the tripping buckle. The tripping component, the latch component and the half shaft component form a two-level latch.

Abstract: Semiconductor structures and fabrication methods thereof are provided. An exemplary fabrication method includes providing a base substrate having an N-type logic region including a first and a second N-type threshold voltage region, a P-type logic region including a first and a second P-type threshold voltage region, a pull-up transistor region and an adjacent pull-down transistor region; forming a gate dielectric layer; forming a first work function layer on the gate dielectric layer; removing portions of the first work function layer; forming a second work function layer on remaining first work function layer and exposed portions of the gate dielectric layer; removing a portion of the second work function layer; forming an N-type work function layer on remaining second work function layer and exposed portion of the gate dielectric layer in the second N-type threshold voltage region; and forming a gate electrode layer on the N-type work function layer.

Abstract: An ultrasonic blood flow imaging display method and an ultrasonic imaging system. The system comprises: a probe (1); a transmitting circuit (2), configured to excite the probe (1) to transmit an ultrasonic beam to a scanning target; a receiving circuit (4) and a beam forming module (5), configured to receive an echo of the ultrasonic beam to obtain an ultrasonic echo signal; a data processing module (9), configured to obtain, according to the ultrasonic echo signal, blood flow velocity vector information and Doppler blood flow velocity information about a target point in the scanning target and at least part of ultrasonic images of the scanning target, and superposing the ultrasonic images and the Doppler blood flow velocity information to form a Doppler color blood flow graph; and a display (8), configured to contrastively display the blood flow velocity vector information and the Doppler color blood flow graph.

Abstract: A semiconductor structure, a method for fabricating the semiconductor structure, and a static random access memory are provided. The method includes providing a base substrate including a substrate and a plurality of discrete fins on the substrate. The substrate includes a pass gate transistor region. The method also includes forming a gate structure across a length portion of each fin, covering top and sidewall surfaces of each fin, and on each fin. Further, the method includes forming pass gate doped regions in the fin on both sides of the gate structure in the pass gate transistor region. At least one of the pass gate doped regions is formed by performing an ion-doped non-epitaxial layer process on the fin.

Abstract: Embodiments presented herein provide techniques for optimizing parallel data flows of a batch processing job using a profile of the processing job. An application retrieves a job profile for a processing job. The processing job has a plurality of processing stages specified in an execution profile. The job profile includes statistical data for at least one of the processing stages obtained during prior executions of the job. The application modifies properties of the execution profile based on the job profile to optimize the execution of the job. The application executes the processing job with the modified execution profile.

Abstract: A method for fabricating a semiconductor structure includes providing a substrate, forming an interface layer on the substrate, and then performing a first annealing process on the interface layer under a nitrogen-containing environment to form a nitrogen-containing layer from a top portion of the interface layer. The first annealing process also deactivates non-bonded silicon ions and oxygen ions in the interface layer. The method further includes forming a high-k dielectric layer on the nitrogen-containing layer, and performing a second annealing process on the high-k dielectric layer to allow nitrogen ions in the nitrogen-containing layer to diffuse into the high-k dielectric layer to reduce a density of active oxygen vacancies in the high-k dielectric layer. Finally, the method includes forming a gate electrode layer on the high-k dielectric layer.

Abstract: The present disclosure relates to a technical field of semiconductors and discloses a semiconductor resistor and a manufacturing method therefor.

Abstract: A semiconductor device includes a substrate structure comprising a substrate and a plurality of fins on the substrate. Each of the fins includes a fluorine-doped top portion.

Abstract: A method includes detecting, using a WiFi access point, channel use data indicating traffic on a plurality of channels of an unlicensed LTE band in a wireless network. The method further includes providing the channel use data to a Long Term Evolution (LTE) access point. The method further includes selecting, using the LTE access point, a channel for use in transmitting data by the LTE access point from among the plurality of channels based on the channel use data from the WiFi access point. The method further includes providing, from the LTE access point, an indication of an upcoming transmission configured to transmit data on the channel to the WiFi access point. The method further includes broadcasting one or more messages from the WiFi access point to one or more WiFi nodes, the one or more messages configured to prevent the WiFi nodes from transmitting on the channel.