Abstract: An ESD protection device includes a semiconductor substrate, first and second fins, first and second doped regions adjacent to each other and having different conductivity types. The first doped region includes a first portion of the substrate and a first region of the first fin. The second doped region includes a second portion of the substrate and a second region of the first fin. The device also includes a first gate structure on a portion of first and second regions of the first fin, a first highly doped region in the first region of the first fin and having a same conductivity type as the first doped region, and a dopant concentration higher than the first doped region, and a second highly doped region in the second fin and having a same conductivity type as the second doped region, and a dopant concentration higher than the second doped region.

Abstract: A method includes providing a semiconductor structure comprising multiple fins and a gate structure on the fins. The method also includes removing a portion of the fins not covered by the gate structure to form a remaining portion of the fins, performing a first epitaxially growth process to form first epitaxially grown regions on the remaining portion of the fins, performing a first annealing process so that an upper portion of the first epitaxially grown regions is greater than a lower portion, performing a second epitaxially growth process on the annealed first epitaxially grown regions to form second epitaxially grown regions, and performing a second annealing process on the second epitaxially grown regions, so that an upper portion of the second epitaxially grown regions is greater than a lower portion. The second epitaxially grown regions are separated from each other before and after the second annealing process.

Abstract: An electronic device is provided. The electronic device includes: a first processing unit; a storage unit, configured to store at least one audio file; a first memory unit; and a modulator-demodulator (modem), configured to perform audio processing of the electronic device during a phone call, wherein when the electronic device is used to play the audio file, the first processing unit reads the audio file from the storage unit, retrieves header information of the audio file, and writes the audio file into the first memory unit, wherein the modem accesses the audio file stored in the first memory unit based on the header information, and performs audio decoding on the audio file.

Abstract: A method includes a workload management (WLM) server that receives a first CHECK WORKLOAD command for a workload in a queue of the WLM server. It may be determined whether the workload is ready to run on a WLM client. If the workload is not ready to run, a wait time for the workload with the WLM server is dynamically estimated. The wait time is sent to the WLM client. If the workload is ready to run, then a response is sent to the WLM client that workload is ready to run.

Abstract: Camera module with switchable light filters includes a lens, a body, a movable tray, a first filter, a second filter, a gear and a protective cover. The lens is disposed in the body. The body defines a first through hole corresponding to the lens and includes a first surface. The movable tray is positioned on the first surface and is used for receiving the first filter and the second filter. The gear is arranged on the first surface by a rotating shaft, the gear is configured to engage with the movable tray to switch the first filter and the second filter. The protective cover is disposed on the body and partially covers the gear.

Abstract: Examples of the present disclosure provide a channel access period allocation method. The method includes: receiving, by an access point (AP), first information sent by a first station (STA) for requesting a dynamic service period (DSP) from the AP; and sending, by the AP, second information to the first STA to instruct the first STA to send a data frame to the AP in a first DSP, where a start time of the first DSP falls within a first preset time period following an end time of an SP of the first STA, and the first DSP requested by the first STA is pre-allocated to a second STA having a priority that is lower than that of the first STA, where a time delay of the first STA for sending the data frame to the AP satisfies a time delay requirement of a quality of service QoS in the first preset time period.

Abstract: Semiconductor devices and fabrication methods thereof are provided. An exemplary fabrication method includes providing a base substrate; forming gate structures over the base substrate; forming doped source/drain regions in the base substrate at two sides of each of the gate structures; forming an oxide layer on each of the doped source/drain regions; forming a metal layer on the oxide layer; and performing a reactive thermal annealing process, such that the metal layer reacts with a material of the oxide layer and a material of the doped source/drain regions to form a metal contact layer on each of the doped source/drain regions. The metal contact layer includes a first metal contact layer on the doped source/drain region, an oxygen-containing metal contact layer on the first metal contact layer, and a second metal contact layer on the oxygen-containing metal contact layer.

Abstract: The invention encompasses a novel process for making piperidinone carboxamide indane and azainane derivatives, which are CGRP receptor antagonists useful for the treatment of migraine.

Abstract: A semiconductor structure and a fabrication method are provided. A fabrication method includes providing a substrate including an NMOS region and a PMOS region; forming a first high-K gate dielectric layer on the NMOS region of the substrate; forming an interfacial layer on the PMOS region of the substrate; forming a second high-K gate dielectric layer on the interfacial layer and the first high-K gate dielectric layer; forming a metal layer on the second high-K gate dielectric layer.

Abstract: An operation mechanism of a circuit breaker includes: a tripping component; a left side plate; a right side plate; a latch; a half shaft; a lever; and a main shaft. The tripping component, the latch, the half shaft and the lever are mounted between the left side plate and the right side plate. The half shaft and the main shaft penetrate through the left side plate and the right side plate, and extend out of the left side plate and the right side plate. The lever includes a sheet metal bending piece. The sheet metal bending piece is bent to form a top wall and two side walls. The tripping component, the latch, the half shaft, the lever and the main shaft move in linkage. The tripping and the latch form a two-level latch. The operation mechanism of the circuit breaker is manual operation.

Abstract: A method of manufacturing a semiconductor device includes providing a substrate structure including PMOS and NMOS regions having respective first and second trenches, a high-k dielectric layer in the first and second trenches, and a first P-type work function adjustment layer on the high-k dielectric layer, sequentially forming first and second protective layers and a mask layer on the substrate structure, removing a portion of the mask layer exposing a portion of the second protective layer on the NMOS region, removing the exposed portion of the second protective layer on the NMOS region exposing a portion of the first protective layer on the NMOS region, removing the mask layer exposing the second protective layer on the PMOS region, removing portions of the first protective layer and first P-type work function adjustment layer on the NMOS region and removing the second and first protective layers on the PMOS region.

Abstract: A method for manufacturing a semiconductor device includes providing a substrate structure having PMOS and NMOS regions. The PMOS region includes a first region, a first gate structure on the first region, and first source and drain regions on opposite sides of the first gate structure. The NMOS region includes a second region and a second gate structure on the second region. The method also includes introducing a p-type dopant into the first source and drain regions, performing a first annealing, forming second source and drain regions on opposite sides of the second gate structure, introducing an n-type dopant into the second source and drain regions, and performing a second annealing. The method satisfies thermal budget requirements of forming PMOS and NMOS devices, thereby enabling a better diffusion of the p-type dopant into the source and drain regions of the PMOS device without affecting the performance of the NMOS device.

Abstract: Compounds, compositions and methods are provided for treating the FXR-mediated disease or process in a mammal, comprising administering to the mammal a therapeutically effective amount of a compound claimed, wherein the FXR-mediated disease or condition linked to chronic liver diseases such as nonalcoholic fatty liver disease and nonalcoholic steatohepatitis; gastrointestinal diseases; cardiovascular diseases; metabolic diseases such as diabetes and obesity; inflammation, or cancer etc.

Abstract: Acoustic diodes, devices incorporating such diodes and methods of using such devices are disclosed. An acoustic diode may include a periodic acoustic grating and a uniform plate. The periodic acoustic grating may include a plurality of gratings. The uniform plate may foe separated from the periodic acoustic grating by a resonant cavity. The acoustic diode may be configured to have a first transmission efficiency for acoustic waves incident on the periodic acoustic grating that is greater than a second transmission efficiency for acoustic waves incident on the uniform plate. The acoustic waves may have a wavelength within a range of wavelengths. Devices incorporating the acoustic diode may include medical imaging devices, such as ultrasound devices, and noise reduction devices.

Abstract: A method for fabricating a Fin-FET device includes providing a base structure and a plurality of fin structures protruding from the base structure. Along a direction perpendicular to the surface of the base structure and from the bottom to the top of each fin structure, the width of the fin structure perpendicular to the length direction of the fin structure decreases. The method further includes forming a gate structure on the base structure across each fin structure and covering a portion of top and sidewall surfaces of the fin structure, and removing a portion of the fin structure on each side of the gate structure to form a trench in the fin structure. Along the length direction of the fin structure, the bottom width of the trench is smaller than the top width of the trench. The method also includes filling each trench with a doped source/drain epitaxial layer.

Abstract: A method for fabricating a semiconductor structure includes providing a base structure including an NMOS region, forming an interlayer dielectric layer on the base structure with a plurality of openings formed in the NMOS region through the interlayer dielectric layer, forming a high-k dielectric layer on a bottom and sidewall surfaces of each opening of the NMOS region, forming an N-type work function layer on the high-k dielectric layer in each opening of the NMOS region, forming a diffusion barrier layer on the N-type work function layer, performing a hydrogenation process on the diffusion barrier layer, and forming a metal gate electrode on the diffusion barrier layer to fill up each opening in the NMOS region. The disclosed method and semiconductor structure improve the ability of the barrier layer to protect the N-type work function layer, and thus improve the electrical performance of the semiconductor device.

Abstract: A method for fabricating a Fin-FET device includes forming fin structures on a substrate and an isolation structure to cover a portion of sidewall surfaces of the fin structures, forming gate structures to cover a portion of sidewall and top surfaces of the fin structures, forming doped source/drain regions in the fin structures, forming a metal layer on the doped source/drain regions and the gate structures, performing a reaction annealing process to convert the metal layer formed on the doped source/drain regions into a metal contact layer and then removing the unreacted metal layer, forming a dielectric layer on the metal contact layer and the gate structures with a top surface higher than the top surfaces of the gate structures, forming a plurality of vias through the dielectric layer above the metal contact layer, and forming a plurality of conductive plugs by filling the vias.

Abstract: A FinFET device and fabrication method thereof is provided. The fabrication method include: providing a semiconductor substrate with a fin protruding from the semiconductor substrate, and a gate structure across a length portion of the fin and covering a portion of the fin; etching a partial thickness of the fin on both sides of the gate structure to form grooves; forming a doped layer in a bottom and sidewalls of the grooves; annealing the doped layer to allow the doping ions to diffuse into the fin and to form a lightly doped source/drain region; removing the doped layer after the annealing; and forming epitaxial layers to fill up the grooves.

Abstract: A method for manufacturing a semiconductor device may include the following steps: preparing a semiconductor structure that comprises a substrate and a first fin member, wherein the first fin member is connected to the substrate and comprises a first semiconductor portion; providing a first-type dopant member that directly contacts the first semiconductor portion, comprises first-type dopants, and is at least one of liquid and amorphous; and performing heat treatment on at least one of the first-type dopant member and the first semiconductor portion to enable a first portion of the first-type dopants to diffuse through a first side of the first-type dopant member into the first semiconductor portion.

Abstract: A user-defined function (UDF) is received in a central Computer System, which causes registration of the UDF and distributes the UDF to a cluster of computer system nodes configured for performing, in volatile memory of the nodes, extract-transform-load processing of data cached in the volatile memory of the nodes. First and second job specifications that include the UDF are received by the central Computer System, and the central computer system distributes instructions for the job specifications to the nodes including at least one instruction that invokes the UDF for loading and executing the UDF in the volatile memory of at least one of the nodes during runtime of the jobs. The central Computer System does not cause registration of the UDF again after receiving the first job specification.