Abstract: A semiconductor device includes a substrate structure, multiple fins protruding from the substrate structure, each of the fins having a first portion, a second portion on opposite sides of the first portion, and a third portion at an outer side of the first portion and adjacent to the second portion, a gate structure on the upper surface of the first portion, sidewall spacers on opposite sides of the gate structure and covering the upper surface of the second portion, and source and drain regions outside of the sidewall spacers. The source and drain regions each have an upper surface higher than the second portion upper surface. The first portion protrudes from the second portion. The upper surface of the second portion is lower than the first portion upper surface. The upper surface of the third portion is lower than the second portion upper surface.

Abstract: Embodiments of the present invention relate to the field of communications technologies, and disclose a resource reservation method and system, and a convergence device. The method includes: receiving, by a convergence device, a first resource reservation request message based on a format of a first interface and that is from a policy server (PS); converting, by the convergence device, the first resource reservation request message into a second resource reservation request message based on a format of a second interface; and sending, by the convergence device, the second resource reservation request message based on the format of the second interface to a modulation and demodulation system, so that the modulation and demodulation system performs resource reservation according to the second resource reservation request message.

Abstract: The present invention includes compounds useful as intermediates in the preparation of macrolactams, methods for preparing the intermediates, and methods for preparing macrolactams. One use of the methods and intermediates described herein is in the production of macrolactam compounds able to inhibit HCV NS3 protease activity. HCV NS3 inhibitory compounds have therapeutic and research applications.

Abstract: A switching power converter is provided with an overvoltage protection circuit that monitors the differential data signal voltages in a data interface such as a USB data interface powering a load device to detect soft short conditions.

Abstract: Semiconductor devices and fabrication methods thereof are provided. An exemplary fabrication method includes forming an interlayer dielectric layer on a base substrate; forming a plurality of first openings and second openings in the interlayer dielectric layer, one first opening connecting to a second opening, the one first opening being between the second opening and the base substrate; forming a high-K gate dielectric layer on side and bottom surfaces of the first openings and on side surfaces of the second openings; forming a cap layer, containing oxygen ions, on the high-K gate dielectric layer; forming an amorphous silicon layer on the cap layer at least on the bottoms of the first openings; performing a thermal annealing process on the amorphous silicon layer, the cap layer and the high-K dielectric; removing the amorphous silicon layer; and forming a metal layer, in the first openings and the second openings.

Abstract: A front cover assembly includes a frame, a cover glass, and a waterproof glue. The frame has a receiving cavity. The cover glass is partially received in the frame. The cover glass has a light exiting face and a lateral face extending from the light exiting face. The cover glass has a step portion located at the lateral face and extending toward the frame. A gap is defined between the step portion of the cover glass and the frame. A waterproof glue fills the gap and directly contacts the step portion and the frame. This assembly can prevent water or dust from entering a terminal device.

Abstract: A power converter with a dynamic preload. The power converter includes a magnetic component coupled between an input and an output of the power converter. The output of the power converter has an output voltage for providing power to a load. A switch is adapted to control current through the magnetic component according to on and off times of the switch. A dynamic preload circuit is coupled to the output of the power converter. The dynamic preload has loading characteristics that are adjusted responsive to a signal indicative of an output voltage at the output of the power converter.

Abstract: A method of manufacturing a semiconductor device includes providing a substrate structure, the substrate structure having a semiconductor substrate including a first semiconductor fin, a first gate structure, and a first mask layer on a first semiconductor region. The method includes forming a second mask layer on the substrate structure, etching first mask layer and second mask layer to expose a portion of a first semiconductor fin not covered by the first gate structure, performing a first ion implantation on an exposed portion of the first semiconductor fin to introduce impurities into a portion of the first semiconductor fin located below the first gate structure, etching the first semiconductor fin to remove a portion of an exposed portion of the first semiconductor fin, and epitaxially growing a first semiconductor material on the remaining portions of the first semiconductor fin to form a first source region and a first drain region.

Abstract: Implementing hardware accelerators using programmable integrated circuits may include performing, using a processor, a design flow on a static circuit design. The static circuit design may specify a region reserved for a hardware accelerator and a static region comprising interface circuitry configured to couple the hardware accelerator with an external node. The design flow may generate an implemented static circuit design. Metadata describing the interface circuitry may be generated using a processor. A device support archive including the implemented static circuit design and the metadata may be written, using the processor, to a computer readable storage medium.

Abstract: A data deduplication method is executed by a controller for a solid state drive (SSD). The controller receives a signature for a block of data. The controller performs a comparison of the signature and information in a signature library and determines whether or not the signature matches the information. The controller sends a signal that indicates a result of the comparison. If the signature and the information match then the signal has a first value indicating that the block of data is already stored on the SSD; if the signature and the information do not match then the signal has a second value that is different than the first value.

Abstract: A gate stack structure for a MOS varactor includes a substrate including a channel region, a high-k dielectric layer on the channel region of the substrate, a P-type work function adjustment layer on the high-k dielectric layer, an N-type work function adjustment layer on the P-type work function adjustment layer, and a metal gate on the N-type work function adjustment layer. The P-type work function adjustment layer includes a first portion and a second portion laterally adjacent to each other, the first portion having a thickness greater than a thickness of the second portion. The gate stack structure in the MOS varactor can increase the tuning range of the MOS varactor.

Abstract: The invention encompasses a novel process for making piperidinone carboxamide indane and azainane derivatives, which are CGRP receptor antagonists useful for the treatment of migraine.

Abstract: A method for forming a transistor is provided. The method includes providing a semiconductor substrate, and forming a dielectric layer on the semiconductor substrate. The dielectric layer has a gate structure recess. The method also includes forming a work function layer on a bottom and sidewalls of the gate structure recess; performing an ion implantation on the work function layer; and forming a gate layer on the work function layer after the ion implantation.

Abstract: A device for providing downlink channel access for non-operator devices includes at least one processor circuit. The at least one processor circuit is configured to establish a local connection with an operator device that is serviced by a network operator. The at least one processor circuit is configured to provide, to the operator device over the local connection, a request to establish a connection to a network, the request comprising a destination address. The at least one processor circuit is configured to receive, from the operator device over the local connection, control information for reception of a downlink channel provisioned by the network operator for the operator device. The at least one processor circuit is configured to receive downlink data associated with the destination address on the downlink channel and provide, to the operator device, uplink data associated with the destination address for transmission to the network.

Abstract: A method for fabricating a Fin-FET includes forming a plurality of fin structures, an isolation layer, and an interlayer dielectric layer on an NMOS region of a substrate, forming a first opening in the interlayer dielectric layer to expose a portion of the fin structures. A region adjacent to a joint between a bottom surface and a sidewall surface of the first opening is a corner region. The method includes forming a high-k dielectric layer on the bottom and the sidewall surfaces of the first opening, a barrier layer on the high-k dielectric layer, and an N-type work function layer containing aluminum ions on the barrier layer. The method further includes performing a back-flow annealing process such that the portion of N-type work function layer at the corner region is thickened and contains diffused aluminum ions. Finally, the method includes forming a metal layer on the N-type work function layer.

Abstract: A wireless device includes a first modem circuit, a second modem circuit, and one or more processor circuits. The first modem circuit supports wireless local area network (WLAN) communications. The second modem circuit supports long term evolution (LTE) and licensed assisted access (LAA) communications. The processor circuits determine free time intervals during which the second modem circuit is not engaged with a medium. The wireless device provides measurement reports to a base station. The first modem circuit enables the wireless device to perform the WLAN communications using the free time intervals without signaling to the base station.

Abstract: A method for manufacturing a semiconductor device includes providing a substrate structure including a substrate, an interlayer dielectric layer, multiple trenches in the interlayer dielectric layer including first, second, third trenches for forming respective gate structures of first, second, and third transistors, forming an interface layer on the bottom of the trenches; forming a high-k dielectric layer on the interface layer and sidewalls of the trenches; forming a first PMOS work function adjustment layer on the high-k dielectric layer of the third trench; forming a second PMOS work function adjustment layer in the trenches after forming the first PMOS work function adjustment layer; forming an NMOS work function layer in the trenches after forming the second PMOS work function adjustment layer; and forming a barrier layer in the trenches after forming the NMOS work function layer and a metal gate layer on the barrier layer.

Abstract: The application relates to a multi-operating system (multi-OS) device and a notification device. The multi-OS device comprises a processor, a transceiver, and an output device. The processor is configured to host a first operating system (OS1) in a foreground and a second operating system (OS2) in a background, or vice versa. The output device is configured to be controlled by an operating system hosted in the foreground. The transceiver is configured to receive a first signal (S1) from a notification device over a communication system, where the S1 indicates a notification associated to the OS2. The output device is further configured to output the notification associated to the OS2 when the OS1 is hosted in the foreground.

Abstract: A method of manufacturing a semiconductor device includes providing a substrate structure, the substrate structure having a semiconductor substrate including a first semiconductor fin, a first gate structure, and a first mask layer on a first semiconductor region. The method includes forming a second mask layer on the substrate structure, etching first mask layer and second mask layer to expose a portion of a first semiconductor fin not covered by the first gate structure, performing a first ion implantation on an exposed portion of the first semiconductor fin to introduce impurities into a portion of the first semiconductor fin located below the first gate structure, etching the first semiconductor fin to remove a portion of an exposed portion of the first semiconductor fin, and epitaxially growing a first semiconductor material on the remaining portions of the first semiconductor fin to form a first source region and a first drain region.

Abstract: The disclosure discloses a virtual impedance comprehensive control method for an inductive power filtering (IPF) system. According to the disclosure, harmonic damping control at grid side and zero impedance control of filters are organically combined according to a technical problem which is unsolved and process difficulty in equipment manufacturing in an existing filtering method, so that the problem of performance reduction of passive filtering equipment caused by a change in an impedance parameter of a power grid system is solved on one hand, optimization control over a quality factor of the passive filtering equipment may be implemented to reduce dependence on an equipment production process level on the other hand, a quality factor of the single-tuned filters may meet a design requirement, and an overall filtering characteristic is further improved.