Abstract: One illustrative method disclosed herein includes, among other things, forming a multi-layer patterned masking layer comprised of first and second layers of material and first and second openings that extend through both of the first and second layers of material, wherein the first opening is positioned above a first area of the substrate where the DDB isolation structure will be formed and the second opening is positioned above a second area of the substrate where the SDB isolation structure will be formed. The method also includes performing a first process operation through the first opening to form the DDB isolation structure, performing a second process operation to remove the second layer of material and to expose the first opening in the first layer of material, and performing a third process operation through the second opening to form the SDB isolation structure.

Abstract: An image sensor includes a first column pair and a second column pair among a plurality of columns of a pixel array, an analog-to-digital converter pair, and a switch arrangement circuit configured to connect the first column pair with the analog-to-digital converter pair in response to first switch control signals such that two rows among a plurality of rows in the pixel array are read during a single access time.

Abstract: An integrated circuit includes a PMOS gate structure and a gate structure on adjacent field oxide. An epitaxy hard mask is formed over the gate structure on the field oxide so that the epitaxy hard mask overlaps the semiconductor material in PMOS source/drain region. SiGe semiconductor material is epitaxially formed in the source/drain regions, so that that a top edge of the SiGe semiconductor material at the field oxide does not extend more than one third of a depth of the SiGe in the source/drain region abutting the field oxide. Dielectric spacers on lateral surfaces of the gate structure on the field oxide extend onto the SiGe; at least one third of the SiGe is exposed. Metal silicide covers at least one third of a top surface of the SiGe. A contact has at least half of a bottom of the contact directly contacts the metal silicide on the SiGe.

Abstract: Methods of fabricating circuit structures including FinFET structures are provided, including: providing a substrate and a first material having a first threshold voltage above the substrate, and a second material having a second threshold voltage lower than the first threshold voltage above the first material; forming fins having base fin portions formed from the first material and upper fin portions formed from the second material; providing gate structures over the fins to form one or more FinFET structures, wherein the gate structures wrap around at least the upper fin portions and have an operating voltage lower than the first threshold voltage and higher than the second threshold voltage, so that the upper fin portions define a channel size of the one or more FinFET structures. Circuit structures including FinFET structures are also provided, in which the FinFET structures have a uniform channel size defined only by upper fin portions thereof.

Abstract: Integrated circuits and methods fabricating memory cells and integrated circuits are provided. In one embodiment, a method for fabricating a memory cell includes doping a semiconductor substrate to define a conductive region. The method includes forming a stacked structure over the semiconductor substrate. The stacked structure lies over the conductive region and includes a control gate overlying a floating gate. A source line region is formed adjacent a first side of the stacked structure. The method includes forming a contact over the semiconductor substrate and adjacent a second side of the stacked structure to define an electrical current path from the source line region through the conductive region under the stacked structure to the contact.

Abstract: A display device is discussed. The display device includes a substrate having a display area and a pad area in a periphery of the display area, the display area including a plurality of pixel regions; a thin film transistor having a channel layer, and on the substrate; a gate link line and a first common voltage line arranged to cross each other, and having a first insulation film interposed therebetween; a second common voltage line and a data link line arranged to cross each other, and having second insulation film interposed therebetween; a first pattern disposed on the first insulation film; and a second pattern disposed. on the second insulation film, wherein the channel layer, the first pattern and the second pattern are formed of the same material.

Abstract: An image sensor includes a pixel array including at least one active pixel and at least one line-optical black (L-OB) pixel arranged in a matrix including first to nth rows and first to mth columns, the pixel array configured to output a pixel signal and a dark-level offset signal in units of columns during a read-out operation in one of the first to nth rows; a row driver configured to output a selection control signal to the first to nth rows; and an analog-to-digital converter (ADC) block configured to digitize the pixel signal and the dark-level offset signal. In the pixel array, a dark-level offset signal is simultaneously output from an L-OB pixel in another row during the read-out operation in one of the first to nth rows. Here, ‘n’ and ‘m’ each denote an integer that is equal to or greater than ‘2’.

Abstract: An apparatus for controlling an object may include a communicator configured to communicate with a first user terminal and a second user terminal, and a processor configured to control a first object corresponding to a first user in a virtual world to be displayed, configured to control the first object to move in the virtual world in response to a movement control of the first user, configured to randomly select at least one candidate object in response to a morphing control of the first user, and configured to change the first object to a second object when the first user selects the second object from the at least one candidate object. Methods for controlling an object are also provided.

Abstract: Various embodiments provide a method for landing an unmanned aerial vehicle (UAV) in the presence of a wind. The method comprises: performing a first flare-maneuver whilst the UAV is flying. The flare-maneuver causes a front portion of the UAV to rise with respect to a rear portion of the UAV. The method also comprises steering the UAV along a path heading into a direction of the wind. The method further comprises performing a second flare-maneuver before the UAV impacts a landing surface to land. Various embodiments provide a corresponding UAV.

Abstract: A method for tuning a threshold voltage of a semiconductor device includes implanting at least one dopant in a semiconductor substrate at an angle to form a source region and/or a drain region of a transistor. The angle is oblique to a surface of the substrate. Implanting the at least one dopant at the angle alters a flat-band voltage of the transistor and shifts the threshold voltage of the transistor. The at least one dopant or at least one additional dopant can be implanted in a gate electrical contact of the transistor. Implanting the at least one dopant at the oblique angle can change an electrostatic potential of a gate electrical contact of the transistor compared to implanting the at least one dopant at a non-oblique angle, and the change in the electrostatic potential of the gate electrical contact can shift the threshold voltage of the transistor.

Abstract: One illustrative method disclosed herein includes forming first sacrificial gate structures above a fin for two active gates and a dummy gate, removing the first sacrificial gate structure for the dummy gate so as to define a cavity that exposes the fin while leaving the first sacrificial gate structures for the two active gates intact, etching through the cavity to form a trench in the fin under the cavity, forming a second sacrificial gate structure for the dummy gate, removing the first sacrificial gate structures for the two active gates and the second sacrificial gate structure for the dummy gate so as to define a replacement gate cavity for the two active gates and the dummy gate, and forming a replacement gate structure in each of the replacement gate cavities, wherein the replacement gate structure for the dummy gate extends into the trench in the fin.

Abstract: One illustrative method disclosed herein includes forming first sacrificial gate structures above a fin for two active gates and a dummy gate, removing the first sacrificial gate structure for the dummy gate so as to define a cavity that exposes the fin while leaving the first sacrificial gate structures for the two active gates intact, etching through the cavity to form a trench in the fin under the cavity, forming a second sacrificial gate structure for the dummy gate, removing the first sacrificial gate structures for the two active gates and the second sacrificial gate structure for the dummy gate so as to define a replacement gate cavity for the two active gates and the dummy gate, and forming a replacement gate structure in each of the replacement gate cavities, wherein the replacement gate structure for the dummy gate extends into the trench in the fin.

Abstract: A method of contact formation and resulting structure is disclosed. The method includes providing a starting semiconductor structure, the structure including a semiconductor substrate with fins coupled to the substrate, a bottom portion of the fins being surrounded by a first dielectric layer, dummy gates covering a portion of each of the fins, spacers and a cap for each dummy gate, and a lined trench between the gates extending to and exposing the first dielectric layer. The method further includes creating an epitaxy barrier of hard mask material between adjacent fins in the trench, creating N and P type epitaxial material on the fins adjacent opposite sides of the barrier, and creating sacrificial semiconductor epitaxy over the N and P type epitaxial material, such that subsequent removal thereof can be done selective to the N and P type of epitaxial material.

Abstract: Integrated circuits are provided. An exemplary integrated circuit includes a source/drain region in a semiconductor substrate. The integrated circuit includes a charge storage structure overlying the semiconductor substrate and having a first sidewall overlying the source/drain region. The integrated circuit also includes a control gate overlying the source/drain region. Further, the integrated circuit includes a first select gate overlying the semiconductor substrate and adjacent the first sidewall. A first memory cell is formed by the control gate and the first select gate.

Abstract: A method of providing service continuity between cellular communication and device-to-device communication is disclosed. A procedure for switching between cellular communication and device-to-device communication according to an example embodiment of the present invention may include transferring, by a gateway, a D2D bearer creation request message to an MME, transferring, by the MME, the D2D bearer creation request message to a base station, mapping, by the base station, D2D bearer QoS to D2D radio bearer QoS and transmitting an RRC connection reconfiguration message to terminals, receiving, by the base station, an RRC connection reconfiguration completion message indicating creation of a D2D radio bearer from the terminals, transmitting, by the base station, a D2D bearer creation response message indicating creation of a D2D bearer to the MME, and transferring, by the MME, the D2D bearer creation response message to the gateway.

Abstract: The present invention relates to a system test apparatus. The system test apparatus includes an insertion module configured to insert a test agent into a process control block, a hooking module configured to hook a test target to a test code using the test agent when an event related to the test target occurs, a scanning module configured to collect pieces of test information about a process in which the event related to the test target has occurred when the test target is hooked, and a logging module configured to store the pieces of test information collected by the scanning module.

Abstract: Methods for fabricating memory cells, methods for fabricating integrated circuits having memory cells, and integrated circuits having memory cells are provided. In one example, a method for fabricating a memory cell includes depositing a first tunnel dielectric layer over a semiconductor substrate. The method includes depositing a floating gate material over the first tunnel dielectric layer. The method forms two control gate stacks over the floating gate material, defines a source line area between the two control gate stacks, and defines select gate areas adjacent the two control gate stacks. The method includes depositing a second tunnel dielectric layer over the select gate areas of the semiconductor substrate. Further, the method includes forming select gates over the second tunnel dielectric layer over the select gate areas of the semiconductor substrate. The second tunnel dielectric layer forms a gate dielectric layer for each select gate.

Abstract: Methods of fabricating circuit structures including FinFET structures are provided, including: providing a substrate and a first material having a first threshold voltage above the substrate, and a second material having a second threshold voltage lower than the first threshold voltage above the first material; forming fins having base fin portions formed from the first material and upper fin portions formed from the second material; providing gate structures over the fins to form one or more FinFET structures, wherein the gate structures wrap around at least the upper fin portions and have an operating voltage lower than the first threshold voltage and higher than the second threshold voltage, so that the upper fin portions define a channel size of the one or more FinFET structures. Circuit structures including FinFET structures are also provided, in which the FinFET structures have a uniform channel size defined only by upper fin portions thereof.

Abstract: In a high strength and high electrical conductive nano crystalline grain multi-layer copper alloy sheet, a plurality of high strength and high electrical conductive nano crystalline grain multi-layer sheets manufactured by roll-bonding an oxygen free copper (OFC) alloy sheet and a deoxidized low-phosphorous copper (DLP) alloy sheet are plastically bonded by roll-bonding method so that an OFC alloy layer and a DLP alloy layer are alternated to each other to have electrical conductivity of 85 IACS (%) or more and tensile strength of 500 MPa or more.

Abstract: Methods of fabricating circuit structures including FinFET structures are provided, including: providing a substrate and a first material having a first threshold voltage above the substrate, and a second material having a second threshold voltage lower than the first threshold voltage above the first material; forming fins having base fin portions formed from the first material and upper fin portions formed from the second material; providing gate structures over the fins to form one or more FinFET structures, wherein the gate structures wrap around at least the upper fin portions and have an operating voltage lower than the first threshold voltage and higher than the second threshold voltage, so that the upper fin portions define a channel size of the one or more FinFET structures. Circuit structures including FinFET structures are also provided, in which the FinFET structures have a uniform channel size defined only by upper fin portions thereof.