Abstract: A method of providing service continuity between cellular communication and device-to-device communication is disclosed. A procedure for switching between cellular communication and device-to-device communication according to an example embodiment of the present invention may include transferring, by a gateway, a D2D bearer creation request message to an MME, transferring, by the MME, the D2D bearer creation request message to a base station, mapping, by the base station, D2D bearer QoS to D2D radio bearer QoS and transmitting an RRC connection reconfiguration message to terminals, receiving, by the base station, an RRC connection reconfiguration completion message indicating creation of a D2D radio bearer from the terminals, transmitting, by the base station, a D2D bearer creation response message indicating creation of a D2D bearer to the MME, and transferring, by the MME, the D2D bearer creation response message to the gateway.

Abstract: The present invention relates to a system test apparatus. The system test apparatus includes an insertion module configured to insert a test agent into a process control block, a hooking module configured to hook a test target to a test code using the test agent when an event related to the test target occurs, a scanning module configured to collect pieces of test information about a process in which the event related to the test target has occurred when the test target is hooked, and a logging module configured to store the pieces of test information collected by the scanning module.

Abstract: Methods for fabricating memory cells, methods for fabricating integrated circuits having memory cells, and integrated circuits having memory cells are provided. In one example, a method for fabricating a memory cell includes depositing a first tunnel dielectric layer over a semiconductor substrate. The method includes depositing a floating gate material over the first tunnel dielectric layer. The method forms two control gate stacks over the floating gate material, defines a source line area between the two control gate stacks, and defines select gate areas adjacent the two control gate stacks. The method includes depositing a second tunnel dielectric layer over the select gate areas of the semiconductor substrate. Further, the method includes forming select gates over the second tunnel dielectric layer over the select gate areas of the semiconductor substrate. The second tunnel dielectric layer forms a gate dielectric layer for each select gate.

Abstract: Methods of fabricating circuit structures including FinFET structures are provided, including: providing a substrate and a first material having a first threshold voltage above the substrate, and a second material having a second threshold voltage lower than the first threshold voltage above the first material; forming fins having base fin portions formed from the first material and upper fin portions formed from the second material; providing gate structures over the fins to form one or more FinFET structures, wherein the gate structures wrap around at least the upper fin portions and have an operating voltage lower than the first threshold voltage and higher than the second threshold voltage, so that the upper fin portions define a channel size of the one or more FinFET structures. Circuit structures including FinFET structures are also provided, in which the FinFET structures have a uniform channel size defined only by upper fin portions thereof.

Abstract: In a high strength and high electrical conductive nano crystalline grain multi-layer copper alloy sheet, a plurality of high strength and high electrical conductive nano crystalline grain multi-layer sheets manufactured by roll-bonding an oxygen free copper (OFC) alloy sheet and a deoxidized low-phosphorous copper (DLP) alloy sheet are plastically bonded by roll-bonding method so that an OFC alloy layer and a DLP alloy layer are alternated to each other to have electrical conductivity of 85 IACS (%) or more and tensile strength of 500 MPa or more.

Abstract: Methods of fabricating circuit structures including FinFET structures are provided, including: providing a substrate and a first material having a first threshold voltage above the substrate, and a second material having a second threshold voltage lower than the first threshold voltage above the first material; forming fins having base fin portions formed from the first material and upper fin portions formed from the second material; providing gate structures over the fins to form one or more FinFET structures, wherein the gate structures wrap around at least the upper fin portions and have an operating voltage lower than the first threshold voltage and higher than the second threshold voltage, so that the upper fin portions define a channel size of the one or more FinFET structures. Circuit structures including FinFET structures are also provided, in which the FinFET structures have a uniform channel size defined only by upper fin portions thereof.

Abstract: A method of forming raised S/D regions by partial EPI growth with a partial EPI liner therebetween and the resulting device are provided. Embodiments include forming groups of fins extending above a STI layer; forming a gate over the groups of fins; forming a gate spacer on each side of the gate; forming a raised S/D region proximate to each spacer on each fin of the groups of fins, each raised S/D region having a top surface, vertical sidewalls, and an undersurface; forming a liner over and between each raised S/D region; removing the liner from the top surface of each raised S/D region and from in between a group of fins; forming an overgrowth region on the top surface of each raised S/D region; forming an ILD over and between the raised S/D regions; and forming a contact through the ILD, down to the raised S/D regions.

Abstract: A microwave filter for use with a microwave brazing system having a brazing chamber, a vacuum line, and a pressure gauge located proximate the vacuum line. The microwave filter includes a baffle plate configured to be mounted in an opening between the brazing chamber and the pressure gauge, and a plurality of hollow pipes configured to substantially prevent the transmission of microwaves from the brazing chamber to the pressure gauge, and further configured to allow gas to flow between the brazing chamber and the vacuum line.

Abstract: One illustrative method disclosed herein includes, among other things, forming a shared gate cavity that spans across an isolation region and is positioned above first and second active regions, forming at least one layer of material in the shared gate cavity above the first and second active regions and above the isolation region, forming a first masking layer that covers portions of the shared gate cavity positioned above the first and second active regions while exposing a portion of the shared gate cavity positioned above the isolation region, with the first masking layer in position, performing at least one first etching process to remove at least a portion of the at least one layer of material in the exposed portion of the shared gate cavity above the isolation region, and removing the first masking layer.

Abstract: An integrated circuit includes a PMOS gate structure and a gate structure on adjacent field oxide. An epitaxy hard mask is formed over the gate structure on the field oxide so that the epitaxy hard mask overlaps the semiconductor material in PMOS source/drain region. SiGe semiconductor material is epitaxially formed in the source/drain regions, so that that a top edge of the SiGe semiconductor material at the field oxide does not extend more than one third of a depth of the SiGe in the source/drain region abutting the field oxide. Dielectric spacers on lateral surfaces of the gate structure on the field oxide extend onto the SiGe; at least one third of the SiGe is exposed. Metal silicide covers at least one third of a top surface of the SiGe. A contact has at least half of a bottom of the contact directly contacts the metal silicide on the SiGe.

Abstract: A metal-oxide-semiconductor transistor (MOS) and method of fabricating the same, in which the effective channel length is increased relative to the width of the gate electrode. A dummy gate electrode overlying dummy gate dielectric material is formed at the surface of the structure, with self-aligned source/drain regions, and dielectric spacers on the sidewalls of the dummy gate structure. The dummy gate dielectric underlies the sidewall spacers. Following removal of the dummy gate electrode and the underlying dummy gate dielectric material, including from under the spacers, a silicon etch is performed to form a recess in the underlying substrate. This etch is self-limiting on the undercut sides, due to the crystal orientation, relative to the etch of the bottom of the recess. The gate dielectric and gate electrode material are then deposited into the remaining void, for example to form a high-k metal gate MOS transistor.

Abstract: An embedded resistor structure in an integrated circuit that can be formed in a replacement gate high-k metal gate metal-oxide-semiconductor (MOS) technology process flow. The structure is formed by etching a trench into the substrate, either by removing a shallow trench isolation structure or by silicon etch at the desired location. Deposition of the dummy gate polysilicon layer fills the trench with polysilicon; the resistor polysilicon portion is protected from dummy gate polysilicon removal by a hard mask layer. The resistor polysilicon can be doped during source/drain implant, and can have its contact locations silicide-clad without degrading the metal gate electrode.

Abstract: Methods of fabricating fin structures having exposed upper fin portions with a uniform exposure height are disclosed herein. The fabrication methods include providing a substrate with plurality of fins and a dielectric material disposed between and over the plurality of fins, planarizing the dielectric material and the plurality of fins, and uniformly recessing the dielectric material to a pre-selected depth below upper surfaces of the plurality of fins to expose upper fin portions. The exposed upper fin portions, as a result of uniformly recessing the dielectric material, have a uniform exposure height above the recessed dielectric material. A protective film may be provided over the recessed dielectric material and exposed upper fin portions to preserve the uniform exposure height of the upper fin portions. The uniform exposure height of the exposed upper fin portions facilitates subsequent formation of one or more circuit structures above the substrate.

Abstract: A method of forming raised S/D regions by partial EPI growth with a partial EPI liner therebetween and the resulting device are provided. Embodiments include forming groups of fins extending above a STI layer; forming a gate over the groups of fins; forming a gate spacer on each side of the gate; forming a raised S/D region proximate to each spacer on each fin of the groups of fins, each raised S/D region having a top surface, vertical sidewalls, and an undersurface; forming a liner over and between each raised S/D region; removing the liner from the top surface of each raised S/D region and from in between a group of fins; forming an overgrowth region on the top surface of each raised S/D region; forming an ILD over and between the raised S/D regions; and forming a contact through the ILD, down to the raised S/D regions.

Abstract: A method of driving a display panel includes steps of generating a plurality of load signals, of which at least one load signal has a different timing from the rest of the load signals, generating data voltages synchronized to low periods of the load signals and outputting the data voltages to data lines. Accordingly, the data voltages synchronized to each of the load signals can be outputted to each of the data lines. A color coordinate problem occurring when applying a RGBW type may be solved by setting a charging time of a white sub-pixel different from the rest of the sub-pixels. Thus, display quality of a display apparatus including the display panel may be improved.

Abstract: A method of offloading data is provided by a UE. The UE receives data from a macro cell base station over an MC-RB while an E-RAB between the macro cell base station and a gateway is established. The UE receives a first connection reconfiguration message from the macro cell base station after the E-RAB between a small cell base station and the gateway is established, and establishes an SC-RB according to the first connection reconfiguration message. Next, the UE receives a second connection reconfiguration message from the macro cell base station after a path between the macro cell base station and the gateway is switched to a path between the small cell base station and the gateway, and data for the MC-RB are exhausted on the macro cell base station. Then, the UE releases the MC-RB and switches to the SC-RB.

Abstract: Described herein is a technology for facilitating remote monitoring, in accordance with one aspect, image data and corresponding true color data of a region of interest is received by a computer system from a mobile device. The computer system may integrate the image data and the true color data to generate normalized true color data. The normalized true color data may then be mapped to device independent color image data A recommendation may then be sent based on the device-independent color image data.

Abstract: The present invention describes an electronic fuze operable to complement a mechanical point impact fuze. The electronic fuze includes a voltage generator circuit, micro-controller, a piezo-electric sensor, a firing circuit and a safety lockout circuit. When a projectile strikes a target at an optimum angle, the mechanical point impact fuze is activated; when the strike angle is oblique, the mechanical point impact fuze may be ineffective but the piezo-electric sensor is operable to trigger the firing circuit. The safety lockout circuit ensures the firing circuit is operative only after a predetermined delay time when an n-channel FET is turned OFF. The micro-controller also generates a TIME-OUT signal, which provides for self-destruction of a projectile that has failed to explode.

Abstract: An integrated circuit includes a PMOS gate structure and a gate structure on adjacent field oxide. An epitaxy hard mask is formed over the gate structure on the field oxide so that the epitaxy hard mask overlaps the semiconductor material in PMOS source/drain region. SiGe semiconductor material is epitaxially formed in the source/drain regions, so that that a top edge of the SiGe semiconductor material at the field oxide does not extend more than one third of a depth of the SiGe in the source/drain region abutting the field oxide. Dielectric spacers on lateral surfaces of the gate structure on the field oxide extend onto the SiGe; at least one third of the SiGe is exposed. Metal silicide covers at least one third of a top surface of the SiGe. A contact has at least half of a bottom of the contact directly contacts the metal silicide on the SiGe.

Abstract: A method of forming raised S/D regions by partial EPI growth with a partial EPI liner therebetween and the resulting device are provided. Embodiments include forming groups of fins extending above a STI layer; forming a gate over the groups of fins; forming a gate spacer on each side of the gate; forming a raised S/D region proximate to each spacer on each fin of the groups of fins, each raised S/D region having a top surface, vertical sidewalls, and an undersurface; forming a liner over and between each raised S/D region; removing the liner from the top surface of each raised S/D region and from in between a group of fins; forming an overgrowth region on the top surface of each raised S/D region; forming an ILD over and between the raised S/D regions; and forming a contact through the ILD, down to the raised S/D regions.