Abstract: The present specification is related to a method for performing multi-projection and a multi-projection system for minimizing a black offset in a multi-projection environment. The present specification provides the method for performing multi-projection comprising estimating the intensity transfer function (ITF) of a plurality of projectors, calculating an optimal black offset threshold for each of the projectors by using each of the ITFs, and applying the optimal black offset threshold to an image projection by each of the projectors.

Abstract: An embedded resistor structure in an integrated circuit that can be formed in a replacement gate high-k metal gate metal-oxide-semiconductor (MOS) technology process flow. The structure is formed by etching a trench into the substrate, either by removing a shallow trench isolation structure or by silicon etch at the desired location. Deposition of the dummy gate polysilicon layer fills the trench with polysilicon; the resistor polysilicon portion is protected from dummy gate polysilicon removal by a hard mask layer. The resistor polysilicon can be doped during source/drain implant, and can have its contact locations silicide-clad without degrading the metal gate electrode.

Abstract: A protein used as a biomarker for diagnosing IgA nephropathy and TGBM (thin-glomerular-basement-membrane) using urine through a target proteomics method. A diagnosis biomarker protein and a kit for diagnosing IgA nephropathy and TGBM and predicting progress of the nephropathy in advance using the protein are provided. The degree of the progression of the disease can be grasped by detecting IgA nephropathy and TGBM, enabling early diagnosis and confirming progress from the patient's urine. In addition, a monoclonal antibody produced based on the diagnosis biomarker protein can be used for an immunoassay kit (ELISA, antibody coated tube test, lateral-flow test, potable biosensor). The monoclonal antibody is used in early diagnosis and progression detection of IgA nephropathy and development of a novel drug for the purpose of treatment.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. An exemplary method for fabricating an integrated circuit having a split-gate nonvolatile memory device includes forming a charge storage structure overlying a semiconductor substrate and having a first sidewall and a second sidewall and forming an interior cavity. The method forms a control gate in the interior cavity. Further, the method forms a first select gate overlying the semiconductor substrate and adjacent the first sidewall. A first memory cell is formed by the control gate and the first select gate. The method also forms a second select gate overlying the semiconductor substrate and adjacent the second sidewall. A second memory cell is formed by the control gate and the second select gate.

Abstract: Provided is a technology for preventing noisy data from being displayed before valid data is inputted when power is turned on in a liquid crystal display.

Abstract: The present invention relates to a multi-storage case for toothpicks, skewers, and cotton swabs, wherein it is possible to store toothpicks, skewers, and cotton swabs together and to easily withdraw and use the same. In the other words, the present invention comprises: a cylindrical storage body for allowing toothpicks, skewers, and cotton swabs to be stored upright; and a rotatable cover boy inserted and coupled to the outside of the storage body, wherein a withdrawing opening means is provided at the storage body and the covert body to allow toothpicks, skewers, and cotton swabs to be selectively drawn. Therefore, the present invention has improved functionality and convenience since toothpicks, skewers, and cotton swabs are separately stored while standing upright, and it is possible to selectively withdraw toothpicks, skewers, and cotton swabs by the rotations of the cover body.

Abstract: Techniques to recursively discover services in a distributed environment may include receiving a request, including a unique client identifier, from a client device to access a home resource at a services site. The services site may identify which services site is mapped to the client domain of the unique client identifier in the request. If the services site that received the request is not the services site identified by the client domain, the services site that received the request may provide a redirect token that includes a link to the identified services site to the client device. Otherwise, the services site that received the request may provide one or more links to resources in a cluster within the services site. The links to resources may include a link to the requested home resource. Other embodiments are described and claimed.

Abstract: A metal-oxide-semiconductor transistor (MOS) and method of fabricating the same, in which the effective channel length is increased relative to the width of the gate electrode. A dummy gate electrode overlying dummy gate dielectric material is formed at the surface of the structure, with self-aligned source/drain regions, and dielectric spacers on the sidewalls of the dummy gate structure. The dummy gate dielectric underlies the sidewall spacers. Following removal of the dummy gate electrode and the underlying dummy gate dielectric material, including from under the spacers, a silicon etch is performed to form a recess in the underlying substrate. This etch is self-limiting on the undercut sides, due to the crystal orientation, relative to the etch of the bottom of the recess. The gate dielectric and gate electrode material are then deposited into the remaining void, for example to form a high-k metal gate MOS transistor.

Abstract: An embedded resistor structure in an integrated circuit that can be formed in a replacement gate high-k metal gate metal-oxide-semiconductor (MOS) technology process flow. The structure is formed by etching a trench into the substrate, either by removing a shallow trench isolation structure or by silicon etch at the desired location. Deposition of the dummy gate polysilicon layer fills the trench with polysilicon; the resistor polysilicon portion is protected from dummy gate polysilicon removal by a hard mask layer. The resistor polysilicon can be doped during source/drain implant, and can have its contact locations silicide-clad without degrading the metal gate electrode.

Abstract: A dual polysilicon gate of a semiconductor device includes a substrate having a first region, a second region, and a third region, and a channel region with a protrusion structure formed in the substrate of the first region, a gate insulating layer formed over the substrate, a first polysilicon layer filling the channel region, and formed over the gate insulating layer of the first and second regions, a second polysilicon layer formed over the gate insulating layer of the third region, and an insulating layer doped with an impurity, and disposed inside the first polysilicon layer in the channel region.

Abstract: A memory device and a method of making the same are presented. The memory device includes a substrate and a memory cell formed on the substrate. The memory cell includes a single transistor. The single transistor includes a first gate on the substrate which functions as a control gate and a second gate embedded in the substrate which functions as a select gate.

Abstract: A semiconductor device having a substrate; a plurality of pillar structures, wherein each pillar structure includes an active pillar disposed over the substrate; a gate electrode surrounding an outer wall of the active pillar; an interlayer dielectric (ILD) layer insulating adjacent pillar structures; a gate contact penetrating the ILD layer and configured to connect to a sidewall of the gate electrode; and a word line connected to the gate contact.

Abstract: An image sensor includes a pixel array including at least one active pixel and at least one line-optical black (L-OB) pixel arranged in a matrix including first to nth rows and first to mth columns, the pixel array configured to output a pixel signal and a dark-level offset signal in units of columns during a read-out operation in one of the first to nth rows; a row driver configured to output a selection control signal to the first to nth rows; and an analog-to-digital converter (ADC) block configured to digitize the pixel signal and the dark-level offset signal. In the pixel array, a dark-level offset signal is simultaneously output from an L-OB pixel in another row during the read-out operation in one of the first to nth rows. Here, ‘n’ and ‘m’ each denote an integer that is equal to or greater than ‘2’.

Abstract: Disclosed is a prediction method of glomerular filtration rate (GFR) from urine samples after kidney transplantation to provide an information needed for predict renal function after the transplantation, more particularly to a prediction method of glomerular filtration rate (GFR) from urine samples after kidney transplantation, which comprises detecting metabolic profiles of five biomarkers, 5a-androst-3-en-17-one (AS), glycocholic acid (GC), sphingosine (SG), tryptophan (TR) and histidine (HT), from urine samples of patients. Glomerular filtration rate (GFR) after kidney transplantation can be predicted more rapidly and precisely to provide an information needed for predict renal function after the transplantation by using five metabolites as biomarkers. The method provides more specific, sensitive, and reliable biomarkers that monitor clinical outcomes and adverse renal events after kidney transplantation, such as rejection, drug toxicity, delayed graft function, and infection.

Abstract: An analog to digital converter (ADC) can include a multi-input comparison unit configured to compare a pixel voltage from an image sensor, a comparison voltage comprising a stepped voltage modified during a coarse mode of operation, and a ramp voltage comprising a ramped voltage modified to one another during a fine mode of operation, to provide a comparison result signal that indicates whether the comparison voltage combined with the ramp voltage is greater than or less than the pixel voltage. A selection control signal generation unit can receive the comparison result signal and a mode control signal, to indicate the coarse or fine mode, to provide a selection control signal allowing modification of the comparison voltage in the coarse mode and to hold the comparison voltage constant in the fine mode. A reference voltage selection unit can receive the selection control signal to control modification of the comparison voltage.

Abstract: A data transmission device includes a control unit and a delay chain unit. The control unit outputs a first control signal through an nth control signal, where n is a natural number. The delay chain unit includes a first switching element through an nth switching element. The switching elements receive a first data signal through an nth data signal and perform pipelining operations on the first through nth data signals based upon the first through nth control signals, respectively, to output the pipelined data signals as at least one data stream. The switching elements are connected to each other to form at least one data delay chain.

Abstract: A method for discovery in device-to-device communications and an apparatus for the same are disclosed. The method performed in a device-to-device server supporting device-to-device discovery between a discovery terminal and a discoverable terminal may include receiving a device-to-device discovery participation message from the discoverable terminal, requesting a gateway to measure a proximity between the discovery terminal and the discoverable terminal, receiving a proximity measurement result from the gateway, and requesting the discovery terminal and the discoverable terminal to initiate a procedure of device-to-device discovery when the proximity measurement result satisfies a predetermined threshold. Thus, the procedure of device-to-device discovery may be performed efficiently.

Abstract: An image sensor includes a reference voltage generation unit that generates a reference voltage that alternately decreases and increases at a constant rate in an operation mode of the image sensor to convert analog signals of detected incident light to a digital value using the reference voltage to determine an intensity of the incident light with high sensitivity and high signal-to-noise ratio.

Abstract: A raised source/drain MOS transistor is formed in a process that utilizes a first sidewall spacer when implanting a semiconductor region to form the heavily-doped source region and the heavily-doped drain region of the transistor, and a second different sidewall spacer when epitaxially growing the raised source region and the raised drain region of the transistor.

Abstract: An embedded resistor structure in an integrated circuit that can be formed in a replacement gate high-k metal gate metal-oxide-semiconductor (MOS) technology process flow. The structure is formed by etching a trench into the substrate, either by removing a shallow trench isolation structure or by silicon etch at the desired location. Deposition of the dummy gate polysilicon layer fills the trench with polysilicon; the resistor polysilicon portion is protected from dummy gate polysilicon removal by a hard mask layer. The resistor polysilicon can be doped during source/drain implant, and can have its contact locations silicide-clad without degrading the metal gate electrode.