Patents by Inventor Yong Lim

Yong Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8874717
    Abstract: Techniques to recursively discover services in a distributed environment may include receiving a request, including a unique client identifier, from a client device to access a home resource at a services site. The services site may identify which services site is mapped to the client domain of the unique client identifier in the request. If the services site that received the request is not the services site identified by the client domain, the services site that received the request may provide a redirect token that includes a link to the identified services site to the client device. Otherwise, the services site that received the request may provide one or more links to resources in a cluster within the services site. The links to resources may include a link to the requested home resource. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: October 28, 2014
    Assignee: Microsoft Corporation
    Inventors: Yves Pitsch, Rastan Boroujerdi, Amit Sehgal, Santhosh Kopparapu, Yong Lim, Deepak Rao, Vadim Eydelman
  • Patent number: 8865542
    Abstract: An embedded resistor structure in an integrated circuit that can be formed in a replacement gate high-k metal gate metal-oxide-semiconductor (MOS) technology process flow. The structure is formed by etching a trench into the substrate, either by removing a shallow trench isolation structure or by silicon etch at the desired location. Deposition of the dummy gate polysilicon layer fills the trench with polysilicon; the resistor polysilicon portion is protected from dummy gate polysilicon removal by a hard mask layer. The resistor polysilicon can be doped during source/drain implant, and can have its contact locations silicide-clad without degrading the metal gate electrode.
    Type: Grant
    Filed: January 8, 2013
    Date of Patent: October 21, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Kwan-Yong Lim, Ki-Don Lee, Stanley Seungchul Song
  • Patent number: 8865549
    Abstract: A metal-oxide-semiconductor transistor (MOS) and method of fabricating the same, in which the effective channel length is increased relative to the width of the gate electrode. A dummy gate electrode overlying dummy gate dielectric material is formed at the surface of the structure, with self-aligned source/drain regions, and dielectric spacers on the sidewalls of the dummy gate structure. The dummy gate dielectric underlies the sidewall spacers. Following removal of the dummy gate electrode and the underlying dummy gate dielectric material, including from under the spacers, a silicon etch is performed to form a recess in the underlying substrate. This etch is self-limiting on the undercut sides, due to the crystal orientation, relative to the etch of the bottom of the recess. The gate dielectric and gate electrode material are then deposited into the remaining void, for example to form a high-k metal gate MOS transistor.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: October 21, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Kwan-Yong Lim, Stanley Seungchul Song, Amitabh Jain
  • Patent number: 8847322
    Abstract: A dual polysilicon gate of a semiconductor device includes a substrate having a first region, a second region, and a third region, and a channel region with a protrusion structure formed in the substrate of the first region, a gate insulating layer formed over the substrate, a first polysilicon layer filling the channel region, and formed over the gate insulating layer of the first and second regions, a second polysilicon layer formed over the gate insulating layer of the third region, and an insulating layer doped with an impurity, and disposed inside the first polysilicon layer in the channel region.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: September 30, 2014
    Assignee: SK hynix Inc.
    Inventors: Kwan-Yong Lim, Heung-Jae Cho, Min-Gyu Sung
  • Publication number: 20140264554
    Abstract: A memory device and a method of making the same are presented. The memory device includes a substrate and a memory cell formed on the substrate. The memory cell includes a single transistor. The single transistor includes a first gate on the substrate which functions as a control gate and a second gate embedded in the substrate which functions as a select gate.
    Type: Application
    Filed: December 31, 2013
    Publication date: September 18, 2014
    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Khee Yong LIM, Kian Ming TAN, Elgin Kiok Boone QUEK
  • Publication number: 20140252458
    Abstract: A semiconductor device having a substrate; a plurality of pillar structures, wherein each pillar structure includes an active pillar disposed over the substrate; a gate electrode surrounding an outer wall of the active pillar; an interlayer dielectric (ILD) layer insulating adjacent pillar structures; a gate contact penetrating the ILD layer and configured to connect to a sidewall of the gate electrode; and a word line connected to the gate contact.
    Type: Application
    Filed: May 22, 2014
    Publication date: September 11, 2014
    Applicant: SK HYNIX INC.
    Inventors: Min-Gyu SUNG, Yong-Soo KIM, Kwan-Yong LIM
  • Publication number: 20140240569
    Abstract: An image sensor includes a pixel array including at least one active pixel and at least one line-optical black (L-OB) pixel arranged in a matrix including first to nth rows and first to mth columns, the pixel array configured to output a pixel signal and a dark-level offset signal in units of columns during a read-out operation in one of the first to nth rows; a row driver configured to output a selection control signal to the first to nth rows; and an analog-to-digital converter (ADC) block configured to digitize the pixel signal and the dark-level offset signal. In the pixel array, a dark-level offset signal is simultaneously output from an L-OB pixel in another row during the read-out operation in one of the first to nth rows. Here, ‘n’ and ‘m’ each denote an integer that is equal to or greater than ‘2’.
    Type: Application
    Filed: February 20, 2014
    Publication date: August 28, 2014
    Inventors: HAN YANG, Kyoung Min Koh, Yong Lim, Shin Hoo Kim, Ju Ha Kim, Seung Jin Lee, Jae Jin Jung, Kee Moon Chun
  • Publication number: 20140235503
    Abstract: Disclosed is a prediction method of glomerular filtration rate (GFR) from urine samples after kidney transplantation to provide an information needed for predict renal function after the transplantation, more particularly to a prediction method of glomerular filtration rate (GFR) from urine samples after kidney transplantation, which comprises detecting metabolic profiles of five biomarkers, 5a-androst-3-en-17-one (AS), glycocholic acid (GC), sphingosine (SG), tryptophan (TR) and histidine (HT), from urine samples of patients. Glomerular filtration rate (GFR) after kidney transplantation can be predicted more rapidly and precisely to provide an information needed for predict renal function after the transplantation by using five metabolites as biomarkers. The method provides more specific, sensitive, and reliable biomarkers that monitor clinical outcomes and adverse renal events after kidney transplantation, such as rejection, drug toxicity, delayed graft function, and infection.
    Type: Application
    Filed: July 31, 2013
    Publication date: August 21, 2014
    Applicant: KYUNGPOOK NATIONAL UNIVERSITY INDUSTRY-ACADEMIC COOPERATION FOUNDATION
    Inventors: Yong-Lim KIM, Young-Ran YOON, Jung-Ju SEO
  • Patent number: 8810676
    Abstract: An analog to digital converter (ADC) can include a multi-input comparison unit configured to compare a pixel voltage from an image sensor, a comparison voltage comprising a stepped voltage modified during a coarse mode of operation, and a ramp voltage comprising a ramped voltage modified to one another during a fine mode of operation, to provide a comparison result signal that indicates whether the comparison voltage combined with the ramp voltage is greater than or less than the pixel voltage. A selection control signal generation unit can receive the comparison result signal and a mode control signal, to indicate the coarse or fine mode, to provide a selection control signal allowing modification of the comparison voltage in the coarse mode and to hold the comparison voltage constant in the fine mode. A reference voltage selection unit can receive the selection control signal to control modification of the comparison voltage.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: August 19, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Hyun Lim, Kwi-Sung Yoo, Kyoung-Min Koh, Yu-Jin Park, Chi-Ho Hwang, Yong Lim
  • Patent number: 8797063
    Abstract: A data transmission device includes a control unit and a delay chain unit. The control unit outputs a first control signal through an nth control signal, where n is a natural number. The delay chain unit includes a first switching element through an nth switching element. The switching elements receive a first data signal through an nth data signal and perform pipelining operations on the first through nth data signals based upon the first through nth control signals, respectively, to output the pipelined data signals as at least one data stream. The switching elements are connected to each other to form at least one data delay chain.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: August 5, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyo-Jin Choo, Yu-Jin Park, Yong Lim
  • Publication number: 20140194115
    Abstract: A method for discovery in device-to-device communications and an apparatus for the same are disclosed. The method performed in a device-to-device server supporting device-to-device discovery between a discovery terminal and a discoverable terminal may include receiving a device-to-device discovery participation message from the discoverable terminal, requesting a gateway to measure a proximity between the discovery terminal and the discoverable terminal, receiving a proximity measurement result from the gateway, and requesting the discovery terminal and the discoverable terminal to initiate a procedure of device-to-device discovery when the proximity measurement result satisfies a predetermined threshold. Thus, the procedure of device-to-device discovery may be performed efficiently.
    Type: Application
    Filed: January 7, 2014
    Publication date: July 10, 2014
    Applicant: Electronics & Telecommunications Research Institute
    Inventors: Mi Jeong YANG, Soon Yong LIM, Kwang Ryul JUNG, Hyung Deug BAE, You Sun HWANG, Moon Soo JANG, Hyeong Jun PARK, Nam Hoon PARK
  • Patent number: 8773544
    Abstract: An image sensor includes a reference voltage generation unit that generates a reference voltage that alternately decreases and increases at a constant rate in an operation mode of the image sensor to convert analog signals of detected incident light to a digital value using the reference voltage to determine an intensity of the incident light with high sensitivity and high signal-to-noise ratio.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: July 8, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyoung-Min Koh, Seog-Heon Ham, Yong Lim
  • Publication number: 20140183657
    Abstract: An embedded resistor structure in an integrated circuit that can be formed in a replacement gate high-k metal gate metal-oxide-semiconductor (MOS) technology process flow. The structure is formed by etching a trench into the substrate, either by removing a shallow trench isolation structure or by silicon etch at the desired location. Deposition of the dummy gate polysilicon layer fills the trench with polysilicon; the resistor polysilicon portion is protected from dummy gate polysilicon removal by a hard mask layer. The resistor polysilicon can be doped during source/drain implant, and can have its contact locations silicide-clad without degrading the metal gate electrode.
    Type: Application
    Filed: January 8, 2013
    Publication date: July 3, 2014
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kwan-Yong Lim, Ki-Don Lee, Stanley Seungchul Song
  • Publication number: 20140183663
    Abstract: A raised source/drain MOS transistor is formed in a process that utilizes a first sidewall spacer when implanting a semiconductor region to form the heavily-doped source region and the heavily-doped drain region of the transistor, and a second different sidewall spacer when epitaxially growing the raised source region and the raised drain region of the transistor.
    Type: Application
    Filed: December 28, 2012
    Publication date: July 3, 2014
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Seung-Chul Song, James W. Blatchford, Kwan-Yong Lim
  • Patent number: 8767147
    Abstract: A liquid crystal display according to an exemplary embodiment of the present invention includes: a first substrate; a first signal line disposed on the first substrate; a thin film transistor connected to the first signal line; a color filter and a light blocking member disposed on the first substrate; a pixel electrode disposed on the color filter and the light blocking member; and a colored member formed on the pixel electrode and disposed on the light blocking member, the colored member having an upper surface that is generally planar with an upper surface of the color filter.
    Type: Grant
    Filed: October 1, 2010
    Date of Patent: July 1, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Seung-Suk Yang, Young-Goo Song, Jae-Yong Lim, In-Ho Park, Kyung-Suk Jung
  • Publication number: 20140181879
    Abstract: A device-adaptable contents generation device includes a media generation unit that generates, based on rich media content, basic level media having a first resolution and at least one extended level media having a higher resolution by stages than the first resolution, a metadata generation unit that generates metadata which allows selective access to the basic level media and the at least one extended level media generated by the media generation unit, a feature information generation unit that generates feature information about the rich media content, and a database that stores a file of the rich media content containing the feature information, the metadata, the basic level media and the at least one extended level media.
    Type: Application
    Filed: April 3, 2012
    Publication date: June 26, 2014
    Applicant: SK PLANET CO., LTD
    Inventors: Myung Seok Ki, Jihun Cha, Injae Lee, Seong Yong Lim, SangHyun Park, Joong Yun Lee
  • Patent number: 8759906
    Abstract: A semiconductor device having a substrate; a plurality of pillar structures, wherein each pillar structure includes an active pillar disposed over the substrate; a gate electrode surrounding an outer wall of the active pillar; an interlayer dielectric (ILD) layer insulating adjacent pillar structures; a gate contact penetrating the ILD layer and configured to connect to a sidewall of the gate electrode; and a word line connected to the gate contact.
    Type: Grant
    Filed: December 24, 2008
    Date of Patent: June 24, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventors: Min-Gyu Sung, Yong-Soo Kim, Kwan-Yong Lim
  • Patent number: 8754956
    Abstract: A method of k*k subsampling, where k is an integer greater than one, a full frame readout on a plurality of pixels arranged in rows and columns, each pixel belonging to one of at least two sets, a first set configured to sense a first value of an image parameter and a second set configured to sense a second value of the image parameter, the method including sampling signals of k pixels of at least one set in a first row to output subsampled signals, converting the subsampled signals into digital signals having a lower resolution than the full frame readout, repeating sampling and converting for k rows, and adding digital signals for the first to kth rows within the at least one set.
    Type: Grant
    Filed: April 2, 2012
    Date of Patent: June 17, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong Lim, Kyoung Min Koh, Soo Youn Kim
  • Publication number: 20140162633
    Abstract: A method of providing service continuity between cellular communication and device-to-device communication is disclosed. A procedure for switching between cellular communication and device-to-device communication according to an example embodiment of the present invention may include transferring, by a gateway, a D2D bearer creation request message to an MME, transferring, by the MME, the D2D bearer creation request message to a base station, mapping, by the base station, D2D bearer QoS to D2D radio bearer QoS and transmitting an RRC connection reconfiguration message to terminals, receiving, by the base station, an RRC connection reconfiguration completion message indicating creation of a D2D radio bearer from the terminals, transmitting, by the base station, a D2D bearer creation response message indicating creation of a D2D bearer to the MME, and transferring, by the MME, the D2D bearer creation response message to the gateway.
    Type: Application
    Filed: November 26, 2013
    Publication date: June 12, 2014
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: You Sun HWANG, Kwang Ryul JUNG, Mi Jeong YANG, Hyung Deug BAE, Soon Yong LIM, Moon Soo JANG, Hyeong Jun PARK, Nam Hoon PARK
  • Publication number: 20140159142
    Abstract: A metal-oxide-semiconductor transistor (MOS) and method of fabricating the same, in which the effective channel length is increased relative to the width of the gate electrode. A dummy gate electrode overlying dummy gate dielectric material is formed at the surface of the structure, with self-aligned source/drain regions, and dielectric spacers on the sidewalls of the dummy gate structure. The dummy gate dielectric underlies the sidewall spacers. Following removal of the dummy gate electrode and the underlying dummy gate dielectric material, including from under the spacers, a silicon etch is performed to form a recess in the underlying substrate. This etch is self-limiting on the undercut sides, due to the crystal orientation, relative to the etch of the bottom of the recess. The gate dielectric and gate electrode material are then deposited into the remaining void, for example to form a high-k metal gate MOS transistor.
    Type: Application
    Filed: December 7, 2012
    Publication date: June 12, 2014
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kwan-Yong Lim, Stanley Seungchul Song, Amitabh Jain