Patents by Inventor Yong Lim

Yong Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Electro-mechanical fuze for a projectile
    Patent number: 9163916
    Abstract: The present invention describes an electronic fuze (200) operable to complement a mechanical point impact fuze (101). The electronic fuze (200) includes a voltage generator circuit (210), micro-controller (220), a piezo-electric sensor (262), a firing circuit (280) and a safety lockout circuit (290). When a projectile (50) strikes a target at an optimum angle, the mechanical point impact fuze (101) is activated; when the strike angle is oblique, the mechanical point impact fuze may be ineffective but the piezo-electric sensor (262) is operable to trigger the firing circuit (280). The safety lockout circuit (290) ensures the firing circuit (280) is operative only after a predetermined delay time when an n-channel FET (292) is turned OFF. The micro-controller (220) also generates a TIME-OUT signal, which provides for self-destruction of a projectile that has failed to explode.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: October 20, 2015
    Assignee: Advanced Material Engineering Pte Ltd
    Inventors: Cheng Hok Aw, Juan Kiat Jeremy Quek, Yong Lim Thomas Ang, Siwei Huang, Soo Chew Sie
  • SILICIDE FORMATION DUE TO IMPROVED SIGE FACETING
    Publication number: 20150287801
    Abstract: An integrated circuit includes a PMOS gate structure and a gate structure on adjacent field oxide. An epitaxy hard mask is formed over the gate structure on the field oxide so that the epitaxy hard mask overlaps the semiconductor material in PMOS source/drain region. SiGe semiconductor material is epitaxially formed in the source/drain regions, so that that a top edge of the SiGe semiconductor material at the field oxide does not extend more than one third of a depth of the SiGe in the source/drain region abutting the field oxide. Dielectric spacers on lateral surfaces of the gate structure on the field oxide extend onto the SiGe; at least one third of the SiGe is exposed. Metal silicide covers at least one third of a top surface of the SiGe. A contact has at least half of a bottom of the contact directly contacts the metal silicide on the SiGe.
    Type: Application
    Filed: June 19, 2015
    Publication date: October 8, 2015
    Inventors: Shashank S. EKBOTE, Kwan-Yong LIM, Ebenezer ESHUN, Youn Sung CHOI
  • NOVEL COMPACT CHARGE TRAP MULTI-TIME PROGRAMMABLE MEMORY
    Publication number: 20150236034
    Abstract: A memory device requiring no or minimal additional mask for fabrication having a low cost, a small footprint, and multiple-time programming capability is disclosed. Embodiments include: a substrate; a gate stack on the substrate; a source and drain in the substrate at opposite sides, respectively, of the gate stack; a source extension region in the substrate adjacent the source region, wherein no drain extension region is formed on the other side of the gate stack; a tunnel oxide liner on the substrate at each side of the gate stack and on side surfaces of the gate stack; and a charge-trapping (CT) spacer on each tunnel oxide liner.
    Type: Application
    Filed: May 5, 2015
    Publication date: August 20, 2015
    Inventors: Eng Huat TOH, Khee Yong LIM, Shyue Seng TAN, Elgin QUEK
  • DISCOVERY METHOD AND APPARATUS IN TERMINAL-TO-TERMINAL DIRECT COMMUNICATION
    Publication number: 20150215848
    Abstract: A discovery method is provided by a terminal in a terminal-to-terminal direct communication terminal-to-terminal direct communication. The terminal broadcasts a sequence, and receives an echo sequence on the sequence from other terminal. The terminal scrambles discovery information with the sequence, and transmits the scrambled discovery information.
    Type: Application
    Filed: January 15, 2015
    Publication date: July 30, 2015
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Mi Jeong YANG, Soon Yong LIM, Jae Wook SHIN, Pyeong Jung SONG
  • Silicide formation due to improved SiGe faceting
    Patent number: 9093298
    Abstract: An integrated circuit includes a PMOS gate structure and a gate structure on adjacent field oxide. An epitaxy hard mask is formed over the gate structure on the field oxide so that the epitaxy hard mask overlaps the semiconductor material in PMOS source/drain region. SiGe semiconductor material is epitaxially formed in the source/drain regions, so that that a top edge of the SiGe semiconductor material at the field oxide does not extend more than one third of a depth of the SiGe in the source/drain region abutting the field oxide. Dielectric spacers on lateral surfaces of the gate structure on the field oxide extend onto the SiGe; at least one third of the SiGe is exposed. Metal silicide covers at least one third of a top surface of the SiGe. A contact has at least half of a bottom of the contact directly contacts the metal silicide on the SiGe.
    Type: Grant
    Filed: August 22, 2013
    Date of Patent: July 28, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Shashank S. Ekbote, Kwan-Yong Lim, Ebenezer Eshun, Youn Sung Choi
  • METHOD, SYSTEM AND COMPUTER-READABLE RECORDING MEDIA FOR PROVIDING SERVICE SELECTIVELY IN WEBINOS PLATFORM
    Publication number: 20150207778
    Abstract: The present invention relates to a method for providing a service selectively in a webinos platform. The method includes steps of: (a) encrypting a service name corresponding to a PZP belonging to a first personal zone with a specific key while the PZP to the first personal zone is registered in a PZH in the first personal zone and a PZP to a second personal zone is registered in a PZH in the second personal zone; (b) allowing the PZH in the first personal zone to publish the service name encrypted with the specific key; and (c) allowing the PZH in the second personal zone to search the service name encrypted with the specific key by the first personal zone among at least one published service name in at least one personal zone by referring to information on the specific key received from the PZH in the first personal zone.
    Type: Application
    Filed: April 24, 2014
    Publication date: July 23, 2015
    Applicant: Obigo Inc.
    Inventors: Se Kwon Jang, Jae Yong Lim, Jwa Jin Kim, Seung Bok Ryu, Jong Min Moon
  • APPARATUS AND METHOD FOR RECOGNIZING TRAFFIC SIGN BOARD
    Publication number: 20150193663
    Abstract: A method and apparatus for detecting and recognizing a traffic sign using a modified census transform (MCT) feature are disclosed. The traffic sign recognizing method according to an exemplary embodiment of the present invention includes detecting a traffic sign candidate region from an input image using a modified census transform (MCT) feature; verifying whether the candidate region corresponds to a traffic sign using the MCT feature histogram for the candidate region; and lassifying a region of interest into the corresponding traffic sign step by step using the MCT feature histogram for the verified candidate region.
    Type: Application
    Filed: July 15, 2014
    Publication date: July 9, 2015
    Applicant: HYUNDAI MOBIS CO., LTD
    Inventors: Huen OH, Hye Ran BYUN, Tae Woo LEE, Kwang Yong LIM
  • LASER ANNEALS FOR REDUCED DIODE LEAKAGE
    Publication number: 20150187656
    Abstract: An integrated circuit with reduced gate induced drain leakage and with reduced reverse biased diode leakage is formed using a process that employs a first laser anneal, a rapid thermal anneal, and a second laser anneal after implanting the source and drain dopant to improve transistor performance.
    Type: Application
    Filed: December 19, 2014
    Publication date: July 2, 2015
    Inventors: Younsung CHOI, Kwan-Yong LIM, Ebenezer ESHUN
  • Semiconductor device with gate stack structure
    Patent number: 9064854
    Abstract: A semiconductor device includes a first conductive layer, a first intermediate structure over the first conductive layer, a second intermediate structure over the first intermediate structure, and a second conductive layer over the second intermediate structure. The first intermediate structure includes a metal silicide layer and a nitrogen containing metal layer. The second intermediate structure includes at least a nitrogen containing metal silicide layer.
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: June 23, 2015
    Assignee: SK hynix Inc.
    Inventors: Kwan-Yong Lim, Hong-Seon Yang, Heung-Jae Cho, Tae-Kyung Kim, Yong-Soo Kim, Min-Gyu Sung
  • METHOD TO FORM SILICIDE AND CONTACT AT EMBEDDED EPITAXIAL FACET
    Publication number: 20150170972
    Abstract: An integrated circuit with an MOS transistor abutting field oxide and a gate structure on the field oxide adjacent to the MOS transistor and a gap between an epitaxial source/drain and the field oxide is formed with a silicon dioxide-based gap filler in the gap. Metal silicide is formed on the exposed epitaxial source/drain region. A CESL is formed over the integrated circuit and a PMD layer is formed over the CESL. A contact is formed through the PMD layer and CESL to make an electrical connection to the metal silicide on the epitaxial source/drain region.
    Type: Application
    Filed: December 8, 2014
    Publication date: June 18, 2015
    Inventors: Kwan-Yong LIM, James Walter BLATCHFORD, Shashank S. EKBOTE, Younsung CHOI
  • WRAP AROUND PHASE CHANGE MEMORY
    Publication number: 20150162532
    Abstract: A device is disclosed. The device includes a top electrode, a bottom electrode and a storage element between the top and bottom electrodes. The storage element includes a heat generating element disposed on the bottom electrode, a phase change element wrapping around an upper portion of the heat generating element, and a dielectric liner sandwiched between the phase change element and the heat generating element.
    Type: Application
    Filed: February 18, 2015
    Publication date: June 11, 2015
    Inventors: Khee Yong LIM, Zufa ZHANG
  • Compact charge trap multi-time programmable memory
    Patent number: 9054209
    Abstract: A method for enabling fabrication of memory devices requiring no or minimal additional mask for fabrication having a low cost, a small footprint, and multiple-time programming capability is disclosed. Embodiments include: forming a gate stack on a substrate; forming a source extension region in the substrate on one side of the gate stack, wherein no drain extension region is formed on the other side of the gate stack; forming a tunnel oxide liner on side surfaces of the gate stack and on the substrate on each side of the gate stack; forming a charge-trapping spacer on each tunnel oxide liner; and forming a source in the substrate on the one side of the gate stack and a drain in the substrate on the other side of the gate stack.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: June 9, 2015
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Eng Huat Toh, Khee Yong Lim, Shyue Seng Tan, Elgin Quek
  • DATA OFFLOADING METHOD
    Publication number: 20150148046
    Abstract: A method of offloading data is provided by a UE. The UE receives data from a macro cell base station over an MC-RB while an E-RAB between the macro cell base station and a gateway is established. The UE receives a first connection reconfiguration message from the macro cell base station after the E-RAB between a small cell base station and the gateway is established, and establishes an SC-RB according to the first connection reconfiguration message. Next, the UE receives a second connection reconfiguration message from the macro cell base station after a path between the macro cell base station and the gateway is switched to a path between the small cell base station and the gateway, and data for the MC-RB are exhausted on the macro cell base station. Then, the UE releases the MC-RB and switches to the SC-RB.
    Type: Application
    Filed: September 12, 2014
    Publication date: May 28, 2015
    Inventors: Soon Yong LIM, Mi Jeong YANG
  • INTEGRATED CIRCUITS HAVING IMPROVED SPLIT-GATE NONVOLATILE MEMORY DEVICES AND METHODS FOR FABRICATION OF SAME
    Publication number: 20150145024
    Abstract: Integrated circuits are provided. An exemplary integrated circuit includes a source/drain region in a semiconductor substrate. The integrated circuit includes a charge storage structure overlying the semiconductor substrate and having a first sidewall overlying the source/drain region. The integrated circuit also includes a control gate overlying the source/drain region. Further, the integrated circuit includes a first select gate overlying the semiconductor substrate and adjacent the first sidewall. A first memory cell is formed by the control gate and the first select gate.
    Type: Application
    Filed: December 29, 2014
    Publication date: May 28, 2015
    Inventors: Zhang Zufa, Khee Yong Lim, Quek Kiok Boone Elgin
  • DISPLAY APPARATUS AND METHOD OF DRIVING THEREOF
    Publication number: 20150145844
    Abstract: A display apparatus includes a display panel including a plurality of data lines arranged in a first direction, where the data line extends substantially in a second direction, and a plurality of pixels electrically connected to the data lines, and a data driver configured to output a first data voltage and a second data voltage to the data lines and configured to control the number of the data lines which receives the first data voltage and the number of the data lines which receive the second data voltage, where the first data voltage has a positive polarity during a first frame and a negative polarity during a second frame, and the second data voltage has the negative polarity during the first frame and the positive polarity during the second frame.
    Type: Application
    Filed: July 2, 2014
    Publication date: May 28, 2015
    Inventors: Tong-ILL KWAK, Ji-Hye KWON, Min-Su SON, Yong-Oh EOM, Woon-Yong LIM, Ki-Hyun PYUN
  • RAISED SOURCE/DRAIN MOS TRANSISTOR AND METHOD OF FORMING THE TRANSISTOR WITH AN IMPLANT SPACER AND AN EPITAXIAL SPACER
    Publication number: 20150140769
    Abstract: A raised source/drain MOS transistor is formed in a process that utilizes a first sidewall spacer when implanting a semiconductor region to form the heavily-doped source region and the heavily-doped drain region of the transistor, and a second different sidewall spacer when epitaxially growing the raised source region and the raised drain region of the transistor.
    Type: Application
    Filed: January 29, 2015
    Publication date: May 21, 2015
    Inventors: Seung-Chul Song, James W. Blatchford, Kwan-Yong Lim
  • PHOTOGRAPHING DEVICE AND STITCHING METHOD OF CAPTURED IMAGE
    Publication number: 20150138309
    Abstract: A stitching method of a captured image is disclosed. The stitching method includes capturing a plurality of images having different viewing angles, setting a feature point extraction region on the plural images, extracting a plurality of feature points from a plurality of objects in the set region, extracting a combination line connecting corresponding feature points based on the plural extracted feature points, outputting the extracted combination line, and combining the plural images based on the extracted combination line. Accordingly, the stitching method provides an effective and high-quality stitched image.
    Type: Application
    Filed: January 30, 2014
    Publication date: May 21, 2015
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Joo Myoung SEOK, Seong Yong LIM, Yong Ju CHO, Ji Hun CHA
  • Apparatus and method for correcting color of image projection device
    Patent number: 9030485
    Abstract: An apparatus and a method for correcting colors of an image projection device are provided. The method includes: acquiring a photographed image by photographing a sample image projected on projection surface; generating input-output color information for n regions, based on color values of a block in the sample image and corresponding color values of the block in the photographed image; selecting one of the n regions of photographed images as a reference region; generating look-up tables (LUTs) for non-reference regions, based on the reference region and the input and output color information; and correcting colors of input images to be projected by the image projection device using the look-up tables, thereby minimizing color difference of the input images on the projection surface for both intra and inter projection device color correction while simplifying the correction procedure.
    Type: Grant
    Filed: October 23, 2012
    Date of Patent: May 12, 2015
    Assignees: Electronics and Telecommunications Research Institute, National University of Sciences & Technology
    Inventors: Yong Ju Cho, Yong Ju Lee, Seung Kwon Beack, Ji Hun Cha, Seong Yong Lim, Myung Seok Ki, Joo Myoung Seok, Jin Woong Kim, Muhammad Murtaza Khan, Rehan Hafiz, Haris Anis, Mutahir Latif, Ashar Rasul, Arshad Ali
  • METHOD AND APPARATUS FOR PERCEIVING ACCESS BETWEEN TERMINAL AND SMALL CELL
    Publication number: 20150119048
    Abstract: A method and apparatus for perceiving access between a terminal and a small base station is provided. A macro base station transmits a small cell addition/change request message to a small base station that a terminal enters and transmits a message for access to the terminal when receiving a response message from the small base station. Then the macro base station obtains results of access between the terminal and the small base station and determines whether the access between the terminal and the small base station is completed based on the result of access.
    Type: Application
    Filed: October 22, 2014
    Publication date: April 30, 2015
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Mi Jeong YANG, Soon Yong LIM, Kwang Ryul JUNG, Jae Wook SHIN
  • METHOD OF MANUFACURING GRAIN-REFINED ALUMINUM-ZINC-MAGNESIUM-COPPER ALLOY SHEET
    Publication number: 20150114522
    Abstract: Provided is a method of manufacturing a grain-refined aluminum-zinc-magnesium-copper alloy sheet, including manufacturing an aluminum alloy sheet from an aluminum-zinc-magnesium-copper alloy melt by twin-roll strip casting, primarily rolling the aluminum alloy sheet manufactured in step 1, cold rolling the aluminum alloy sheet manufactured in step 2, and performing a heat treatment on the aluminum alloy sheet manufactured in step 3, thereby reducing processing time and cost by using twin-roll casting. Since grain refinement and homogenization of the sheet manufactured by the twin-roll casting are maximized by sequentially performing warm rolling, cold rolling, and a heat treatment on the sheet, elongation may be improved.
    Type: Application
    Filed: December 17, 2014
    Publication date: April 30, 2015
    Inventors: Hyoung-Wook Kim, Yun-Soo Lee, Cha Yong Lim, Jae Hyung Cho