Abstract: A coating composition, a method for producing the coating composition, a coating film and magnetic recording medium are described. The coating composition comprises a binder, a solvent, and an ?-alumina powder, wherein the ?-alumina powder satisfies the following (a) and (b): (a) when the ?-alumina powder is pressed to obtain a green body and the green body is sintered at 1250° C.

Abstract: A method for producing ?-alumina powder is described. The method comprises the steps of removing water from a compound containing the following (1), (2), (3) and (4), and calcining the results: (1) ?-alumina precursor, (2) seed crystal, (3) water, (4) nitrate ion in an amount of from 2.8 to 3.3 mol per mol of aluminum (Al) contained in the ?-alumina precursor and the seed crystal.

Abstract: A method for producing an &agr;-alumina powder is described. The method for producing an &agr;-alumina powder comprises a step of calcining an aluminum salt in the presence of a seed crystal at 600-890° C.

Abstract: A method for producing an &agr;-alumina particulate is described.

Abstract: A chain type ferroelectric random access memory has a memory cell unit including ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier. A value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.

Abstract: An &agr;-alumina powder suitably used as an additive to a magnetic recording medium and a method of producing the same are described.

Abstract: A semiconductor device includes an internal power supply, at least one semiconductor circuit block, a delay circuit, and a detecting circuit. The internal power supply outputs an initialization completion signal when initialized. The semiconductor circuit block operates on the basis of a voltage generated by the internal power supply. The delay circuit delays the initialization completion signal. The detecting circuit commands the semiconductor circuit block to start operations in response to the initialization completion signal delayed by the delay circuit and an externally input first input signal.

Abstract: A ferroelectric memory has a memory cell array of memory cells having ferroelectric capacitors, which is divided into a plurality of blocks, a boost power circuit provided in each block of the memory cell array to generate a boost voltage required for operation of the memory, a boost power switch provided between a power line connected to an external power terminal and a power supply terminal of each boost power circuit, and remaining ON during normal operation of the memory, a voltage detector circuit for detecting a drop of voltage level of the power line, and a switch control circuit for turning off the boost power switches in the blocks of the memory cell array excluding the boost power switch in a currently selected block in response to the voltage detector circuit.

Abstract: A chain type ferroelectric random access memory has a memory cell unit comprising ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier, and that a value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.

Abstract: An optical fiber collimator array includes an optical fiber array block and a microlens array substrate. The optical fiber array block includes an angled surface and is configured to receive and retain a plurality of individual optical fibers, which carry optical signals. The microlens array substrate includes a plurality of microlenses integrated along a microlens surface and a sloped surface opposite the microlens surface. The microlens surface is coupled to the angled surface such that the optical signals from the individual optical fibers are each collimated by a different one of the integrated microlenses.

Abstract: A ferroelectric memory has a memory cell array of memory cells having ferroelectric capacitors, which is divided into a plurality of blocks, a boost power circuit provided in each block of the memory cell array to generate a boost voltage required for operation of the memory, a boost power switch provided between a power line connected to an external power terminal and a power supply terminal of each boost power circuit, and remaining ON during normal operation of the memory, a voltage detector circuit for detecting a drop of voltage level of the power line, and a switch control circuit for turning off the boost power switches in the blocks of the memory cell array excluding the boost power switch in a currently selected block in response to the voltage detector circuit.

Abstract: A calcined alumina, its production method and fine a alumina powder obtained by using the calcined alumina are described. The calcined alumina has the SET specific surface area of 10 to 20 m2/g, the main crystal phase of &agr; phase, a &thgr; phase not substantially contained, and the average particle size of 0.5 &mgr;m or less. The method for producing the calcined alumina comprising calcining an aluminum-containing substance containing substantially no metal element other than aluminum in an atmosphere having a partial pressure of water vapor of 600 Pa or less. The fine &agr;-alumina powder having a purity of 99.99% or more and a BET specific surface area of 15 m2/g or more, containing substantially no transition alumina, and providing, when calcined at 1250° C. under normal pressure, a sintered body having a relative density of 95% or more.

Abstract: Titanium oxide exhibiting a superior photocatalytic activity through irradiation of a visible light as well as an ultraviolet light, and a photocatalyst and a photocatalytic coating agent including said titanium oxide, wherein said titanium oxide has a value of an index X1 calculated by the following equation (I) of not more than about 0.90, and a value of an index Y1 calculated by the following equation (II) of not less than 0.

Abstract: An optical fiber collimator array includes an optical fiber array block and a microlens array substrate. The optical fiber array block includes an angled surface and is configured to receive and retain a plurality of individual optical fibers, which carry optical signals. The microlens array substrate includes a plurality of microlenses integrated along a microlens surface and a sloped surface opposite the microlens surface. The microlens surface is coupled to the angled surface such that the optical signals from the individual optical fibers are each collimated by a different one of the integrated microlenses.

Abstract: The present invention provides a polarizer-attached optical fiber ferrule, a polarizer-attached optical fiber connector, and a polarized-attached optical fiber connector adapter for coupling a linear polarizer with one or more optical fibers without employing a lens. The polarizer-attached optical fiber connector 2 is equipped with an optical fiber 10, a ferrule 5 fitted on the periphery of the optical fiber 10 and equipped with a slit 16 reaching the optical fiber 10, and a linear polarizer 18 inserted into the slit 16 so that it crosses the optical fiber 10.

Abstract: A semiconductor integrated circuit device includes a memory, /CE transition detector, address transition detector, /WE transition detector and controller. The controller includes a timeout circuit. The timeout circuit generates an internal circuit control signal with preset width to control access to the memory based on detection results of the above transition detectors. The operation of the memory is controlled by the timeout circuit at the read time. The operation of the memory is controlled by the timeout circuit when transition of the end of a /WE signal is detected by the /WE transition detector before a timing specified by the timeout circuit at the write time. Further, the operation of the memory is controlled in response to the transition of the /WE signal when the transition of the end of the /WE signal is detected by the /WE transition detector after passage of the above timing.

Abstract: A sensor for converting a physical quantity into an electric signal and issuing the output is driven by a drive circuit which is driven by a drive signal issued from a 1-chip microcomputer. The 1-chip microcomputer judges fault of sensor function when the sensor output signal is out of a specified output range. Further, when stopping the operation of the drive circuit, if the sensor output signal does not coincide with a specific value, the 1-chip microcomputer also judges fault of sensor function. According to the invention, in the event of a trouble of sensor function allowing the sensor output signal to settle within an output range, such trouble can be detected.

Abstract: A chain type ferroelectric random access memory has a memory cell unit comprising ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier, and that a value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.

Abstract: A semiconductor integrated circuit includes a first address transition detecting circuit which detects transitions of a row address signal and a column address signal of a memory cell array, a second address transition detecting circuit which detects only the transition of the column address signal, a control circuit which generates an internal circuit control signal with a desired period of time required for row access based on only a first detection signal and generates a column-related circuit control signal with a desired period of time required for column access to the memory cell array based on only a second detection signal, and a mode discriminator which determines one of the row access and the column access to be made and performs the access control operation based on the determination result.

Abstract: A chain type ferroelectric random access memory has a memory cell unit comprising ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier, and that a value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.