Patents by Inventor Yoshiyuki Matsunaga

Yoshiyuki Matsunaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060192263
    Abstract: In each photosensitive cell, a photodiode 101, a transfer gate 102, a floating diffusion layer section 103, an amplifier transistor 104, and a reset transistor 105 are formed in one active region surrounded by a device isolation region. The floating diffusion layer section 103 included in one photosensitive cell is connected not to the amplifier transistor 104 included in that cell but to the gate of the amplifier transistor 104 included in another photosensitive cell adjacent to the one photosensitive cell in the column direction. A polysilicon wire 111 connects the transfer gates 102 arranged in the same row, and a polysilicon wire 112 connects the reset transistors 105 arranged in the same row. For connection in the row direction, only polysilicon wires are used.
    Type: Application
    Filed: April 4, 2006
    Publication date: August 31, 2006
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Makoto Inagaki, Yoshiyuki Matsunaga
  • Publication number: 20060158540
    Abstract: A solid-state image pickup device consists of a plurality of pixels arranged in a matrix for outputting an image signal corresponding to the received light intensity. The solid-state image pickup device includes: reset switches (13,23) for opening/closing between a VDDCELL that repeatedly and cyclically outputs a high potential and a low potential and an electric charge holding section in each pixel; reset signal lines (97,98) connected to pixels of the same row; a row scan circuit (80) for successively selecting rows, always giving Hi impedance or Lo impedance to the reset signal of the selected row and Hi impedance to the reset signal lines of the non-selected row; and an ALLRS circuit 94 for giving the Lo potential to the reset line of the non-selected row before and after the rise of VDCELL from a low potential to high potential. Thus, the solid-state image pickup device can reduce its size and increase its operation speed while suppressing lowering of the dynamic range.
    Type: Application
    Filed: April 5, 2004
    Publication date: July 20, 2006
    Inventors: Masashi Murakami, Masayuki Masuyama, Yoshiyuki Matsunaga
  • Publication number: 20060146160
    Abstract: A digital camera 100 includes an imaging device having a plurality of unit cells, each generating and accumulating therein a piece of luminance information in accordance with an amount of received light. The imaging device comprises: a receiving unit 103 operable to receive a shooting instruction from outside; an all-reset unit 104 operable to simultaneously reset all the unit cells in response to the shooting instruction while a light-shielding gate is open; a light-shielding unit 101 operable to close the light-shielding gate to simultaneously block light incident on all the unit cells when, after the all-reset unit resets all the unit cells, a total length of periods for which the light-shielding gate has been open reaches an exposure time; and a reading unit 105 operable to sequentially read pieces of the luminance information from all the unit cells while the light-shielding gate is closed.
    Type: Application
    Filed: December 6, 2005
    Publication date: July 6, 2006
    Inventors: Masashi Murakami, Masayuki Masuyama, Yoshiyuki Matsunaga
  • Patent number: 7060960
    Abstract: A solid-state imaging device that achieves a reduction in variations appearing on a reproducing screen is provided. The solid-state imaging device includes a plurality of pixel cells that are laid out in matrix form on a semiconductor substrate and a driving unit that is provided to drive the plurality of pixel cells. Each of the plurality of pixel cells includes a photodiode, a MOS transistor, and an element isolating portion 2 that is formed so that the photodiode and the MOS transistor are isolated from each other. The element isolating portion 2 is formed of a STI (Shallow Trench Isolation) that is a grooved portion of the semiconductor substrate. In the semiconductor substrate 7, a STI leakage stopper 1 in which an impurity of a conductive type opposite to a conductive type of source/drain regions in the MOS transistor is introduced is formed to enclose side walls and a bottom face of the element isolating portion 2.
    Type: Grant
    Filed: December 4, 2003
    Date of Patent: June 13, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Sougo Ohta, Mikiya Uchida, Yoshiyuki Matsunaga
  • Publication number: 20060076582
    Abstract: A high-performance solid-state imaging device is provided. The solid-state imaging device includes: a plurality of pixel cells; and a driving unit. Each of the plurality of pixel cells includes: a photodiode that converts incident light into a signal charge and stores the signal charge; a MOS transistor that is provided for reading out the signal charge stored in the photodiode; an element isolation portion that is formed of a STI that is a grooved portion of the semiconductor substrate so that the photodiode and the MOS transistor are isolated from each other; and a deep-portion isolation implantation layer that is formed under the element isolation portion for preventing a flow of a charge from the photodiode to the MOS transistor.
    Type: Application
    Filed: December 2, 2005
    Publication date: April 13, 2006
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Hiroki Nagasaki, Syouji Tanaka, Yoshiyuki Matsunaga
  • Publication number: 20060050161
    Abstract: Photosensitive cells each includes a photodiode (1), a transfer gate (2), a floating diffusion layer portion (3), an amplifying transistor (4), and a reset transistor (5). Drains of the amplifying transistors (4) of the photosensitive cells are connected to a power supply line (10), and a pulsed power supply voltage (VddC) is applied to the power supply line (10). Here, a low-level potential (VddC_L) of the power supply voltage has a predetermined potential higher than zero potential. Specifically, by making the low-level potential (VddC_L) higher than channel potentials obtained when a low level is applied to the reset transistors (5), or channel potentials obtained when a low level is applied to the transfer gates (2), or channel potentials of the photodiodes (1), a reproduced image with low noise is read.
    Type: Application
    Filed: February 26, 2004
    Publication date: March 9, 2006
    Inventors: Makoto Inagaki, Yoshiyuki Matsunaga
  • Publication number: 20050225653
    Abstract: The image pickup device comprises: an image pickup unit 1 in which a plurality of unit cells for generating reset and read voltages are arranged; a noise eliminating unit 6 for generating, with respect to each unit cell, a differential voltage corresponding to a difference between the reset and read voltages; and output units 5 and 7 for outputting the read and differential voltages, respectively, to a signal processing apparatus. The signal processing apparatus comprises: a judging unit 8 for judging whether each of the read voltages is within a predetermined range; and a system output unit 9 for outputting, for unit cells whose voltages are judged as being within the predetermined range, corresponding differential voltages as luminance information of the unit cells; for unit cells whose voltages are judged as not being within the predetermined range, a predetermined voltage indicating high luminance as luminance information of the unit cells.
    Type: Application
    Filed: April 5, 2005
    Publication date: October 13, 2005
    Inventors: Masayuki Masuyama, Yoshiyuki Matsunaga, Masashi Murakami
  • Publication number: 20050167705
    Abstract: An object of the present invention is to provide a shift register in which it is prevented from malfunctioning because of a portion between a first transistor and a second transistor being in a high-impedance state. The shift register of the present invention includes capacitor means 5 for storing data outputted from a unit circuit 1 of the preceding block. A first transistor 3 is turned ON only when data is being stored in the capacitor means 5. A second transistor 7 includes a control electrode and an input-side diffusion layer connected to the output-side diffusion layer of the first transistor 3, and is turned ON only when a pulse of a clock signal from the first transistor 3 is inputted to the control electrode and the input-side diffusion layer. Potential controlling means 2 keeps the second transistor 7 OFF at least during a period in which the second transistor 7 is supposed to be OFF.
    Type: Application
    Filed: January 14, 2005
    Publication date: August 4, 2005
    Inventors: Masashi Murakami, Yoshiyuki Matsunaga, Masayuki Masuyama
  • Publication number: 20050012839
    Abstract: An MOS-type solid-state imaging apparatus includes an imaging region formed by two-dimensionally arranging unit cells serving as photoelectric conversion portions on a semiconductor substrate, a plurality of vertical address lines arranged in a row direction of the imaging region to select a row of unit cells to be addressed, a plurality of vertical signal lines arranged in a column direction of the imaging region to read out signals from the unit cells in each column, a plurality of load transistors each connected to one end of each of the vertical signal lines, and a plurality of horizontal selection transistors each connected to the other end of each of the vertical signal lines.
    Type: Application
    Filed: August 12, 2004
    Publication date: January 20, 2005
    Inventors: Yoshiyuki Matsunaga, Shinji Ohsawa, Nobuo Nakamura, Hirofumi Yamashita, Hiroki Miura
  • Publication number: 20040239786
    Abstract: An imaging device outputs brightness information according to an amount of incident light and includes: an imaging unit that includes a plurality of unit cells arranged one dimensionally or two-dimensionally, each unit cell including a photoelectric conversion part that generates a first output voltage in a reset state and a second output voltage according to an amount of incident light, and each unit cell generating a reset voltage that corresponds to the first output voltage and a read voltage that corresponds to the second output voltage; and an output unit operable to output, in relation to each unit cell, brightness information indicating a difference between the reset voltage and the read voltage when the read voltage is in a predetermined range, and brightness information indicating high brightness when the read voltage is not in the predetermined range.
    Type: Application
    Filed: March 25, 2004
    Publication date: December 2, 2004
    Inventors: Masayuki Masuyama, Masashi Murakami, Yoshiyuki Matsunaga
  • Patent number: 6815879
    Abstract: A circular fluorescent lamp comprises a light-transmitting circular tube, filled with a discharge gas including mercury and a rare gas, having an outer diameter between about 14 mm and 18 mm. A phosphor layer is coated on the inner surface of the light-transmitting circular tube. A stem seals each end of the light-transmitting circular tube air-tightly, and holds a pair of conductive wires. One of the ends of each pair are connected to a filament, and the other of the ends extend outwardly from the circular tube. A lamp base is arranged between the ends of the light-transmitting circular tube so as to rotate slightly around the center axis of the circular tube and includes conductive pins, which are connected to the conductive wires. An insulator, arranged between at least one pair of the conductive wires, limits the movement of the conductive wires. The circular fluorescent lamp may be used for a lighting fixture.
    Type: Grant
    Filed: February 15, 2001
    Date of Patent: November 9, 2004
    Assignee: Toshiba Lighting & Technology Corporation
    Inventors: Toshiyuki Nakamura, Yoshiyuki Matsunaga
  • Publication number: 20040201732
    Abstract: An imaging device chip set includes an imaging chip provided for obtaining an electric signal by photoelectric conversion of incident light, and a DSP chip provided for carrying out digital signal processing with respect to the electric signal obtained by the imaging chip. The imaging chip includes a plurality of unit pixels for generating the electric signal by the photoelectric conversion of incident light, a horizontal scanning circuit for selecting the unit pixels in a horizontal direction, and a vertical scanning circuit for selecting the unit pixels in a vertical direction. The DSP chip includes a timing generating circuit for generating timing pulses necessary for operations of the horizontal scanning circuit and the vertical scanning circuit, and a digital signal processing circuit for carrying out digital signal processing with respect to the electric signal generated by the plurality of unit pixels.
    Type: Application
    Filed: September 9, 2003
    Publication date: October 14, 2004
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO.
    Inventors: Shigetaka Kasuga, Yoshiyuki Matsunaga, Kazuyuki Inokuma
  • Publication number: 20040188729
    Abstract: A solid-state imaging apparatus includes a plurality of photosensitive cells, and a driving unit provided for driving the plurality of photosensitive cells. Each photosensitive cell includes a photodiode formed to be exposed on a surface of a semiconductor substrate for the purpose of accumulating signal charge obtained by subjecting incident light to photoelectric conversion, a transfer transistor for transferring signal charge accumulated by the photodiode, a floating diffusion layer for temporarily accumulating signal charge transferred by the transfer transistor, and an amplifier transistor for amplifying signal charge temporarily accumulated in the floating diffusion layer. A source/drain diffusion layer provided in the amplifier transistor is covered with a salicide layer, and the floating diffusion layer is formed to be exposed on a surface of the semiconductor substrate.
    Type: Application
    Filed: March 25, 2004
    Publication date: September 30, 2004
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Mikiya Uchida, Yoshiyuki Matsunaga, Makoto Inagaki
  • Patent number: 6794801
    Abstract: A compact selfballasted fluorescent lamp includes a fluorescent arc tube forming a crooked discharge path, a housing comprised of a first end portion open to be fit thereon with a bulb-base, a middle portion and a second end portion open to be mounted thereto with the fluorescent arc tube, a lighting circuit module accommodated in the housing, the unit being provided with a circuit board and two or more circuit components mounted on the circuit board for constituting a lighting circuit for lighting the fluorescent arc tube, and a thermal conductor having a thermal conductivity of 0.1 W/(m·K) or more, which is filled in the housing, extending upwards from a components mounting side of the circuit board of the lighting circuit module and contacting with the inner wall of the housing lying on the side of the first end portion of the housing, thereby covering at least one of the circuit components of the lighting circuit.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: September 21, 2004
    Assignee: Toshiba Lighting & Technology Corporation
    Inventors: Takeo Yasuda, Masahiro Toda, Shinichiro Matsumoto, Tsutomu Araki, Toshiyuki Hiraoka, Yoshiyuki Matsunaga
  • Patent number: 6795121
    Abstract: An MOS-type solid-state imaging apparatus includes an imaging region formed by two-dimensionally arranging unit cells serving as photoelectric conversion portions on a semiconductor substrate, a plurality of vertical address lines arranged in a row direction of the imaging region to select a row of unit cells to be addressed, a plurality of vertical signal lines arranged in a column direction of the imaging region to read out signals from the unit cells in each column, a plurality of load transistors each connected to one end of each of the vertical signal lines, and a plurality of horizontal selection transistors each connected to the other end of each of the vertical signal lines.
    Type: Grant
    Filed: December 12, 2000
    Date of Patent: September 21, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiyuki Matsunaga, Shinji Ohsawa, Nobuo Nakamura, Hirofumi Yamashita, Hiroki Miura
  • Publication number: 20040173824
    Abstract: A high-performance solid-state imaging device is provided. The solid-state imaging device includes: a plurality of pixel cells; and a driving unit. Each of the plurality of pixel cells includes: a photodiode that converts incident light into a signal charge and stores the signal charge; a MOS transistor that is provided for reading out the signal charge stored in the photodiode; an element isolation portion that is formed of a STI that is a grooved portion of the semiconductor substrate so that the photodiode and the MOS transistor are isolated from each other; and a deep-portion isolation implantation layer that is formed under the element isolation portion for preventing a flow of a charge from the photodiode to the MOS transistor.
    Type: Application
    Filed: December 19, 2003
    Publication date: September 9, 2004
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO. LTD.
    Inventors: Hiroki Nagasaki, Syouji Tanaka, Yoshiyuki Matsunaga
  • Publication number: 20040173864
    Abstract: In each photosensitive cell, a photodiode 101, a transfer gate 102, a floating diffusion layer section 103, an amplifier transistor 104, and a reset transistor 105 are formed in one active region surrounded by a device isolation region. The floating diffusion layer section 103 included in one photosensitive cell is connected not to the amplifier transistor 104 included in that cell but to the gate of the amplifier transistor 104 included in another photosensitive cell adjacent to the one photosensitive cell in the column direction. A polysilicon wire 111 connects the transfer gates 102 arranged in the same row, and a polysilicon wire 112 connects the reset transistors 105 arranged in the same row. For connection in the row direction, only polysilicon wires are used.
    Type: Application
    Filed: January 9, 2004
    Publication date: September 9, 2004
    Inventors: Makoto Inagaki, Yoshiyuki Matsunaga
  • Publication number: 20040165092
    Abstract: A solid-state imaging device can be provided by which a signal charge stored in a photodiode can be transferred completely even when a power supply voltage is low. The solid-state imaging device includes: a plurality of pixel cells arranged on a semiconductor substrate; and a driving unit that is provided for driving the plurality of pixel cells. Each of the plurality of pixel cells includes: a photodiode that converts incident light into a signal charge and stores the signal charge; a transfer transistor that is provided for reading out the signal charge stored in the photodiode; and a potential smoothing unit that is formed so as to allow a potential from the photodiode to the transfer transistor to change smoothly.
    Type: Application
    Filed: December 8, 2003
    Publication date: August 26, 2004
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO. LTD.
    Inventors: Syouji Tanaka, Yoshiyuki Matsunaga
  • Publication number: 20040164227
    Abstract: A solid-state imaging device that achieves a reduction in variations appearing on a reproducing screen is provided. The solid-state imaging device includes a plurality of pixel cells that are laid out in matrix form on a semiconductor substrate and a driving unit that is provided to drive the plurality of pixel cells. Each of the plurality of pixel cells includes a photodiode, a MOS transistor, and an element isolating portion 2 that is formed so that the photodiode and the MOS transistor are isolated from each other. The element isolating portion 2 is formed of a STI (Shallow Trench Isolation) that is a grooved portion of the semiconductor substrate. In the semiconductor substrate 7, a STI leakage stopper 1 in which an impurity of a conductive type opposite to a conductive type of source/drain regions in the MOS transistor is introduced is formed to enclose side walls and a bottom face of the element isolating portion 2.
    Type: Application
    Filed: December 4, 2003
    Publication date: August 26, 2004
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Sougo Ohta, Mikiya Uchida, Yoshiyuki Matsunaga
  • Patent number: 6714247
    Abstract: An area image sensor outputs the difference between charges received by light-receiving cells arranged in an array pattern. A system controller generates a timing signal for generating a pulse or modulation signal. A control signal generator generates a control signal for separately controlling the light-receiving timings of the light-receiving cells of the area image sensor on the basis of the timing signal from the system controller. A light emitting controller controls a light source to generate light, the intensity of which changes on the basis of the timing signal from the system controller. A reflected light image processor extracts a reflected image of an object from the difference outputted from the area image sensor.
    Type: Grant
    Filed: March 16, 1999
    Date of Patent: March 30, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shunichi Numazaki, Miwako Doi, Yoshiyuki Matsunaga, Akira Morishita, Naoko Umeki