Abstract: A method includes creating a plurality of groups of paths from a plurality of paths in an integrated circuit (IC) layout diagram. Each group has a unique dominant feature among a plurality of features of the plurality of paths. The method further includes testing a path in a group and, when the path fails, modifying at least one of the IC layout diagram, at least a portion of at least one library having cells included in the IC layout diagram, or a manufacturing process for manufacturing an IC corresponding to the IC layout diagram. The plurality of features includes a numerical feature having a numerical value, and a categorical feature having a non-numerical value. The non-numerical value is converted into a converted numerical value. The plurality of groups is created based on the numerical value of the numerical feature, and the converted numerical value of the categorical feature.

Abstract: A vehicle indoor illumination device includes a housing having an upper opening with an internal space formed therein, a light-emitting unit disposed on the housing to emit light, a diffuser disposed outside the light-emitting unit in a manner as to close the upper opening of the housing to allow the light emitted from the light-emitting unit to diffuse to the outside, a cover part disposed on an outer surface of the diffuser and on which a light pattern is formed through scattering of the light transmitted through the diffuser, and a controller configured to receive an operation signal of a vehicle electronic part to control an operation of the light-emitting unit.

Abstract: A light emitting display apparatus and a driving method thereof. The light emitting display apparatus includes a display panel configured to display an image, a timing controller including an on bias stress (OBS) voltage calculator configured to calculate an optimal OBS voltage value on the basis of a refresh rate of the display panel and a data signal which is to be supplied to the display panel, and a power supply configured to generate an OBS voltage which is to be supplied to the display panel, on the basis of the optimal OBS voltage value.

Abstract: A system includes a diffractive optical element configured to receive a first beam and a second beam interfering with one another to generate a first interference pattern. The diffractive optical element is also configured to forwardly diffract the first beam and the second beam to output a third beam and a fourth beam. The third beam and the fourth beam interfere with one another to generate a second interference pattern. The system also includes a detector configured to detect the second interference pattern.

Abstract: A low power PAM-4 output transmitter is disclosed. The lower power PAM-4 output transmitter comprises a first source series terminated SST branch configured to include unit cells having transistors which are selectively activated in response to an input signal outputted from an encoder; a second SST branch configured to include unit cells having transistors which are selectively activated in response to a negative signal of the input signal; and a common voltage switch H3 configured to short or open the first SST branch and the second SST branch. Here, differential signals are outputted from both terminals of the first SST branch and the second SST branch by making the first SST branch and the second SST branch short or open according to an operation of the common voltage switch.

Abstract: A method (of manufacturing a semiconductor device) includes: migrating a circuit design from a first netlist corresponding with a first semiconductor process technology (SPT) to a second netlist corresponding with a second SPT, at least the second netlist being stored on a non-transitory computer-readable medium, the migrating including: generating first versions correspondingly of the first and second netlists; abstracting selected components in the first version of the second netlist and correspondingly in the first version of the second netlist to form corresponding second versions of the second and first netlists; performing a logic equivalence check (LEC) between the second versions of the first and second netlists, thereby identifying migration errors; and revising the second version of the second netlist to reduce the migration errors, thereby resulting in a third version of the second netlist.

Abstract: Various embodiments of stacked structures, process steps and methods are provided herein for etching high aspect ratio features (e.g., contact holes, vias, trenches, etc.) within a stacked structure comprising a hard mask layer, which is formed above and in contact with one or more underlying layers. At least one etch stop layer (ESL) is provided within the hard mask layer to divide the hard mask layer into two or more distinct portions. When the stacked structure is subsequently etched to form high aspect ratio features within the hard mask layer, such as contact holes or vias that extend through the hard mask layer, the ESL(s) included within the hard mask layer improve etch rate and critical dimension (CD) uniformity of the features etched within the hard mask layer.

Abstract: Methods are provided herein for patterning extreme ultraviolet (EUV) (or lower wavelength) photoresists, such metal-oxide photoresists. A patterning layer comprising a metal-oxide photoresist is formed on one or more underlying layers provided on a substrate, and portions of the patterning layer not covered by a mask overlying the patterning layer are exposed to EUV or lower wavelengths light. A cyclic dry process is subsequently performed to remove portions of the patterning layer exposed to the EUV or lower wavelength light (i.e., the exposed portions) and develop the metal-oxide photoresist pattern. The cyclic dry process generally includes a plurality of deposition and etch steps, wherein the deposition step selectively deposits a protective layer onto unexposed portions of the patterning layer by exposing the substrate to a first plasma, and the etch step selectively etches the exposed portions of the patterning layer by exposing the substrate to a second plasma.

Abstract: A method of fabricating an amorphous carbon layer (ACL) mask includes forming an ACL on an underlying layer. The ACL includes a soft ACL portion that has a first hardness and a hard ACL portion that has a second hardness. The soft ACL portion underlies the hard ACL portion. The second hardness is greater than the first hardness. The method further includes forming a patterned layer over the ACL and forming an ACL mask by etching through both the soft ACL portion and the hard ACL portion of the ACL to expose the underlying layer using the patterned layer as an etch mask. Forming the ACL may include depositing one or both of the soft ACL portion and the hard ACL portion. Processing conditions may also be varied while forming the ACL to create a hardness gradient that transitions from softer to harder.

Abstract: The disclosed optical assembly may include a photoalignment layer that includes photoalignment material (PAM) anchored to a substrate according to a specified surface anchoring. The optical assembly may also include a functional or transforming layer that is applied to the photoalignment layer. The transforming layer may modify the surface anchoring of the photoalignment layer to align with a polarization volume hologram layer. The polarization volume hologram layer of the optical assembly may be disposed on the transforming layer. Various other methods of manufacturing, systems, and apparatuses are also disclosed.

Abstract: A micro-light emitting diode device includes a backplane including drive circuits formed thereon, an array of micro-LEDs bonded to the backplane and electrically coupled to the drive circuits, an array of polarization diffraction micro-lenses bonded to the array of micro-LEDs and including a planar surface, and a cover glass bonded to the planar surface of the array of polarization diffraction micro-lenses. A center of each polarization diffraction micro-lens of the array of polarization diffraction micro-lenses aligns with a center of a respective micro-LED of the array of micro-LEDs.

Abstract: A memory system includes multiple groups of primary memory cells residing in a first die or a stack of first dies, multiple groups of cache memory cells residing in a second die, an interposer, and control circuits residing in a third die. Each group of the cache memory cells is associated with a corresponding group of the primary memory cells. The first die or the stack of first dies is coupled to a top surface of the second die through a first group of bumps. A bottom surface of the second die is coupled to a top surface of the interposer through a second group of bumps. The control circuits are associated with the primary memory cells and the cache memory cells. The third die is positioned aside the second die and coupled to the top surface of the interposer through a third group of pumps.

Abstract: A semiconductor device structure includes a dielectric layer formed on a silicon substrate, an amorphous carbon layer (ACL) formed on the dielectric layer, and a charge dissipation layer formed between the ACL and the dielectric layer. The charge dissipation layer is formed from a material having a resistivity lower than the resistivity of the ACL Methodologies to fabricate the semiconductor device structure are also disclosed and include forming the dielectric layer on the silicon substrate, forming the charge dissipation layer on the dielectric layer, and forming the ACL on the charge dissipation layer. Alternative semiconductor device structures and fabrication methodologies are also disclosed.

Abstract: A method of processing a substrate that includes: performing a cyclic plasma etch process including a plurality of cycles, each of the plurality of cycles including: etching a patterning layer including a polycrystalline semiconductor material to form or extend a recess by exposing the substrate to a first plasma, the substrate including an oxide layer, the patterning layer formed over the oxide layer, exposing the substrate to a second plasma, the second plasma including dihydrogen, and extending the recess by exposing the substrate to a third plasma, the second plasma being different from the first plasma and the third plasma.

Abstract: A voltage regulator includes a control circuit configured to output a plurality of enable signals, and a power stage including a plurality of phase circuits. Each phase circuit of the plurality of phase circuits includes a node, an inductor coupled between the node and an output node of the voltage regulator, a plurality of p-type transistors coupled between the node and a power supply node of the voltage regulator, and a plurality of n-type transistors coupled between the node and a reference node of the voltage regulator. Each phase circuit of the plurality of phase circuits is configured to, responsive to the plurality of enable signals, selectively couple the node to the power supply node through a first subset or all of the plurality of p-type transistors, and selectively couple the node to the reference node through a second subset or all of the plurality of n-type transistors.

Abstract: A device is provided. The device includes a polarization hologram polymer layer having a wavy surface, an optic axis of the polarization hologram polymer layer being configured with a spatially varying orientation in a first predetermined in-plane direction. The device also includes a compensation layer disposed at the wavy surface of the polarization hologram polymer layer and configured to compensate for the wavy surface in shape.

Abstract: A light emitting display apparatus and a driving method thereof. The light emitting display apparatus includes a display panel configured to display an image, a timing controller including an on bias stress (OBS) voltage calculator configured to calculate an optimal OBS voltage value on the basis of a refresh rate of the display panel and a data signal which is to be supplied to the display panel, and a power supply configured to generate an OBS voltage which is to be supplied to the display panel, on the basis of the optimal OBS voltage value.

Abstract: Disclosed is a transistor of a device that has double side contacts in which at least a drain contact is on the opposite side of the gate. In this way, gate resistance can be reduced without increasing parasitic capacitances between gate and drain.

Abstract: A display device with a transparent illuminator and an liquid crystal (LC) display panel is disclosed. The transparent illuminator includes a light source and a transparent lightguide, which may be based on a slab of transparent material with zigzag light propagation of the illuminating light in the slab and/or a transparent photonic integrated circuit with singlemode ridge waveguides for spreading the illuminating light in a plane parallel to the plane of LC display panel. The lightguide includes a plurality of grating out-couplers whose position is coordinated with positions of LC pixels for higher throughput. A reflective offset-to-angle optical element may be provided to form an image in angular domain through the LC panel and through the transparent illuminator, resulting in an overall compact and efficient display configuration.

Abstract: An optical element includes a first birefringent medium layer with orientations of directors of first optically anisotropic molecules spatially varying with a first in-plane pitch and a first vertical pitch. The optical element also includes a second birefringent medium layer with orientations of directors of second optically anisotropic molecules spatially varying with a second in-plane pitch and a second vertical pitch. The second birefringent medium layer is optically coupled with the first birefringent medium layer and configured to reduce a diffraction of a light by the first birefringent medium layer. The first in-plane pitch is substantially the same as the second in-plane pitch, and the second vertical pitch is smaller than the first vertical pitch.