Patents by Inventor Yun Han

Yun Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230262130
    Abstract: An Internet of Things (IoT) system includes a plurality of terminal devices, a cloud device and a human machine interface (HMI) device. The cloud device is communicatively connected to the terminal devices. The human machine interface (HMI) device is communicatively connected to the terminal devices via a plurality of first communication channels, and communicatively connected to the cloud device via a first dedicated communication channel. The HMI device determines a subscription sequence according to priority information of a plurality of control commands, and schedules and dynamically subscribes to the first communication channels according to the subscription sequence. The HMI device respectively determines whether the terminal devices are adjacent to the HMI device, and transmits switch transmission mode request messages corresponding to the terminal devices adjacent to the HMI device to the cloud device via the first dedicated communication channel.
    Type: Application
    Filed: April 25, 2023
    Publication date: August 17, 2023
    Applicant: Merry Electronics(Shenzhen) Co., Ltd.
    Inventors: Yun Han Yang, Hsin Jia Huang, Yi Lin Hsieh
  • Patent number: 11727177
    Abstract: A method executed at least partially by a processor includes creating a plurality of groups of paths from a plurality of paths in an integrated circuit (IC) layout diagram. Each group among the plurality of groups has a unique dominant feature among a plurality of features of the plurality of paths. The dominant feature of a group among the plurality of groups is slack. The method further includes testing at least one path in a group among the plurality of groups. The method also includes, in response to the testing indicating that the at least one path fails, modifying at least one of the IC layout diagram, at least a portion of at least one library having cells included in the IC layout diagram, or a manufacturing process for manufacturing an IC corresponding to the IC layout diagram.
    Type: Grant
    Filed: June 9, 2022
    Date of Patent: August 15, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY, LIMITED
    Inventors: Ankita Patidar, Sandeep Kumar Goel, Yun-Han Lee
  • Patent number: 11715668
    Abstract: The present disclosure relates to a semiconductor module. The semiconductor module includes an excitable element located on a first side of a substrate. A first ground structure is disposed between the first side of the substrate and the excitable element. The first ground structure includes a conductive via extending through the substrate and an interconnect disposed over a topmost surface of the conductive via facing away from the substrate. A second ground structure is located on a second side of the substrate, opposing the first side, and electrically coupled to the first ground structure.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: August 1, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bo-Jr Huang, William Wu Shen, Chin-Her Chien, Chin-Chou Liu, Yun-Han Lee
  • Publication number: 20230239129
    Abstract: An integrated circuit includes first through fourth devices positioned over one or more substrates, a first radio frequency interconnect (RFI) including a first transmitter included in the first device, a first receiver included in the second device, and a first guided transmission medium coupled to each of the first transmitter and the first receiver, a second RFI including a second transmitter included in the first device, a second receiver included in the third device, and a second guided transmission medium coupled to each of the second transmitter and the second receiver, and a third RFI including a third transmitter included in the first device, a third receiver included in the fourth device, and the second guided transmission medium coupled to each of the third transmitter and the third receiver.
    Type: Application
    Filed: March 27, 2023
    Publication date: July 27, 2023
    Inventors: Huan-Neng CHEN, William Wu SHEN, Chewn-Pu JOU, Feng Wei KUO, Lan-Chou CHO, Tze-Chiang HUANG, Jack LIU, Yun-Han LEE
  • Patent number: 11699010
    Abstract: A method of manufacturing a semiconductor device includes reducing errors in a migration of a first netlist to a second netlist, the first netlist corresponding to a first semiconductor process technology (SPT), the second first netlist corresponding to a second SPT, the first and second netlists each representing a same circuit design, the reducing errors including: inspecting a timing constraint list corresponding to the second netlist for addition candidates; generating a first version of the second netlist having a first number of comparison points relative to a logic equivalence check (LEC) context, the first number of comparison points being based on the addition candidates; performing a LEC between the first netlist and the first version of the second netlist, thereby identifying migration errors; and revising the second netlist to reduce the migration errors, thereby resulting in a second version of the second netlist.
    Type: Grant
    Filed: July 1, 2021
    Date of Patent: July 11, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY, LIMITED
    Inventors: Sandeep Kumar Goel, Ankita Patidar, Yun-Han Lee
  • Patent number: 11698702
    Abstract: A touch sensing unit, includes a plurality of first sensing electrodes and a plurality of second sensing electrodes intersecting with and insulated from the plurality of first sensing electrodes. The plurality of first sensing electrodes includes a plurality of first sensor portions and a plurality of first connection portions connecting each of the plurality of first sensor portions with one another. The plurality of second sensing electrodes includes a plurality of second sensor portions, a plurality of stem sensors extended from the plurality of second sensor portions, and a plurality of second connection portions connecting each of the plurality of sensor portions with one another. Each of the plurality of first sensor portions includes a plurality of depressions indented inwardly. Each of the plurality of stem sensors is disposed such that it is at least partially surrounded by a respective depression of the plurality of depressions.
    Type: Grant
    Filed: March 15, 2022
    Date of Patent: July 11, 2023
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Gyeong Nam Bang, Chang Ho Lee, Hye Yun Han, Young Bae Jung
  • Patent number: 11687454
    Abstract: A memory circuit includes a stack of first dies including multiple sets of memory cells of a first type, a second die including multiple sets of memory cells of a second type, a third die, and an interposer carrying the first, second, and third dies. The second die includes a first set of input/output (I/O) terminals on a top surface of the second die and a second set of I/O terminals on a bottom surface of the second die. The stack of first dies is coupled to the second die through the first set of I/O terminals. The interposer is coupled to the second die through the second set of I/O terminals. The third die is positioned aside the second die and in communication with the second die through the interposer.
    Type: Grant
    Filed: January 4, 2022
    Date of Patent: June 27, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Hsin Sean Lee, William Wu Shen, Yun-Han Lee
  • Patent number: 11687135
    Abstract: In one embodiment, a processor includes a plurality of domains each to operate at an independently controllable voltage and frequency, a plurality of linear regulators each to receive a first voltage from an off-chip source and controllable to provide a regulated voltage to at least one of the plurality of domains, and a plurality of selectors each coupled to one of the domains, where each selector is configured to provide a regulated voltage from one of the linear regulators or a bypass voltage to a corresponding domain. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 20, 2021
    Date of Patent: June 27, 2023
    Assignee: Tahoe Research, Ltd.
    Inventors: Sanjeev S. Jahagirdar, Satish K. Damaraju, Yun-Han Chen, Ryan D. Wells, Inder M. Sodhi, Vishram Sarurkar, Ken Drottar, Ashish V. Choubal, Rabiul Islam
  • Publication number: 20230196998
    Abstract: A light emitting display apparatus and a driving method thereof. The light emitting display apparatus includes a display panel configured to display an image, a timing controller including an on bias stress (OBS) voltage calculator configured to calculate an optimal OBS voltage value on the basis of a refresh rate of the display panel and a data signal which is to be supplied to the display panel, and a power supply configured to generate an OBS voltage which is to be supplied to the display panel, on the basis of the optimal OBS voltage value.
    Type: Application
    Filed: June 30, 2022
    Publication date: June 22, 2023
    Inventor: Sang Yun Han
  • Publication number: 20230185236
    Abstract: A system includes a light outputting element configured to output a first beam propagating toward a beam interference zone from a first side of the beam interference zone. The system also includes a wavefront shaping assembly disposed at a second side of the beam interference zone and including a polarization hologram, the wavefront shaping assembly being configured to reflect the first beam as a second beam propagating toward the beam interference zone from the second side. The first beam and the second beam are linearly polarized beams, and are configured to interfere with one another within the beam interference zone to generate an interference pattern that is recordable in a recording medium layer disposed in the beam interference zone.
    Type: Application
    Filed: September 28, 2022
    Publication date: June 15, 2023
    Inventors: Yun-Han LEE, Changwon JANG, Hyunmin SONG, Chulwoo OH, Matthieu Charles Raoul LEIBOVICI
  • Patent number: 11675188
    Abstract: A system is provided. The system includes a light source configured to emit an infrared light to illuminate an eye of a user. The system includes a grating disposed facing the eye and including a birefringent material film configured with a uniform birefringence lower than or equal to 0.1. The grating is configured to diffract the infrared light reflected from the eye, and transmit a visible light from a real world environment toward the eye, with a diffraction efficiency less than a predetermined threshold. The system includes an optical sensor configured to receive the diffracted infrared light and generate an image of the eye based on the diffracted infrared light.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: June 13, 2023
    Assignee: META PLATFORMS TECHNOLOGIES, LLC
    Inventors: Yun-Han Lee, Lu Lu, Mengfei Wang, Fenglin Peng, Junren Wang
  • Patent number: 11671500
    Abstract: An Internet of Things (IoT) system is provided. The IoT system includes a plurality of terminal devices, a cloud device, and a human machine interface device. The cloud device is communicatively connected to the terminal devices. The human-machine interface device is communicatively connected to the cloud device via a plurality of first communication channels, and is used for determining a subscription sequence according to a piece of priority information of a plurality of control commands. The human-machine interface device schedules and dynamically subscribes to the first communication channels according to the subscription sequence, so as to transmit the control commands to the cloud device through different first communication channels according to the subscription sequence, so that the cloud device transmits the control commands to the corresponding terminal devices.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: June 6, 2023
    Assignee: Merry Electronics(Shenzhen) Co., Ltd.
    Inventors: Yun Han Yang, Yi Lin Hsieh
  • Publication number: 20230170281
    Abstract: An integrated circuit (IC) package includes a logic die, a substrate, a memory die positioned between the logic die and the substrate, and a power distribution structure configured to electrically couple the logic die to the substrate. The power distribution structure includes a plurality of conductive segments positioned between the logic die and the memory die, a plurality of bump structures positioned between the memory die and the substrate, and a plurality of through-silicon vias (TSVs) electrically coupled to the plurality of conductive segments and the plurality of bump structures, and a TSV of the plurality of TSVs extends through, and is electrically isolated from, a memory macro of the memory die.
    Type: Application
    Filed: January 12, 2023
    Publication date: June 1, 2023
    Inventors: Hidehiro FUJIWARA, Tze-Chiang HUANG, Hong-Chen CHENG, Yen-Huei CHEN, Hung-Jen LIAO, Jonathan Tsung-Yung CHANG, Yun-Han LEE, Lee-Chung LU
  • Publication number: 20230159965
    Abstract: A method for increasing the oil yield in an ethanol production process comprising: adding a liquid enzyme formulation having at least one enzyme, a buffering agent, a stabilizer, and a preservative wherein the pH of the enzyme formulation is about pH 6.0-8.0 to a beer, a distillation, a whole stillage, a centrifugation, a thin stillage, an evaporator, a syrup, or an oil recovery unit.
    Type: Application
    Filed: June 14, 2018
    Publication date: May 25, 2023
    Inventors: Brian HOSKINS, Anthony V. NEWTON, Yun HAN, Joseph P. Borst
  • Publication number: 20230153508
    Abstract: A device is disclosed. The cell block includes a pin disposed at a Nth metal layer in a cell layout. The first metal interconnect is disposed at a (N+1)th metal layer above the Nth metal layer and stacked over the pin, and electrically coupled to the pin. The second interconnects are disposed at a (N+2)th metal layer and stacked over the first metal interconnect, and parallel to each other. The second metal interconnects are electrically coupled to the first metal interconnect, and forming an equivalent tapping point of the pin of the cell block. The equivalent tapping point and the pin are vertically overlapped with each other, and fabrication of the device is initiated after a DRC or a SEM simulation test is passed. A first width of at least one first metal interconnect is different from a second width of one of the plurality of second metal interconnects.
    Type: Application
    Filed: January 19, 2023
    Publication date: May 18, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Lin CHUANG, Huang-Yu CHEN, Yun-Han LEE
  • Patent number: 11651967
    Abstract: Improved process flows and methods are provided herein for forming a passivation layer on sidewall surfaces of openings formed in an amorphous carbon layer (ACL) to avoid bowing during an ACL etch process. More specifically, improved process flows and methods are provided to form a silicon-containing passivation layer on sidewall surfaces of the openings created within the ACL without utilizing atomic layer deposition (ALD) techniques or converting the silicon-containing passivation layer to an oxide or a nitride. As such, the improved process flows and methods disclosed herein may be used to protect the sidewall surfaces of the ACL and prevent bowing during the ACL etch process, while also reducing processing time and improving throughput.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: May 16, 2023
    Assignee: Tokyo Electron Limited
    Inventors: Shihsheng Chang, David O'Meara, Andrew Metz, Yun Han
  • Patent number: 11650429
    Abstract: A polarization conversion device includes a geometric phase grating and an angular selective waveplate. The geometric phase grating includes a first liquid crystal layer and is configured to diffract a unpolarized or partially polarized incident light beam into a first light beam and a second light beam (e.g., in two different diffraction orders). The first light beam is characterized by a first polarization state and propagates in a first direction. The second light beam is characterized by a second polarization state and propagates in a second direction. The angular selective waveplate includes a second liquid crystal layer, and functions as a zero or full-wave plate for the first light beam incident in the first direction and a half-wave plate for the second light beam incident in the second direction.
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: May 16, 2023
    Assignee: META PLATFORMS TECHNOLOGIES, LLC
    Inventors: Junren Wang, Mengfei Wang, Yun-Han Lee, Yuge Huang, Lu Lu, Barry David Silverstein
  • Publication number: 20230144920
    Abstract: A device is provided. The device includes a polarization hologram polymer layer having a wavy surface, an optic axis of the polarization hologram polymer layer being configured with a spatially varying orientation in a first predetermined in-plane direction. The device also includes a compensation layer disposed at the wavy surface of the polarization hologram polymer layer and configured to compensate for the wavy surface in shape.
    Type: Application
    Filed: September 13, 2022
    Publication date: May 11, 2023
    Inventors: Junren WANG, Yuge HUANG, Yun-Han LEE, Lu LU
  • Patent number: 11635669
    Abstract: A device includes a first substrate and a second substrate. The device also includes a birefringent medium layer disposed between the first substrate and the second substrate. Orientations of directors of optically anisotropic molecules included in the birefringent medium layer varying periodically with an in-plane pitch tunable by an external field to adjust a diffraction angle of a light beam diffracted by the birefringent medium layer.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: April 25, 2023
    Assignee: META PLATFORMS TECHNOLOGIES, LLC
    Inventors: Lu Lu, Hao Yu, Mengfei Wang, Junren Wang, Yun-Han Lee, Nicholas John Diorio, Barry David Silverstein
  • Patent number: 11635624
    Abstract: A device includes a light guide and at least one in-coupling element configured to couple an image light into the light guide. The device also includes a first out-coupling element configured to couple a first portion of the image light out of the light guide as a plurality of first output lights. The device further includes a second out-coupling element spaced apart from the first out-coupling element by a distance and configured to couple a second portion the image light out of the light guide as a plurality of second output lights. The second output lights are substantially non-overlapping with the first output lights.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: April 25, 2023
    Assignee: META PLATFORMS TECHNOLOGIES, LLC
    Inventors: Babak Amirsolaimani, Scott Charles McEldowney, Yun-Han Lee, Lu Lu