Abstract: An electronic device comprises a controller. The controller is configured to provide a first signal to a display of the electronic device to turn off the display. The controller is also configured to provide a second signal to the display to alter a gate source voltage of a drive transistor coupled to a light emitting diode (LED) of a pixel of the display while the display is turned off.

Abstract: A semiconductor structure includes a fin protruding from a substrate, a first and a second metal gate stacks disposed over the fin, and a dielectric feature defining a sidewall of each of the first and the second metal gate stacks. Furthermore, the dielectric feature includes a two-layer structure, where sidewalls of the first layer are defined by the second layer, and where the first and the second layers have different compositions.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a power rail; a bottom semiconductor layer formed over the dielectric layer; a backside spacer formed along a sidewall of the bottom semiconductor layer; a conductive feature contacting a sidewall of the dielectric layer and a sidewall of the backside spacer; channel semiconductor layers over the bottom semiconductor layer, wherein the channel semiconductor layers are stacked up and separated from each other; a metal gate structure wrapping each of the channel semiconductor layers; and an epitaxial source/drain (S/D) feature contacting a sidewall of each of the channel semiconductor layers, wherein the epitaxial S/D feature contacts the conductive feature, and the conductive feature contacts the power rail.

Abstract: An electrical system includes a rechargeable energy storage system (RESS) and a controller. The RESS includes first and second battery packs connected to a voltage bus, each pack having a respective plurality of battery cells and a corresponding cell balancing circuit. The RESS further includes switches that selectively connect or disconnect the packs to or from each other to achieve series and parallel modes. The controller executes a method by detecting a requested series to parallel mode transition. Responsive to a threshold imbalance being present in a state of charge or pack voltage of the packs relative to each other, the controller balances the state of charge/voltage using open/closed state control of the cell balancing circuits, and possibly a switching block having PWM-controlled switches and a circuit element. The controller may execute the requested mode transition upon balancing.

Abstract: A method for semiconductor fabrication includes providing a device structure having an isolation structure, a fin adjacent the isolation structure, gate structures over the fin and the isolation structure, one or more dielectric layers over the isolation structure and the fin and between the gate structures, a first contact hole over the fin, and a second contact hole over the isolation structure. The method further includes depositing a protection layer and treating it with a plasma so that the protection layer in the first contact hole and the protection layer in the second contact hole have different etch selectivity in an etching process; and etching the protection layer to etch through the protection layer on the bottom surface of the first contact hole without etching through the protection layer on the bottom surface of the second contact hole.

Abstract: A display pixel is provided that is operable to support hybrid compensation scheme having both in-pixel threshold voltage canceling and external threshold voltage compensation. The display may include multiple p-type silicon transistors with at least one n-type semiconducting-oxide transistor and one storage capacitor. An on-bias stress phase may be performed prior to a threshold voltage sampling and data programming phase to mitigate hysteresis and improve first frame response. In low refresh rate displays, a first additional on-bias stress operation can be performed separate from the threshold voltage sampling and data programming phase during a refresh frame and a second additional on-bias stress operation can be performed during a vertical blanking frame. The display pixel may be configured to receive an initialization voltage and an anode reset voltage, either of which can be dynamically tuned to match the stress of the first and second additional on-bias stress operations to minimize flicker.

Abstract: A circuit board arrangement assembled by at least a first and a second circuit boards, each circuit board comprising: a portion of a circuit; and a first and a second electrical terminals to be electrically connected to a respective first and a second electrical terminals of the other circuit board of the first and the second circuit boards, so as to couple the portions of the circuit of the first and the second circuit boards, wherein the first and second electrical terminals on the circuit board are coupled with each other via the portion of the circuit on the other circuit board of the first and the second circuit boards, at least one board further comprising: a voltage suppression element (TSS1, TSS2) in the board connected across the first and second electrical terminals of the board, said voltage suppression element (TSS1, TSS2) is adapted to become conductive when a voltage thereacross reaches a threshold; characterized in that the portion of the circuit comprising at least one LED, and said LED (LED1)

Abstract: A semiconductor device includes a gate structure disposed over a substrate, and a first dielectric layer disposed over the substrate, including and over the gate structure. A first metal feature is disposed in the first dielectric layer, including an upper portion having a first width and a lower portion having a second width that is different than the first width. A dielectric spacer is disposed along the lower portion of the first metal feature, wherein the upper portion of the first metal feature is disposed over the dielectric spacer. A second dielectric layer is disposed over the first dielectric layer, including over the first metal feature and a second metal feature extends through the second dielectric layer to physically contact with the first metal feature. A third metal feature extends through the second dielectric layer and the first dielectric layer to physically contact the gate structure.

Abstract: A device includes a gate stack; a gate spacer on a sidewall of the gate stack; a source/drain region adjacent the gate stack; a silicide; and a source/drain contact electrically connected to the source/drain region through the silicide. The silicide includes a conformal first portion in the source/drain region, the conformal first portion comprising a metal and silicon; and a conformal second portion over the conformal first portion, the conformal second portion further disposed on a sidewall of the gate spacer, the conformal second portion comprising the metal, silicon, and nitrogen.

Abstract: A distributed battery power system having a battery pack and a battery controller. The battery pack has: a plurality of cells configured to generate a plurality of cell voltages; a voltage current temperature module electrically connected to the plurality of cells; and a plurality of isolation switch sets electrically connected between the plurality of cells. The battery controller is in communication with the voltage current temperature module, and operable to: send a status request to the voltage current temperature module; receive the plurality of cell voltages from the voltage current temperature module in response to the status request; determine if the plurality of cells includes one or more problem cells in response to the plurality of cell voltages; and perform an action in response to determining that the one or more problem cells are present to prevent damage to the one or more problem cells.

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, a semiconductor structure includes a first plurality of channel members over a backside dielectric layer, a second plurality of channel members over the backside dielectric layer, a silicide feature disposed in the backside dielectric layer, and a source/drain feature disposed over the silicide feature and extending between the first plurality of channel members and the second plurality of channel members. The silicide feature extends through an entire depth of the backside dielectric layer.

Abstract: A displaying base plate includes an opening region, an adjacent region surrounding the opening region, and a displaying region surrounding the adjacent region, and the displaying base plate located within the adjacent region includes: a substrate base plate; a flat layer and a passivation layer that are provided on one side of the substrate base plate, wherein the passivation layer is provided on one side of the flat layer that is further away from the substrate base plate, a surface of the one side of the flat layer that is further away from the substrate base plate includes at least an inclined plane adjacent to one side of the opening region, and the flat layer includes a first protrusion provided on the inclined plane; and a first isolating groove that at least partially overlaps with the first protrusion and extends throughout the passivation layer and extends into the first protrusion.

Abstract: Techniques for business data protection for running tasks in a computer system are described herein. An aspect includes receiving a request. Another aspect includes processing a task corresponding to the request. Another aspect includes receiving a debugging request from a user corresponding to the task, wherein the debugging request is received during the processing of the task. Another aspect includes, based on receiving the debugging request, determining whether the user is authorized to access business data corresponding to the task. Another aspect includes, based on determining that the user is not authorized to access the business data corresponding to the task, redacting the business data from debugging data corresponding to the debugging request. Another aspect includes providing the redacted debugging data to the user.

Abstract: Micro-alloyed aluminium alloys containing complex sub-micro/or nano-sized strengthening phases are provided for use for example in the automotive industry. Existing commercial alloys are treated by adding at least one of the elements from Ni, Ag, Nb, Mo, Ce, La, Y and Sc at a level of more than 0.1 wt. % but less than 0.5 wt. % on top of the existing commercial alloy containing Si, Cu, Mg, Mn, Zn, and at least one type of sub-micron sized or even nano-sized TiB2, TiC and AI2O3 solid particles at a level of more than 0.05 wt. % but less than 0.5 wt. % in the solidified castings.

Abstract: A system for use with a direct current fast-charging (DCFC) station includes a controller and battery system. The battery system includes first and second battery packs, and first, second, and third switches. The switches have ON/OFF conductive states commanded by the controller to connect the battery packs in a parallel-connected (P-connected) or series-connected (S-connected) configuration. An electric powertrain with one or more electric machines is powered via the battery system. First and second charge ports of the system are connectable to the station via a corresponding charging cable. The first charge port receives a low or high charging voltage from the station. The second charge port receives a low charging voltage. When the station can supply the high charging voltage to the first charge port, the controller establishes the S-connected configuration via the switches, and thereafter charges the battery system solely via the first charge port.

Abstract: A method of manufacturing a display substrate which includes a central display area and an arc-shaped stretch area located at a corner of the central display area, wherein the method includes: preparing a substrate to be etched, which includes a flexible substrate, a stack structure disposed on the flexible substrate, and a last-dry-etched metal layer disposed on a side of the stack structure away from the flexible substrate, the stack structure including an active layer, at least one conductive layer, and a plurality of insulating layers, wherein the last-dry-etched metal layer is a last metal layer that is formed through dry etching; and forming a stretch groove by patterning the substrate to be etched, wherein the stretch groove is disposed in the stretch area and passes through the stack structure and a part of the flexible substrate. A display substrate, a display panel and a display device are further provided.

Abstract: A method is disclosed for determining the state of health of an electric battery that includes a plurality of battery cells. The method includes the steps of measuring the cell voltage of each individual cell of the plurality of battery cells, and analyzing each measured battery cell voltage to determine the state of health of the corresponding battery cell.

Abstract: Methods to form vertically conducting and laterally conducting low-cost resistor structures utilizing dual-resistivity conductive materials are provided. The dual-resistivity conductive materials are deposited in openings in a dielectric layer using a single deposition process step. A high-resistivity ?-phase of tungsten is stabilized by pre-treating portions of the dielectric material with impurities. The portions of the dielectric material in which impurities are incorporated encompass regions laterally adjacent to where high-resistivity ?-W is desired. During a subsequent tungsten deposition step the impurities may out-diffuse and get incorporated in the tungsten, thereby stabilizing the metal in the high-resistivity ?-W phase. The ?-W converts to a low-resistivity ?-phase of tungsten in the regions not pre-treated with impurities.

Abstract: A semiconductor structure includes a source/drain (S/D) feature disposed in a semiconductor layer, a metal gate stack (MG) disposed in a first interlayer dielectric (ILD) layer and adjacent to the S/D feature, a second ILD layer disposed over the MG, and an S/D contact disposed over the S/D feature. The semiconductor structure further includes an air gap disposed between a sidewall of a bottom portion of the S/D contact and the first ILD layer, where a sidewall of a top portion of the S/D contact is in direct contact with the second ILD layer.

Abstract: A method and structure for forming a via-first metal gate contact includes depositing a first dielectric layer over a substrate having a gate structure with a metal gate layer. An opening is formed within the first dielectric layer to expose a portion of the substrate, and a first metal layer is deposited within the opening. A second dielectric layer is deposited over the first dielectric layer and over the first metal layer. The first and second dielectric layers are etched to form a gate via opening. The gate via opening exposes the metal gate layer. A portion of the second dielectric layer is removed to form a contact opening that exposes the first metal layer. The gate via and contact openings merge to form a composite opening. A second metal layer is deposited within the composite opening, thus connecting the metal gate layer to the first metal layer.