Abstract: A lamp has a safety circuit connected to first and second electrical connection terminals. A test is used to detect if the first and second electrical connection terminals are both connected to external power without an interfering impedance such a human body, and only then enable operation of the lamp. A time for the test is different from a time when another lamp in the system applies a test.

Abstract: In an approach for debugging and simulating application runtime execution, a processor loads source code and logs into a debug tool. A processor generates log debug information including a log map, a log variable cross reference table, and a method call stack tree. A processor determines a plurality of log blocks based on log context in the logs and the method call stack tree. A processor maps the source code to the logs for each log block. A processor suggests a starting point and a breakpoint based on the log variable cross reference table and the log blocks. A processor compares a source code variable value to a log variable value and a source code execution path to a log execution path based on the mapping set between the source code and the logs. A processor simulates the source code variable value with the log variable value.

Abstract: An AFI-CHA hybrid crystal molecular sieve and an NH3-SCR catalyst using the AFI-CHA hybrid crystal molecular sieve as a carrier, and preparation methods thereof are disclosed. The AFI-CHA hybrid crystal molecular sieve includes an AFI-type SAPO-5 molecular sieve and a CHA-type SAPO-34 molecular sieve, with hybrid crystal grains of AFI and CHA. The hybrid crystal molecular sieve is synthesized by a hydrothermal synthesis method and can be obtained by changing the structure directing agent, the heating rate and the calcinating temperature in the preparation process. Further, copper is loaded on the basis of the hybrid crystal molecular sieve to prepare copper-based NH3-SCR catalyst and corresponding monolithic catalyst. The catalytic activity and hydrothermal stability of the catalyst are significantly improved by the hybrid crystal molecular sieve.

Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and a metal gate structure formed over the substrate. The semiconductor structure further includes a sealing layer comprising an inner sidewall and an outermost sidewall. In addition, the inner sidewall is in direct contact with the metal gate structure and the outermost sidewall is away from the metal gate structure. The semiconductor structure further includes a mask structure formed over the metal gate structure. In addition, the mask structure has a straight sidewall over the metal gate structure and a sloped sidewall extending from the inner sidewall of the sealing layer and passing over the outmost sidewall of the sealing layer.

Abstract: Semiconductor devices and methods of fabricating semiconductor devices are provided. The present disclosure provides a semiconductor device that includes a first fin structure and a second fin structure each extending from a substrate; a first gate segment over the first fin structure and a second gate segment over the second fin structure; a first isolation feature separating the first and second gate segments; a first source/drain (S/D) feature over the first fin structure and adjacent to the first gate segment; a second S/D feature over the second fin structure and adjacent to the second gate segment; and a second isolation feature also disposed in the trench. The first and second S/D features are separated by the second isolation feature, and a composition of the second isolation feature is different from a composition of the first isolation feature.

Abstract: This invention provides methods, processes, compounds and compositions for modulating the gene expression or secretion of adhesion proteins, angiopoietins or their receptors to cure diseases, for anti-angiogenesis and for treating parasites, wherein the adhesion proteins or receptors comprise fibronectin, integrins family, myosin, vitronectin, collagen, laminin, glycosylation cell surface proteins, polyglycans, cadherin, heparin, tenascin, CD 54, CAM, elastin and FAK; wherein the angiopoietins comprise angiopoietin 1, angiopoietin 2, angiopoietin 3, angiopoietin 4, angiopoietin 5, angiopoietin 6, angiopoietin 7, angiopoietin-like 1, angiopoietin-like 2, angiopoietin-like 3, angiopoietin-like 4, angiopoietin-like 5, angiopoietin-like 6, and angiopoietin-like 7; wherein the cancers comprise breast cancer, leukocyte cancer, liver cancer, ovarian cancer, bladder cancer, prostate cancer, skin cancer, bone cancer, brain cancer, leukemia cancer, lung cancer, colon cancer, CNS cancer, melanoma cancer, renal cancer, c

Abstract: A method according to the present disclosure includes receiving a workpiece that includes a gate structure, a first gate spacer feature, a second gate spacer feature, a gate-top dielectric feature over the gate structure, the first gate spacer feature and the second gate spacer feature, a first source/drain feature over a first source/drain region, a second source/drain feature over a second source/drain region, a first dielectric layer over the first source/drain feature, and a second dielectric layer over the second source/drain feature. The method further includes replacing a top portion of the first dielectric layer with a first hard mask layer, forming a second hard mask layer over the first hard mask layer while the second dielectric layer is exposed, etching the second dielectric layer to form a source/drain contact opening and to expose the second source/drain feature, and forming a source/drain contact over the second source/drain feature.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a power rail; a bottom semiconductor layer formed over the dielectric layer; a backside spacer formed along a sidewall of the bottom semiconductor layer; a conductive feature contacting a sidewall of the dielectric layer and a sidewall of the backside spacer; channel semiconductor layers over the bottom semiconductor layer, wherein the channel semiconductor layers are stacked up and separated from each other; a metal gate structure wrapping each of the channel semiconductor layers; and an epitaxial source/drain (S/D) feature contacting a sidewall of each of the channel semiconductor layers, wherein the epitaxial S/D feature contacts the conductive feature, and the conductive feature contacts the power rail.

Abstract: Provided herein are antibodies that bind to the alpha subunit of an IL-7 receptor (IL-7R?). Also provided are uses of these antibodies in therapeutic applications, such as treatment of inflammatory diseases. Further provided are cells that produce the antibodies, polynucleotides encoding the heavy and/or light chain regions of the antibodies, and vectors comprising the polynucleotides.

Abstract: A lighting apparatus includes a LED module, a light source plate, a heat sink, an antenna, a driver and a light housing. The light source plate is used for holding the LED module. The heat sink has a bottom plate and a lateral wall. The light source plate is placed on the bottom plate. The antenna is disposed on the lateral wall. The driver is used for generating a driving current to the LED module. The driver has a wireless circuit. The wireless circuit is electrically connected to the antenna for transmitting a wireless signal. The light housing is used for holding the heat sink so that the LED module emits light toward a light opening of the light housing.

Abstract: Methods to form vertically conducting and laterally conducting low-cost resistor structures utilizing dual-resistivity conductive materials are provided. The dual-resistivity conductive materials are deposited in openings in a dielectric layer using a single deposition process step. A high-resistivity ?-phase of tungsten is stabilized by pre-treating portions of the dielectric material with impurities. The portions of the dielectric material in which impurities are incorporated encompass regions laterally adjacent to where high-resistivity ?-W is desired. During a subsequent tungsten deposition step the impurities may out-diffuse and get incorporated in the tungsten, thereby stabilizing the metal in the high-resistivity ?-W phase. The ?-W converts to a low-resistivity ?-phase of tungsten in the regions not pre-treated with impurities.

Abstract: A semiconductor structure includes a source/drain (S/D) feature disposed in a semiconductor layer, a metal gate stack (MG) disposed in a first interlayer dielectric (ILD) layer and adjacent to the S/D feature, a second ILD layer disposed over the MG, and an S/D contact disposed over the S/D feature. The semiconductor structure further includes an air gap disposed between a sidewall of a bottom portion of the S/D contact and the first ILD layer, where a sidewall of a top portion of the S/D contact is in direct contact with the second ILD layer.

Abstract: Management system for a rechargeable energy storage device in an electric vehicle and corresponding method is disclosed. The rechargeable energy storage device has one or more battery packs each having a plurality of modules with one or more respective cells. A respective module management unit is embedded in each of the plurality of modules through respective microcircuits and configured to determine one or more local parameters. A supervisory controller is configured for two-way communication with the respective module management unit. The supervisory controller is configured to receive the local parameters, determine one or more global pack parameters based in part on the local parameters and transmit the global pack parameters back to the respective management unit. The supervisory controller is configured to control operation of the rechargeable energy storage device based in part on the global pack parameters and the local parameters.

Abstract: A system includes an electronic display panel that has a plurality of pixels configured to depict frames of image data. The electronic display also includes display driver circuitry configured to, for a first frame of image data representing first image content, modify a gate-to-source voltage of a transistor of a first pixel of the plurality of pixels to a content-dependent first gate-to-source voltage. Additionally, after modifying the gate-to-source voltage to the first gate-to-source voltage, the display driver circuitry is configured to program the first pixel by modifying the gate-to-source voltage to a gate-to-source programming voltage that differs from the first gate-to-source voltage and is based on image data associated with the pixel from the first frame of the image data. Furthermore, the display driver circuitry is configured to cause the plurality of pixels to emit light.

Abstract: A method and device for filling invalid regions of terrain elevation model data are provided by the present disclosure. The filling method includes obtaining an isolated invalid grid in first terrain elevation model data, the invalid grid being a grid without a valid elevation value; interpolating an elevation value of the isolated invalid grid by using elevation values of valid grids around the isolated invalid grid, to obtain data-interpolated first terrain elevation model data; obtaining invalid patches in the data-interpolated first terrain elevation model data, each of the invalid patches being a region consisting of at least two adjacent invalid grids; and interpolating elevation values of the invalid grids in the invalid patches by using a further terrain elevation model data other than the first terrain elevation model data, to fill the invalid regions of the first terrain elevation model data.

Abstract: A method of semiconductor fabrication includes providing a semiconductor structure having a substrate and first, second, third, and fourth fins above the substrate. The method further includes forming an n-type epitaxial source/drain (S/D) feature on the first and second fins, forming a p-type epitaxial S/D feature on the third and fourth fins, and performing a selective etch process on the semiconductor structure to remove upper portions of the n-type epitaxial S/D feature and the p-type epitaxial S/D feature such that more is removed from the n-type epitaxial S/D feature than the p-type epitaxial S/D feature.

Abstract: A method includes providing a structure that includes a substrate, a first gate structure and a second gate structure over the substrate, and a first source/drain (S/D) feature and a second S/D feature over the substrate. The first S/D feature is adjacent to the first gate structure, the second S/D feature is adjacent to the second gate structure, the first S/D feature is configured for an n-type transistor, and the second S/D feature is configured for a p-type transistor. The method further includes introducing a p-type dopant into both the first and the second S/D features. After the introducing of the p-type dopant, the method further includes performing an etching process to the first and the second S/D features, wherein the etching process etches the first S/D feature faster than it etches the second S/D feature.

Abstract: System and method of controlling power distribution from a charging source to an electric vehicle having a battery. The system includes a plurality of switches selectively connectable between the charging source, the battery and a thermal circuit. A controller is configured to control operation of the plurality of switches to provide multiple settings for the electric vehicle. The controller is configured to select from the multiple settings based on part on a trigger signal from a mobile application. The multiple settings include an external power mode, a charging mode, a discharging mode and a mixed charging and conditioning mode. The mixed charging and conditioning mode allows charging of the battery concurrently with thermal conditioning of at least one of the battery and a cabin of the vehicle. The mixed charging and conditioning mode enables a power split between a thermal conditioning power (PT) and a charging power (PC).

Abstract: Techniques for warm cloning of computing nodes are provided. A request to clone a first computing node is received. Upon determining that a first transaction of a plurality of transactions is ongoing, a first moment in time when data associated with the first transaction was coherent on the first computing node is identified. Tracking data related to the first transaction is collected, beginning at the first moment in time. Further, a first storage associated with the first computing node is copied to a second storage associated with a second computing node, where the first transaction continues during the copying. The tracking data related to the first transaction is then transmitted to the second computing node.

Abstract: An embodiment method includes: forming fins extending from a semiconductor substrate; depositing an inter-layer dielectric (ILD) layer on the fins; forming masking layers on the ILD layer; forming a cut mask on the masking layers, the cut mask including a first dielectric material, the cut mask having first openings exposing the masking layers, each of the first openings surrounded on all sides by the first dielectric material; forming a line mask on the cut mask and in the first openings, the line mask having slot openings, the slot openings exposing portions of the cut mask and portions of the masking layers, the slot openings being strips extending perpendicular to the fins; patterning the masking layers by etching the portions of the masking layers exposed by the first openings and the slot openings; and etching contact openings in the ILD layer using the patterned masking layers as an etching mask.