Abstract: Provided herein are antibodies that bind to the alpha subunit of an IL-7 receptor (IL-7R?). Also provided are uses of these antibodies in therapeutic applications, such as treatment of inflammatory diseases. Further provided are cells that produce the antibodies, polynucleotides encoding the heavy and/or light chain regions of the antibodies, and vectors comprising the polynucleotides.

Abstract: A lighting apparatus includes a LED module, a light source plate, a heat sink, an antenna, a driver and a light housing. The light source plate is used for holding the LED module. The heat sink has a bottom plate and a lateral wall. The light source plate is placed on the bottom plate. The antenna is disposed on the lateral wall. The driver is used for generating a driving current to the LED module. The driver has a wireless circuit. The wireless circuit is electrically connected to the antenna for transmitting a wireless signal. The light housing is used for holding the heat sink so that the LED module emits light toward a light opening of the light housing.

Abstract: A method and device for filling invalid regions of terrain elevation model data are provided by the present disclosure. The filling method includes obtaining an isolated invalid grid in first terrain elevation model data, the invalid grid being a grid without a valid elevation value; interpolating an elevation value of the isolated invalid grid by using elevation values of valid grids around the isolated invalid grid, to obtain data-interpolated first terrain elevation model data; obtaining invalid patches in the data-interpolated first terrain elevation model data, each of the invalid patches being a region consisting of at least two adjacent invalid grids; and interpolating elevation values of the invalid grids in the invalid patches by using a further terrain elevation model data other than the first terrain elevation model data, to fill the invalid regions of the first terrain elevation model data.

Abstract: A system includes an electronic display panel that has a plurality of pixels configured to depict frames of image data. The electronic display also includes display driver circuitry configured to, for a first frame of image data representing first image content, modify a gate-to-source voltage of a transistor of a first pixel of the plurality of pixels to a content-dependent first gate-to-source voltage. Additionally, after modifying the gate-to-source voltage to the first gate-to-source voltage, the display driver circuitry is configured to program the first pixel by modifying the gate-to-source voltage to a gate-to-source programming voltage that differs from the first gate-to-source voltage and is based on image data associated with the pixel from the first frame of the image data. Furthermore, the display driver circuitry is configured to cause the plurality of pixels to emit light.

Abstract: Management system for a rechargeable energy storage device in an electric vehicle and corresponding method is disclosed. The rechargeable energy storage device has one or more battery packs each having a plurality of modules with one or more respective cells. A respective module management unit is embedded in each of the plurality of modules through respective microcircuits and configured to determine one or more local parameters. A supervisory controller is configured for two-way communication with the respective module management unit. The supervisory controller is configured to receive the local parameters, determine one or more global pack parameters based in part on the local parameters and transmit the global pack parameters back to the respective management unit. The supervisory controller is configured to control operation of the rechargeable energy storage device based in part on the global pack parameters and the local parameters.

Abstract: A semiconductor structure includes a source/drain (S/D) feature disposed in a semiconductor layer, a metal gate stack (MG) disposed in a first interlayer dielectric (ILD) layer and adjacent to the S/D feature, a second ILD layer disposed over the MG, and an S/D contact disposed over the S/D feature. The semiconductor structure further includes an air gap disposed between a sidewall of a bottom portion of the S/D contact and the first ILD layer, where a sidewall of a top portion of the S/D contact is in direct contact with the second ILD layer.

Abstract: Methods to form vertically conducting and laterally conducting low-cost resistor structures utilizing dual-resistivity conductive materials are provided. The dual-resistivity conductive materials are deposited in openings in a dielectric layer using a single deposition process step. A high-resistivity ?-phase of tungsten is stabilized by pre-treating portions of the dielectric material with impurities. The portions of the dielectric material in which impurities are incorporated encompass regions laterally adjacent to where high-resistivity ?-W is desired. During a subsequent tungsten deposition step the impurities may out-diffuse and get incorporated in the tungsten, thereby stabilizing the metal in the high-resistivity ?-W phase. The ?-W converts to a low-resistivity ?-phase of tungsten in the regions not pre-treated with impurities.

Abstract: A method of semiconductor fabrication includes providing a semiconductor structure having a substrate and first, second, third, and fourth fins above the substrate. The method further includes forming an n-type epitaxial source/drain (S/D) feature on the first and second fins, forming a p-type epitaxial S/D feature on the third and fourth fins, and performing a selective etch process on the semiconductor structure to remove upper portions of the n-type epitaxial S/D feature and the p-type epitaxial S/D feature such that more is removed from the n-type epitaxial S/D feature than the p-type epitaxial S/D feature.

Abstract: A method includes providing a structure that includes a substrate, a first gate structure and a second gate structure over the substrate, and a first source/drain (S/D) feature and a second S/D feature over the substrate. The first S/D feature is adjacent to the first gate structure, the second S/D feature is adjacent to the second gate structure, the first S/D feature is configured for an n-type transistor, and the second S/D feature is configured for a p-type transistor. The method further includes introducing a p-type dopant into both the first and the second S/D features. After the introducing of the p-type dopant, the method further includes performing an etching process to the first and the second S/D features, wherein the etching process etches the first S/D feature faster than it etches the second S/D feature.

Abstract: System and method of controlling power distribution from a charging source to an electric vehicle having a battery. The system includes a plurality of switches selectively connectable between the charging source, the battery and a thermal circuit. A controller is configured to control operation of the plurality of switches to provide multiple settings for the electric vehicle. The controller is configured to select from the multiple settings based on part on a trigger signal from a mobile application. The multiple settings include an external power mode, a charging mode, a discharging mode and a mixed charging and conditioning mode. The mixed charging and conditioning mode allows charging of the battery concurrently with thermal conditioning of at least one of the battery and a cabin of the vehicle. The mixed charging and conditioning mode enables a power split between a thermal conditioning power (PT) and a charging power (PC).

Abstract: Techniques for warm cloning of computing nodes are provided. A request to clone a first computing node is received. Upon determining that a first transaction of a plurality of transactions is ongoing, a first moment in time when data associated with the first transaction was coherent on the first computing node is identified. Tracking data related to the first transaction is collected, beginning at the first moment in time. Further, a first storage associated with the first computing node is copied to a second storage associated with a second computing node, where the first transaction continues during the copying. The tracking data related to the first transaction is then transmitted to the second computing node.

Abstract: An embodiment method includes: forming fins extending from a semiconductor substrate; depositing an inter-layer dielectric (ILD) layer on the fins; forming masking layers on the ILD layer; forming a cut mask on the masking layers, the cut mask including a first dielectric material, the cut mask having first openings exposing the masking layers, each of the first openings surrounded on all sides by the first dielectric material; forming a line mask on the cut mask and in the first openings, the line mask having slot openings, the slot openings exposing portions of the cut mask and portions of the masking layers, the slot openings being strips extending perpendicular to the fins; patterning the masking layers by etching the portions of the masking layers exposed by the first openings and the slot openings; and etching contact openings in the ILD layer using the patterned masking layers as an etching mask.

Abstract: Various embodiments of the present disclosure provide a via-first process for connecting a contact to a gate electrode. In some embodiments, the contact is formed extending through a first interlayer dielectric (ILD) layer to a source/drain region bordering the gate electrode. An etch stop layer (ESL) is deposited covering the first ILD layer and the contact, and a second ILD layer is deposited covering the ESL. A first etch is performed into the first and second ILD layers and the etch stop layer to form a first opening exposing the gate electrode. A series of etches is performed into the second ILD layer and the etch stop layer to form a second opening overlying the contact and overlapping the first opening, such that a bottom of the second opening slants downward from the contact to the first opening. A gate-to-contact (GC) structure is formed filling the first and second openings.

Abstract: A device includes a gate stack; a gate spacer on a sidewall of the gate stack; a source/drain region adjacent the gate stack; a silicide; and a source/drain contact electrically connected to the source/drain region through the silicide. The silicide includes a conformal first portion in the source/drain region, the conformal first portion comprising a metal and silicon; and a conformal second portion over the conformal first portion, the conformal second portion further disposed on a sidewall of the gate spacer, the conformal second portion comprising the metal, silicon, and nitrogen.

Abstract: In an embodiment, a device includes: a semiconductor substrate; a first fin extending from the semiconductor substrate; a second fin extending from the semiconductor substrate; an epitaxial source/drain region including: a main layer in the first fin and the second fin, the main layer including a first semiconductor material, the main layer having a upper faceted surface and a lower faceted surface, the upper faceted surface and the lower faceted surface each being raised from respective surfaces of the first fin and the second fin; and a semiconductor contact etch stop layer (CESL) contacting the upper faceted surface and the lower faceted surface of the main layer, the semiconductor CESL including a second semiconductor material, the second semiconductor material being different from the first semiconductor material.

Abstract: Vertical interconnect structures and methods of forming are provided. The vertical interconnect structures may be formed by partially filling a first opening through one or more dielectric layers with layers of conductive materials. A second opening is formed in a dielectric layer such that a depth of the first opening after partially filling with the layers of conductive materials is close to a depth of the second opening. The remaining portion of the first opening and the second opening may then be simultaneously filled.

Abstract: Methods, systems, and devices, including computer programs encoded on computer storage media, for processing an electronic coupon link are provided. One of the methods includes: receiving, by a server, an electronic coupon link from a first user terminal; determining a first attribute of the electronic coupon link according to the electronic coupon link; determining, according to the first attribute, a storage pool corresponding to the first attribute from a plurality of storage pools; and storing the electronic coupon link in the storage pool corresponding to the first attribute, for a second user terminal to obtain the electronic coupon link in the storage pool. The storage pool may store one or more electronic coupon links.

Abstract: A method and structure for forming semiconductor device includes forming a contact via opening in a first dielectric layer, where the contact via opening exposes a first portion of a contact etch stop layer (CESL). The method further includes etching both the first portion of the CESL exposed by the contact via opening and adjacent lateral portions of the CESL to expose a source/drain contact and form an enlarged contact via opening having cavities disposed on either side of a bottom portion of the enlarged contact via opening. The method further includes forming a passivation layer on sidewall surfaces of the enlarged contact via opening including on sidewall surfaces of the cavities. The method further includes depositing a first metal layer within the enlarged contact via opening and within the cavities to provide a contact via in contact with the exposed source/drain contact.

Abstract: Presented are model predictive control (MPC) systems, methods, and devices for regulating operation of hybrid powertrains. A method of controlling a hybrid powertrain includes a controller determining path plan data, including a vehicle origin, destination, and predicted path. Based on this path plan data, the controller estimates vehicle velocities for multiple rolling road segments of the predicted path and, based on the estimated velocities, determines an estimated power request—transmission input torque and/or vehicle axle torque—for each road segment. The controller calculates a minimum cost function such that total fuel consumption to generate the engine power output is minimized. Minimizing the cost function is subject to battery pack current limits and state of charge (SOC) terminal costs at the ends of the rolling road segments. Command signals are sent to the engine and motor to output engine and motor torque based on the calculated minimum cost function.

Abstract: A method for estimating a state of a battery pack using a controller having battery state estimator (BSE) logic includes receiving or delivering a constant baseline current via the battery pack. Current oscillations having time-variant frequency content are selectively injected into the baseline current via the controller in response to a predetermined condition. The baseline current and the current oscillations combine to form a final current. The method includes estimating a battery parameter via the BSE logic concurrently with the current oscillations to generate an estimated battery parameter, and estimating the present state of the battery pack via the controller using the estimated battery parameter. An electrical system includes a rotary electric machine that is electrically connected to and driven by the battery pack, and a controller configured to execute the method.