Abstract: A method of semiconductor fabrication includes providing a semiconductor structure having a substrate and first, second, third, and fourth fins above the substrate. The method further includes forming an n-type epitaxial source/drain (S/D) feature on the first and second fins, forming a p-type epitaxial S/D feature on the third and fourth fins, and performing a selective etch process on the semiconductor structure to remove upper portions of the n-type epitaxial S/D feature and the p-type epitaxial S/D feature such that more is removed from the n-type epitaxial S/D feature than the p-type epitaxial S/D feature.

Abstract: The present disclosure provides semiconductor devices and methods of forming the same. A semiconductor device according to one embodiment of the present disclosure includes a first fin-shaped structure extending lengthwise along a first direction over a substrate, a first epitaxial feature over a source/drain region of the first fin-shaped structure, a gate structure disposed over a channel region of the first fin-shaped structure and extending along a second direction perpendicular to the first direction, and a source/drain contact over the first epitaxial feature. The bottommost surface of the gate structure is closer to the substrate than a bottommost surface of the source/drain contact.

Abstract: A battery system is electrically connected to a power bus that is arranged to supply electric power to an on-vehicle actuator such as an electric traction machine. Controlling electric power flow in the battery pack includes determining states of charge for the plurality of battery packs, identifying one of the battery packs as a weakest battery pack based upon the states of charge, and determining an internal circulating current being transferred via the wiring harness that is associated with charging of the weakest battery pack. Electric power transfer through the wiring harness and the power bus is controlled such that the internal circulating current is less than an internal circulating current limit. In one embodiment, the internal circulating current limit is determined in relation to battery temperature.

Abstract: Embodiments of the present disclosure relate to a method, a device and a computer program product for managing backup data. The method comprises receiving a first request from a user for managing backup data on a first virtual machine management platform. The method further comprises sending a second request comprising a user identifier and a platform identifier to a backup server. The method further comprises receiving, from the backup server, a first virtual machine identifier of the first virtual machine used by the user on the second virtual machine management platform and backup records corresponding to the first virtual machine identifier. The method further comprises determining, based on the first virtual machine identifier, whether a second virtual machine matched with the first virtual machine is present in the first virtual machine management platform.

Abstract: An embodiment method includes: forming fins extending from a semiconductor substrate; depositing an inter-layer dielectric (ILD) layer on the fins; forming masking layers on the ILD layer; forming a cut mask on the masking layers, the cut mask including a first dielectric material, the cut mask having first openings exposing the masking layers, each of the first openings surrounded on all sides by the first dielectric material; forming a line mask on the cut mask and in the first openings, the line mask having slot openings, the slot openings exposing portions of the cut mask and portions of the masking layers, the slot openings being strips extending perpendicular to the fins; patterning the masking layers by etching the portions of the masking layers exposed by the first openings and the slot openings; and etching contact openings in the ILD layer using the patterned masking layers as an etching mask.

Abstract: A brain tumor image segmentation method and device are disclosed. The disclosed method includes acquiring a basic white matter template generated based on brain magnetic resonance images of a plurality of healthy samples, collecting corresponding low, mid and high b-value diffusion weighted images of the brain of a patient, segmenting out a tumor region including the tumor body and the edema on each image based on the signal distribution of each image in a first set image group of the patient, removing the normal white matter region from the tumor region according to the basic white matter template and the high b-value diffusion weighted image, and classifying the value of the voxel in each image in a second set image group and a second apparent diffusion coefficient image obtained through calculations to obtain a tumor body region and an edema region.

Abstract: Various embodiments of the present disclosure provide a via-first process for connecting a contact to a gate electrode. In some embodiments, the contact is formed extending through a first interlayer dielectric (ILD) layer to a source/drain region bordering the gate electrode. An etch stop layer (ESL) is deposited covering the first ILD layer and the contact, and a second ILD layer is deposited covering the ESL. A first etch is performed into the first and second ILD layers and the etch stop layer to form a first opening exposing the gate electrode. A series of etches is performed into the second ILD layer and the etch stop layer to form a second opening overlying the contact and overlapping the first opening, such that a bottom of the second opening slants downward from the contact to the first opening. A gate-to-contact (GC) structure is formed filling the first and second openings.

Abstract: A display pixel is provided that is operable to support hybrid compensation scheme having both in-pixel threshold voltage canceling and external threshold voltage compensation. The display may include multiple p-type silicon transistors with at least one n-type semiconducting-oxide transistor and one storage capacitor. An on-bias stress phase may be performed prior to a threshold voltage sampling and data programming phase to mitigate hysteresis and improve first frame response. In low refresh rate displays, a first additional on-bias stress operation can be performed separate from the threshold voltage sampling and data programming phase during a refresh frame and a second additional on-bias stress operation can be performed during a vertical blanking frame. The display pixel may be configured to receive an initialization voltage and an anode reset voltage, either of which can be dynamically tuned to match the stress of the first and second additional on-bias stress operations to minimize flicker.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a power rail; a bottom semiconductor layer formed over the dielectric layer; a backside spacer formed along a sidewall of the bottom semiconductor layer; a conductive feature contacting a sidewall of the dielectric layer and a sidewall of the backside spacer; channel semiconductor layers over the bottom semiconductor layer, wherein the channel semiconductor layers are stacked up and separated from each other; a metal gate structure wrapping each of the channel semiconductor layers; and an epitaxial source/drain (S/D) feature contacting a sidewall of each of the channel semiconductor layers, wherein the epitaxial S/D feature contacts the conductive feature, and the conductive feature contacts the power rail.

Abstract: A method for forming a FinFET device structure is provided. The method includes forming a fin structure over a substrate and forming a gate dielectric layer over the fin structure. The method also includes forming a gate electrode layer over the gate dielectric layer and forming a source/drain (S/D) structure adjacent to the gate electrode layer. In addition, the method includes forming an S/D contact structure over the S/D structure. The method also includes forming a first conductive layer in direct with the gate electrode layer. A bottom surface of the first conductive layer is lower than a top surface of the gate dielectric layer. The method further includes forming a second conductive layer over the first conductive layer. The gate electrode layer is electrically connected to the second conductive layer by the first conductive layer.

Abstract: A polycarbonate polyol is provided. The polycarbonate polyol comprises a repeating unit represented by the following formula (I) and terminal hydroxyls: in formula (I), R is a substituted or unsubstituted C2-C20 divalent aliphatic hydrocarbyl, wherein the 1H-NMR spectrum of the polycarbonate polyol has an integral value A of signals from 4.00 ppm to 4.50 ppm and an integral value D of signals from 0.90 ppm to 1.10 ppm, the ratio of D to A (D/A) ranges from 0.03 to 1.45, and the 1H-NMR spectrum is measured by using deuterated chloroform as a solvent and tetramethylsilane as a reference substance.

Abstract: A FinFET device structure is provided. The FinFET device structure includes a first gate structure formed over a fin structure, and a conductive layer formed over the first gate structure. The FinFET device structure includes a first capping layer formed over the conductive layer, and a top surface of the conductive layer is in direct contact with a bottom surface of the first capping layer.

Abstract: A lamp has a safety circuit connected to first and second electrical connection terminals. A test is used to detect if the first and second electrical connection terminals are both connected to external power without an interfering impedance such a human body, and only then enable operation of the lamp. A time for the test is different from a time when another lamp in the system applies a test.

Abstract: In an approach for debugging and simulating application runtime execution, a processor loads source code and logs into a debug tool. A processor generates log debug information including a log map, a log variable cross reference table, and a method call stack tree. A processor determines a plurality of log blocks based on log context in the logs and the method call stack tree. A processor maps the source code to the logs for each log block. A processor suggests a starting point and a breakpoint based on the log variable cross reference table and the log blocks. A processor compares a source code variable value to a log variable value and a source code execution path to a log execution path based on the mapping set between the source code and the logs. A processor simulates the source code variable value with the log variable value.

Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and a metal gate structure formed over the substrate. The semiconductor structure further includes a sealing layer comprising an inner sidewall and an outermost sidewall. In addition, the inner sidewall is in direct contact with the metal gate structure and the outermost sidewall is away from the metal gate structure. The semiconductor structure further includes a mask structure formed over the metal gate structure. In addition, the mask structure has a straight sidewall over the metal gate structure and a sloped sidewall extending from the inner sidewall of the sealing layer and passing over the outmost sidewall of the sealing layer.

Abstract: An AFI-CHA hybrid crystal molecular sieve and an NH3-SCR catalyst using the AFI-CHA hybrid crystal molecular sieve as a carrier, and preparation methods thereof are disclosed. The AFI-CHA hybrid crystal molecular sieve includes an AFI-type SAPO-5 molecular sieve and a CHA-type SAPO-34 molecular sieve, with hybrid crystal grains of AFI and CHA. The hybrid crystal molecular sieve is synthesized by a hydrothermal synthesis method and can be obtained by changing the structure directing agent, the heating rate and the calcinating temperature in the preparation process. Further, copper is loaded on the basis of the hybrid crystal molecular sieve to prepare copper-based NH3-SCR catalyst and corresponding monolithic catalyst. The catalytic activity and hydrothermal stability of the catalyst are significantly improved by the hybrid crystal molecular sieve.

Abstract: Semiconductor devices and methods of fabricating semiconductor devices are provided. The present disclosure provides a semiconductor device that includes a first fin structure and a second fin structure each extending from a substrate; a first gate segment over the first fin structure and a second gate segment over the second fin structure; a first isolation feature separating the first and second gate segments; a first source/drain (S/D) feature over the first fin structure and adjacent to the first gate segment; a second S/D feature over the second fin structure and adjacent to the second gate segment; and a second isolation feature also disposed in the trench. The first and second S/D features are separated by the second isolation feature, and a composition of the second isolation feature is different from a composition of the first isolation feature.

Abstract: This invention provides methods, processes, compounds and compositions for modulating the gene expression or secretion of adhesion proteins, angiopoietins or their receptors to cure diseases, for anti-angiogenesis and for treating parasites, wherein the adhesion proteins or receptors comprise fibronectin, integrins family, myosin, vitronectin, collagen, laminin, glycosylation cell surface proteins, polyglycans, cadherin, heparin, tenascin, CD 54, CAM, elastin and FAK; wherein the angiopoietins comprise angiopoietin 1, angiopoietin 2, angiopoietin 3, angiopoietin 4, angiopoietin 5, angiopoietin 6, angiopoietin 7, angiopoietin-like 1, angiopoietin-like 2, angiopoietin-like 3, angiopoietin-like 4, angiopoietin-like 5, angiopoietin-like 6, and angiopoietin-like 7; wherein the cancers comprise breast cancer, leukocyte cancer, liver cancer, ovarian cancer, bladder cancer, prostate cancer, skin cancer, bone cancer, brain cancer, leukemia cancer, lung cancer, colon cancer, CNS cancer, melanoma cancer, renal cancer, c

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a power rail; a bottom semiconductor layer formed over the dielectric layer; a backside spacer formed along a sidewall of the bottom semiconductor layer; a conductive feature contacting a sidewall of the dielectric layer and a sidewall of the backside spacer; channel semiconductor layers over the bottom semiconductor layer, wherein the channel semiconductor layers are stacked up and separated from each other; a metal gate structure wrapping each of the channel semiconductor layers; and an epitaxial source/drain (S/D) feature contacting a sidewall of each of the channel semiconductor layers, wherein the epitaxial S/D feature contacts the conductive feature, and the conductive feature contacts the power rail.

Abstract: A method according to the present disclosure includes receiving a workpiece that includes a gate structure, a first gate spacer feature, a second gate spacer feature, a gate-top dielectric feature over the gate structure, the first gate spacer feature and the second gate spacer feature, a first source/drain feature over a first source/drain region, a second source/drain feature over a second source/drain region, a first dielectric layer over the first source/drain feature, and a second dielectric layer over the second source/drain feature. The method further includes replacing a top portion of the first dielectric layer with a first hard mask layer, forming a second hard mask layer over the first hard mask layer while the second dielectric layer is exposed, etching the second dielectric layer to form a source/drain contact opening and to expose the second source/drain feature, and forming a source/drain contact over the second source/drain feature.