Abstract: Provided is a sensor and method for weld defect detection. The sensor includes several piezoelectric elements which form a matrix arranged on a flexible substrate. Each piezoelectric element is covered with a damping block and surrounded by sound absorbing material, within a flexible protective film. The sensor is simple, highly adaptable and high detection efficiency, which is especially suitable for the quick in-service inspection of long distance welds in large equipment, it has high degree of automation.

Abstract: A display may include an array of organic light-emitting diode display pixels having transistors characterized by threshold voltages subject to transistor variations. Compensation circuitry may be used to sense a current from selected display pixels. A display pixel may include a drive transistor, a gate setting transistor for driving a reference voltage onto the gate terminal of the drive transistor, a data loading and current sensing transistor for connecting the drive transistor to a data/current-sensing line, a light-emitting diode, an emission control transistor coupled between the drive transistor and the diode, and an anode resetting transistor for selectively resetting the anode terminal of the diode. During in-frame current sensing operations, the emission control transistor may be turned off to decouple the drive transistor from the diode, thereby blocking off any residue current and lateral leakage current that may be present at the diode.

Abstract: A method and structure for forming semiconductor device includes forming a contact via opening in a first dielectric layer, where the contact via opening exposes a first portion of a contact etch stop layer (CESL). The method further includes etching both the first portion of the CESL exposed by the contact via opening and adjacent lateral portions of the CESL to expose a source/drain contact and form an enlarged contact via opening having cavities disposed on either side of a bottom portion of the enlarged contact via opening. The method further includes forming a passivation layer on sidewall surfaces of the enlarged contact via opening including on sidewall surfaces of the cavities. The method further includes depositing a first metal layer within the enlarged contact via opening and within the cavities to provide a contact via in contact with the exposed source/drain contact.

Abstract: In an embodiment, a device includes: a gate electrode; a epitaxial source/drain region adjacent the gate electrode; one or more inter-layer dielectric (ILD) layers over the epitaxial source/drain region; a first source/drain contact extending through the ILD layers, the first source/drain contact connected to the epitaxial source/drain region; a contact spacer surrounding the first source/drain contact; and a void disposed between the contact spacer and the ILD layers.

Abstract: A semiconductor device includes an n-type FET device and a p-type FET device. The n-type FET device includes a first substrate region, a first gate stack, a first gate spacer over sidewalls of the first gate stack, and an n-type epitaxial feature in a source/drain (S/D) region of the n-type FET device. The p-type FET device includes a second substrate region, a second gate stack, a second gate spacer over sidewalls of the second gate stack, and a p-type epitaxial feature in an S/D region of the p-type FET device. A vertical distance between a bottom surface of the first gate spacer and a lowest point of an upper surface of the n-type epitaxial feature is greater than a vertical distance between a bottom surface of the second gate spacer and a lowest point of an upper surface of the p-type epitaxial feature.

Abstract: An AFI-CHA hybrid crystal molecular sieve and an NH3—SCR catalyst using the AFI-CHA hybrid crystal molecular sieve as a carrier, and preparation methods thereof are disclosed. The AFI-CHA hybrid crystal molecular sieve includes an AFI-type SAPO-5 molecular sieve and a CHA-type SAPO-34 molecular sieve, with hybrid crystal grains of AFI and CHA. The hybrid crystal molecular sieve is synthesized by a hydrothermal synthesis method and can be obtained by changing the structure directing agent, the heating rate and the calcinating temperature in the preparation process. Further, copper is loaded on the basis of the hybrid crystal molecular sieve to prepare copper-based NH3—SCR catalyst and corresponding monolithic catalyst. The catalytic activity and hydrothermal stability of the catalyst are significantly improved by the hybrid crystal molecular sieve.

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiments, a semiconductor device includes an n-type transistor region and a p-type transistor region. The n-type transistor region includes a first gate stack, a first gate spacer over sidewalls of the first gate stack, an n-type epitaxial feature in a source/drain (S/D) region of the n-type transistor region, and a first metal silicide layer over the n-type epitaxial feature. The p-type transistor region includes a second gate stack, a second gate spacer over sidewalls of the second gate stack, a p-type epitaxial feature in an S/D region of the p-type transistor region, a dopant-containing implant layer over the p-type epitaxial feature, and a second metal silicide layer over the dopant-containing implant layer. The dopant-containing implant layer includes a metallic dopant.

Abstract: The present disclosure provides devices, systems, kits and methods useful for quantitation of biomolecules such as intact proteins and nucleic acids.

Abstract: System and method of dynamically balancing a rechargeable energy storage assembly having two or more respective units, a respective switch for each of the respective units and at least one sensor. The system includes a controller configured to control operation of the respective switch. The respective switch is configured to enable a respective circuit connection to the respective units when in an ON state and disable the respective circuit connection when in an OFF state. The respective units are characterized by a respective state of charge obtained based in part on the at least one sensor. A controller is configured to selectively employ at least one of a plurality of charging modes to charge one or more of the respective units, through operation of the respective switch. The plurality of charging modes includes a rest charging mode, a rapid initial charging mode and a rapid final charging mode.

Abstract: A contact structure of a semiconductor device includes a gate contact in contact with a gate structure and extending through a first dielectric layer, a source/drain contact in contact with a source/drain feature and extending through the first dielectric layer, a common rail line in contact with the gate contact and the source/drain contact, and a power rail line in contact with the common rail line and electrically coupled to a ground of the semiconductor device.

Abstract: A semiconductor structure includes an isolation feature disposed over a semiconductor substrate, a semiconductor fin disposed over the semiconductor substrate and adjacent to the isolation feature, a source/drain (S/D) feature disposed over the semiconductor substrate and apart from the isolation feature, an interlayer dielectric (ILD) layer disposed over the isolation feature and the S/D feature, a first contact plug disposed in the ILD layer and over the isolation feature, a second contact plug disposed in the ILD layer and over the S/D feature, and a dielectric layer between surfaces of the first contact plug and the ILD layer and between a sidewall of the second contact plug and the ILD layer, where a bottom surface of the second contact plug is free of the dielectric layer.

Abstract: A method and a system for extracting vocabulary for imagery of a product, including: collecting a comment text data of a target product, segmenting the comment text data to obtain an evaluation vocabulary; extracting a high-frequency word used to evaluate an appearance as a central word from the evaluation vocabulary, and extracting an adjective from the evaluation vocabulary to obtain the adjectives; converting the evaluation vocabulary into a word vector, calculating a similarity between each adjectives and the central word based on the word vector, extracting a corresponding adjectives according to the similarity as an original vocabulary for imager; clustering the original vocabulary for imagery, exacting the corresponding original vocabulary for imagery according to a clustering result as a vocabulary for imagery, which can extract the vocabulary for imagery based on the comment text data, reduce the labor cost, and improve the extraction efficiency.

Abstract: A method and a system for obtaining a product prototype based on an eye movement data. The method comprises the following steps: Obtaining A front-side view of the target product for establishing a underlying sample library; The target product is divided into several detection areas according to its structure or function features, and the eye movement is detected to obtain the fixation time of the target product The invention adopts computer and image collecting technology to process the observation data of human eyes, and adopts K-means clustering to obtain the prototype of the target product, to assist the designer to grasp the categories of personal interest contour, so as to improve the design effect of product appearance.

Abstract: Semiconductor devices and methods of fabricating semiconductor devices are provided. The present disclosure provides a semiconductor device that includes a first fin structure and a second fin structure each extending from a substrate; a first gate segment over the first fin structure and a second gate segment over the second fin structure; a first isolation feature separating the first and second gate segments; a first source/drain (S/D) feature over the first fin structure and adjacent to the first gate segment; a second S/D feature over the second fin structure and adjacent to the second gate segment; and a second isolation feature also disposed in the trench. The first and second S/D features are separated by the second isolation feature, and a composition of the second isolation feature is different from a composition of the first isolation feature.

Abstract: Vertical interconnect structures and methods of forming are provided. The vertical interconnect structures may be formed by partially filling a first opening through one or more dielectric layers with layers of conductive materials. A second opening is formed in a dielectric layer such that a depth of the first opening after partially filling with the layers of conductive materials is close to a depth of the second opening. The remaining portion of the first opening and the second opening may then be simultaneously filled.

Abstract: Various embodiments of the present disclosure provide a via-first process for connecting a contact to a gate electrode. In some embodiments, the contact is formed extending through a first interlayer dielectric (ILD) layer to a source/drain region bordering the gate electrode. An etch stop layer (ESL) is deposited covering the first ILD layer and the contact, and a second ILD layer is deposited covering the ESL. A first etch is performed into the first and second ILD layers and the etch stop layer to form a first opening exposing the gate electrode. A series of etches is performed into the second ILD layer and the etch stop layer to form a second opening overlying the contact and overlapping the first opening, such that a bottom of the second opening slants downward from the contact to the first opening. A gate-to-contact (GC) structure is formed filling the first and second openings.

Abstract: A method includes forming a first conductive feature over a semiconductor substrate, forming an ILD layer over the first conductive feature, patterning the ILD layer to form a trench, and forming a conductive layer over the patterned ILD layer to fill the trench. The method further includes polishing the conductive layer to form a via contact configured to interconnect the first conductive feature with a second conductive feature, where polishing the conductive layer exposes a top surface of the ILD layer, polishing the exposed top surface of the ILD layer, such that a top portion of the via contact protrudes from the exposed top surface of the ILD layer, and forming the second conductive feature over the via contact, such that the top portion of the via contact extends into the second conductive feature.

Abstract: The present disclosure provides semiconductor devices and methods of forming the same. A semiconductor device according to one embodiment of the present disclosure includes a first fin-shaped structure extending lengthwise along a first direction over a substrate, a first epitaxial feature over a source/drain region of the first fin-shaped structure, a gate structure disposed over a channel region of the first fin-shaped structure and extending along a second direction perpendicular to the first direction, and a source/drain contact over the first epitaxial feature. The bottommost surface of the gate structure is closer to the substrate than a bottommost surface of the source/drain contact.

Abstract: In some embodiments, a display stack includes a set of light-emitting elements, and a display backplane that includes a set of conductors and is electrically coupled to the set of light-emitting elements. A conductor in the set of conductors has a length, and a curved edge extending along at least a portion of the length. In some embodiments, a display stack includes a set of light-emitting elements; a set of transistors, electrically coupled to the set of light-emitting elements; and a set of conductors, electrically coupled to the set of transistors. The set of transistors may be electrically coupled to the set of conductors at a set of conductive pads. A plurality of conductive pads in the set of conductive pads is coupled to a single conductor in the set of conductors. The single conductor approaches different conductive pads in the plurality of conductive pads at different angles.

Abstract: A battery system is electrically connected to a power bus that is arranged to supply electric power to an on-vehicle actuator such as an electric traction machine. Controlling electric power flow in the battery pack includes determining states of charge for the plurality of battery packs, identifying one of the battery packs as a weakest battery pack based upon the states of charge, and determining an internal circulating current being transferred via the wiring harness that is associated with charging of the weakest battery pack. Electric power transfer through the wiring harness and the power bus is controlled such that the internal circulating current is less than an internal circulating current limit. In one embodiment, the internal circulating current limit is determined in relation to battery temperature.