Thermally enhanced semiconductor package having field effect transistors with back-gate feature

- Qorvo US, Inc.

The present disclosure relates to a thermally enhanced semiconductor package having field effect transistors (FETs) with a back-gate feature. The thermally enhanced semiconductor package includes a first buried oxide (BOX) layer, a first epitaxial layer over the first BOX layer, a second BOX layer over the first epitaxial layer, a second epitaxial layer over the second BOX layer and having a source, a drain, and a channel between the source and the drain, a gate dielectric aligned over the channel, and a front-gate structure over the gate dielectric. Herein, a back-gate structure is formed in the first epitaxial layer and has a back-gate region aligned below the channel. A FET is formed by the front-gate structure, the source, the drain, the channel, and the back-gate structure.

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Description

RELATED APPLICATIONS

This application claims the benefit of provisional patent application Ser. No. 62/363,499, filed Jul. 18, 2016. This application is related to concurrently filed U.S. patent application Ser. No. 15/652,867, entitled “THERMALLY ENHANCED SEMICONDUCTOR PACKAGE HAVING FIELD EFFECT TRANSISTORS WITH BACK-GATE FEATURE” the disclosures of which are hereby incorporated herein by reference in their entirety.

FIELD OF THE DISCLOSURE

The present disclosure relates to a semiconductor package having field effect transistors (FETs) and a process for making the same, and more particularly to a thermally enhanced semiconductor package having FETs with a back-gate feature, and a process to enhance thermal performance of the semiconductor package.

BACKGROUND

With the current popularity of portable communication devices and developed semiconductor fabrication technology, high speed and high performance transistors are more densely integrated on semiconductor dies. Consequently, the amount of heat generated by the semiconductor dies will increase significantly due to the large number of transistors integrated on the semiconductor dies, the large amount of power passing through the transistors, and the high operation speed of the transistors. Accordingly, it is desirable to package the semiconductor dies in a configuration for better heat dissipation.

The field effect transistor (FET) fabricated on silicon-on-insulator (SOI) substrate is widely used in communication applications because of its reliability, a large scale capacity of wafer production, and low cost. SOI technologies at 65 nm or below (45 nm, 22 nm, etc.) need to implement back-gate transistors to improve control over the channel and reduce leakage current.

To accommodate the increased heat generation of high performance dies and to utilize the advantages of FET on SOI, it is therefore an object of the present disclosure to provide an improved semiconductor package design with FETs in a configuration for better heat dissipation. In addition, there is also a need to implement back-gates for FETs to improve control over the channel and reduce leakage current.

SUMMARY

The present disclosure relates to a thermally enhanced semiconductor package having field effect transistors (FETs) with a back-gate feature, and a process for making the same. According to one embodiment, a thermally enhanced semiconductor package includes a first buried oxide (BOX) layer, a first epitaxial layer over the first BOX layer, a second BOX layer over the first epitaxial layer, a second epitaxial layer over the second BOX layer, a gate dielectric over the second epitaxial layer, and a front-gate structure formed over the gate dielectric. Herein, the second epitaxial layer has a source, a drain, and a channel between the source and the drain. The gate dielectric and the front-gate structure are aligned over the channel. A back-gate structure is formed in the first epitaxial layer and has a back-gate region aligned below the channel. A FET is formed by the front-gate structure, the source, the drain, the channel, and the back-gate structure.

According to another embodiment, the thermally enhanced semiconductor package further includes a thermal conductive component, which has a thermal conductivity greater than 2.5 w/m·k. Herein, the first BOX layer resides over the thermal conductive component.

According to another embodiment, the first epitaxial layer further includes first isolation regions, which surround the back-gate structure. And the second epitaxial layer further includes second isolation regions, which surround the source and the drain.

According to another embodiment, the thermally enhanced semiconductor package further includes a front-side back-gate contact coupled to the back-gate structure via a front-side interconnect. The front-side interconnect extends through the second BOX layer and one of the second isolation regions of the second epitaxial layer, where the one of the second isolation regions is adjacent to the drain or the source.

According to another embodiment, the thermally enhanced semiconductor package further includes a back-side back-gate contact coupled to the back-gate structure via a back-side interconnect. The back-side interconnect extends through the first BOX layer and the thermal conductive component.

Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.

BRIEF DESCRIPTION OF THE DRAWING FIGURES

The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

FIGS. 1A-1E provide exemplary steps that illustrate a process to fabricate an exemplary thermally enhanced semiconductor package.

FIG. 2 provides an exemplary field effect transistor (FET) included in the exemplary thermally enhanced semiconductor package shown in FIG. 1E.

FIG. 3 provides an alternative FET included in the exemplary thermally enhanced semiconductor package shown in FIG. 1E.

FIGS. 4A-4E provide exemplary steps that illustrate a process to fabricate an alternative thermally enhanced semiconductor package.

FIG. 5 provides an exemplary FET included in the alternative thermally enhanced semiconductor package shown in FIG. 4E.

FIG. 6 provides an alternative FET included in the alternative thermally enhanced semiconductor package shown in FIG. 4E.

FIG. 7 provides an alternative FET included in the alternative thermally enhanced semiconductor package shown in FIG. 4E.

It will be understood that for clear illustrations, FIG. 1A-FIG. 7 may not be drawn to scale.

DETAILED DESCRIPTION

The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

The present disclosure relates to a thermally enhanced semiconductor package having field effect transistors (FETs) with a back-gate feature, and a process for making the same. FIGS. 1A-1E provide exemplary steps that illustrate a process to fabricate an exemplary thermally enhanced semiconductor package. Although the exemplary steps are illustrated in a series, the exemplary steps are not necessarily order dependent. Some steps may be done in a different order than that presented. Further, processes within the scope of this disclosure may include fewer or more steps than those illustrated in FIGS. 1A-1E.

Initially, a semiconductor package 10 is provided as depicted in FIG. 1A. For the purpose of this illustration, the semiconductor package 10 includes a module substrate 12, a flip chip die 14, an underfilling layer 16, and a mold compound component 18. In different applications, the semiconductor package 10 may include multiple flip chip dies. In detail, the flip chip die 14 includes a device layer 20, a number of interconnects 22 extending from a lower surface of the device layer 20 and coupled to an upper surface of the module substrate 12, and a silicon handle layer 24 over the device layer 20. As such, the backside of the silicon handle layer 24 is a top surface of the flip chip die 14.

In addition, the underfilling layer 16 resides over the upper surface of the module substrate 12, such that the underfilling layer 16 encapsulates the interconnects 22 and underfills the flip chip die 14 between the lower surface of the device layer 20 and the upper surface of the module substrate 12. The underfilling layer 16 may be formed from conventional polymeric compounds, which serve to mitigate the stress effects caused by Coefficient of Thermal Expansion (CTE) mismatch between the flip chip die 14 and the module substrate 12.

The mold compound component 18 resides over the underfilling layer 16 and encapsulates at least the sides of the device layer 20 and the sides of the silicon handle layer 24. The mold compound component 18 may be used as an etchant barrier to protect the flip chip die 14 against etchant chemistries such as Tetramethylammonium hydroxide (TMAH), potassium hydroxide (KOH), sodium hydroxide (NaOH), and acetylcholine (ACH) in the following steps. The mold compound component 18 may be formed from a same or different material as the underfilling layer 16. When the first mold compound 18 and the underfilling layer 16 are formed from a same material, the first mold compound 18 and the underfilling layer 16 may be formed simultaneously. One exemplary material used to form the mold compound component 18 is an organic epoxy resin system.

Next, the mold compound component 18 is thinned down to expose the backside of the silicon handle layer 24 of the flip chip die 14, as shown in FIG. 1 B. The thinning procedure may be done with a mechanical grinding process. The following step is to remove substantially the entire silicon handle layer 24 of the flip chip die 14 to create a cavity 26 and provide the thinned flip chip die 14T with an upper surface exposed to the cavity 26, as shown in FIG. 1C. Herein, removing substantially the entire silicon handle layer 24 refers to removing at least 95% of the entire silicon handle layer 24, and perhaps a portion of the device layer 20. As such, in some applications, there is a thin layer of the substrate handle layer 24 (no more than 2 μm) left at the bottom of the cavity 26 (not shown). For other cases, the substrate handle layer 24 is removed completely and the device layer 20 is exposed at the bottom of the cavity 26. Removing substantially the entire silicon handle layer 24 may be provided by an etching process with a wet/dry etchant chemistry, which may be TMAH, KOH, ACH, NaOH, or the like.

FIG. 1D shows a step for filling the cavity 26 with a thermal conductive material 28. The thermal conductive material 28 may further reside over the mold compound component 18. The thermal conductive material 28 may be applied by various procedures, such as sheet molding, overmolding, compression molding, transfer molding, dam fill encapsulation, and screen print encapsulation. The thermal conductive material 28 may be a non-silicon high thermal conductivity mold compound with a thermal conductivity greater than 1 w/m·k or greater than 2.5 w/m·k, such as Hitachi Chemical Electronic Materials GE-506HT. A curing process (not shown) is followed to harden the thermal conductive material 28 in order to form a thermal conductive component 28C. The curing temperature is between 100° C. and 320° C. depending on which material is used as the thermal conductive material 28.

Finally, an upper surface of the thermal conductive component 28C is planarized to form a thermally enhanced semiconductor package 30 as depicted in FIG. 1E. A mechanical grinding process may be used for planarization. The upper portion of the thermal conductive component 28C may reside over the mold compound component 18.

FIG. 2 provides an exemplary FET 32 residing in the device layer 20 within a dashed section S1 of FIG. 1E. In different applications, there may be multiple FETs residing in the device layer 20. For clear illustrations, the exemplary FET 32 is shown upside down in FIG. 2. The FET 32 includes a first buried oxide (BOX) layer 34 over the thermal conductive component 28C, a first epitaxial layer 36 over the first BOX layer 34, a second BOX layer 38 over the first epitaxial layer 36, a second epitaxial layer 40 over the second BOX layer 38, a gate dielectric 42 over the second epitaxial layer 40, and a front-gate structure 44 formed over the gate dielectric 42. The front-gate structure 44 is separated from the second epitaxial layer 40 by the gate dielectric 42. Herein, the first BOX layer 34 may be formed from silicon oxide with a thickness between 5 nm and 2000 nm, or between 200 nm and 400 nm. The second BOX layer 38 may be formed from silicon oxide with a thickness between 5 nm and 2000 nm, or between 200 nm and 400 nm. The first epitaxial layer 36 has a thickness between 100 Å and 2 μm and the second epitaxial layer 40 has a thickness between 100 Å and 2 μm. Notice that, the first BOX layer 34 resides at the bottom boundary of the device layer 20 and has selective etching stop characteristics with respect to etchant chemistries (TMAH, KOH, NaOH, or ACH) for silicon. Therefore, when the silicon handle layer 24 is removed substantially with the etchant chemistries (TMAH, KOH, NaOH, or ACH) in the etching step as shown in FIG. 1C, the first BOX layer 34 provides an etchant barrier for the device layer 20.

In detail, the first epitaxial layer 36 includes a back-gate structure 46 and first isolation regions 48 surrounding the back-gate structure 46. The back-gate structure 46 has a back-gate region 50 and a back-gate extension 52 extending from the back-gate region 50 to one of the first isolation regions 48. The second BOX layer 38 is directly over the back-gate region 50. In addition, the second epitaxial layer 40 has a source 54, a drain 56, a channel 58, and second isolation regions 60. The channel 58 is formed directly over the second BOX layer 38. The source 54 is formed over the second BOX layer 38 and in contact with a first side of the channel 58. The drain 56 is formed over the second BOX layer 38 and in contact with a second side of the channel 58. The channel 58 separates the source 54 and the drain 56. The second isolation regions 60 surround the source 54 and the drain 56. Herein, the gate dielectric 42 and the front-gate structure 44 are aligned over the channel 58, and the back-gate region 50 is aligned below the channel 58. The first isolation regions 48 and the second isolation regions 60 may be formed by shallow trench isolation (STI).

The source 54, the drain 56, the channel 58, the gate dielectric 42, and the front-gate structure 44 are used to achieve a front-gate switch function of the exemplary FET 32. The source 54, the drain 56, the channel 58, the second BOX layer 38, and the back-gate structure 46 are used to achieve a back-gate switch function of the FET 32. Consequently, the FET 32 formed by the front-gate structure 44, the gate dielectric 42, the source 54, the drain 56, the channel 58, the second BOX layer 38, and the back-gate structure 46 is able to implement both front-gate switch function and back-gate switch function. Because of the first isolation regions 48, the FET 32 may have independent back-gate bias voltage from other FETs (not shown) residing in the device layer 20.

In addition, the FET 32 may also include a source contact 62 in contact with the source 54, a drain contact 64 in contact with the drain 56, a front-gate contact 66 in contact with the front-gate structure 44, and a front-side back-gate contact 68 coupled to the back-gate structure 46 via a front-side interconnect 70. The source contact 62, the drain contact 64, the front-gate contact 66, and the front-side back-gate contact 68 are over the second epitaxial layer 40 and facing the same direction. The front-side interconnect 70 extends through the second BOX layer 38 and one of the second isolation regions 60 of the second epitaxial layer 40 to connect the back-gate structure 46 to the front-side back-gate contact 68. In this embodiment, the front-side interconnect 70 is in contact with the back-gate extension 52 of the back-gate structure 46, and the one of the second isolation regions 60 penetrated by the front-side interconnect 70 is adjacent to the drain 56 or the source 54 (not shown). The front-side interconnect 70 may be formed from polysilicon or a metal material, such as tungsten or aluminum. For simplification, other necessary elements of the FET 32 such as Field Oxide, Gate Spacers, and Metal layers are not depicted.

According to another embodiment, the FET 32 has a back-side back-gate contact 72 instead of the front-side back-gate contact 68 as shown in FIG. 3. The source contact 62, the drain contact 64, and the front-gate contact 66 are over the second epitaxial layer 40 and facing a first direction; and the back-side back-gate contact 72 is below the first BOX layer 34 and facing a second direction, which is opposite the first direction. The back-side back-gate contact 72 is coupled to the back-gate structure 46 via a back-side interconnect 74, which may be formed from a low temperature deposition metal, like aluminum. The back-side interconnect 74 is formed by a backside process where an opening is selectively formed in the polymer material in 28C by using a laser ablation method, and a via metallization step. The back-side interconnect 74 extends through the first BOX layer 34 and at least a portion of the thermal conductive component 28C to connect the back-gate extension 52 to the back-side back-gate contact 72. The back-side back-gate contact 72 and the back-side interconnect 74 may be formed after the formation of the thermal conductive component 28C shown in FIG. 1E.

In some cases, the back-side interconnect 74 extends through the first BOX layer 34 and at least a portion of the thermal conductive component 28C, and connects the back-gate region 50 (not shown) instead of the back-gate extension 52 to the back-side back-gate contact 72. The actual locations of the back-side back-gate contact 72 and the back-side interconnect 74 vary in different applications. Typically, the further the back-side back-gate contact 72 is away from the back-gate region 50, the higher the possibility that the back-gate region 50 is influenced by other external terminals. Notice that, if the back-side interconnect 74 directly connects the back-gate region 50, the back-gate structure 46 may not include the back-gate extension 52.

In some cases, the FET 32 does not include either the front-side back-gate contact 68 or the back-side back-gate contact 72 (not shown). The back-gate structure 46 may be left floating and it may impact the FET 32 operation mainly through the static work-function. The floating back-gate structure 46 may help deplete the channel 58 and thus allow for better control.

FIGS. 4A-4E provide exemplary steps that illustrate a process to fabricate an alternative thermally enhanced semiconductor package. Although the exemplary steps are illustrated in a series, the exemplary steps are not necessarily order dependent. Some steps may be done in a different order than that presented. Further, processes within the scope of this disclosure may include fewer or more steps than those illustrated in FIGS. 4A-4E.

Initially, an alternative semiconductor package 10A is provided as depicted in FIG. 4A. For the purpose of this illustration, the semiconductor package 10A includes the module substrate 12, an alternative flip chip die 14A, the underfilling layer 16, and the mold compound component 18. In different applications, the semiconductor package 10A may include multiple flip chip dies. In detail, the flip chip die 14A includes an alternative device layer 20A, the interconnects 22 extending from a lower surface of the device layer 20A and coupled to the upper surface of the module substrate 12, and an alternative silicon handle layer 24A over the device layer 20A. As such, the backside of the silicon handle layer 24 is a top surface of the flip chip die 14A. The silicon handle layer 24A includes a first silicon layer 76 directly over the device layer 20A and a second silicon layer 78 over the first silicon layer 76. The first silicon layer 76 is at least 0.001% of the silicon handle layer 24A and has a thickness between 10 nm and 10000 nm. The first silicon layer 76 has a different polarity from the second silicon layer 78. If the second silicon layer 78 has an N-type polarity, the first silicon layer 76 will have a P-type polarity and there will be a P-N junction formed between the first silicon layer 76 and the second silicon layer 78. In some applications, the second silicon layer 78 may have a P-type polarity, and the first silicon layer 76 will have an N-type polarity. There is still a P-N junction formed between the first silicon layer 76 and the second silicon layer 78. Herein, the different polarities within the silicon handle layer 24A may be formed by an implanting process.

In addition, the underfilling layer 16 resides over the upper surface of the module substrate 12, such that the underfilling layer 16 encapsulates the interconnects 22 and underfills the flip chip die 14A between the lower surface of the device layer 20A and the upper surface of the module substrate 12. The underfilling layer 16 may be formed from conventional polymeric compounds, which serve to mitigate the stress effects caused by CTE mismatch between the flip chip die 14A and the module substrate 12.

The mold compound component 18 resides over the underfilling layer 16 and encapsulates at least the sides of the device layer 20A and the sides of the silicon handle layer 24A. The mold compound component 18 may be used as an etchant barrier to protect the flip chip die 14A against etchant chemistries such as TMAH, KOH, NaOH, and ACH in the following etching step. The mold compound component 18 may be formed from a same or different material as the underfilling layer 16. When the first mold compound 18 and the underfilling layer 16 are formed from a same material, the first mold compound 18 and the underfilling layer 16 may be formed simultaneously. One exemplary material used to form the mold compound component 18 is an organic epoxy resin system.

Next, the mold compound component 18 is thinned down to expose the backside of the silicon handle layer 24A of the flip chip die 14A, as shown in FIG. 4B. The thinning procedure may be done with a mechanical grinding process. The following step is to remove the second silicon layer 78 of the silicon handle layer 24A to create a cavity 26A and provide a thinned flip chip die 14AT with an upper surface exposed to the cavity 26A, as shown in FIG. 4C. Removing the second silicon layer 78 of the silicon handle layer 24A may be provided by an etching process with a wet/dry etchant chemistry, which may be TMAH, KOH, ACH, NaOH, or the like. Since the P-N junction formed between the second silicon layer 78 and the first silicon layer 76 has selective etching stop characteristics with respect to etchant chemistries (TMAH, KOH, NaOH, or ACH) for single-polarity silicon, the etching process with these etchant chemistries will stop at the P-N junction. In some applications, there may be a thin layer of the second silicon layer 78 (less than 5%) left at the bottom of the cavity 26A (not shown). For other cases, the second silicon layer 78 is removed completely and the first silicon layer 76 is exposed at the bottom of the cavity 26A.

FIG. 4D shows a step for filling the cavity 26A with the thermal conductive material 28. The thermal conductive material 28 may further reside over the mold compound component 18. The thermal conductive material 28 may be applied by various procedures, such as sheet molding, overmolding, compression molding, transfer molding, dam fill encapsulation, and screen print encapsulation. The thermal conductive material 28 may be a non-silicon high thermal conductivity mold compound with a thermal conductivity greater than 1 w/m·k or greater than 2.5 w/m·k, such as Hitachi Chemical Electronic Materials GE-506HT. A curing process (not shown) is followed to harden the thermal conductive material 28 in order to form a thermal conductive component 28C. The curing temperature is between 100° C. and 320° C. depending on which material is used as the thermal conductive material 28.

Finally, an upper surface of the thermal conductive component 28C is planarized to form an alternative thermally enhanced semiconductor package 30A as depicted in FIG. 4E. A mechanical grinding process may be used for planarization. The upper portion of the thermal conductive component 28C may reside over the mold compound component 18.

FIG. 5 provides an exemplary FET 80 included in the alternative thermally enhanced semiconductor package 30A within a dashed section SII of FIG. 4E. In different applications, there may be multiple FETs residing in the thermally enhanced semiconductor package 30A. For clear illustrations, the exemplary FET 80 is shown upside down in FIG. 5. The FET 80 includes the first silicon layer 76 over the thermal conductive component 28C, a BOX layer 82 over the first silicon layer 76, an epitaxial layer 84 over the BOX layer 82, a gate dielectric 86 over the epitaxial layer 84, and a front-gate structure 88 formed over the gate dielectric 86. The front-gate structure 88 is separated from the epitaxial layer 84 by the gate dielectric 86. Herein, the BOX layer 82 is formed from silicon oxide with a thickness between 5 nm and 2000 nm, or between 200 nm and 400 nm. The epitaxial layer 84 has a thickness between 100 Å and 2 μm.

In detail, the first silicon layer 76 includes a back-gate structure 90, which has a back-gate region 92 and back-gate extensions 94. The back-gate region 92 is surrounded by the back-gate extensions 94 and may have a higher implant density than the back-gate extensions 94. The BOX layer 82 is directly over the back-gate region 92. In addition, the epitaxial layer 84 has a source 96, a drain 98, a channel 100, and epitaxial isolation regions 102. The channel 100 is formed directly over the BOX layer 82. The source 96 is formed over the BOX layer 82 and in contact with a first side of the channel 100. The drain 98 is formed over the BOX layer 82 and in contact with a second side of the channel 100. The channel 100 separates the source 96 and the drain 98. The epitaxial isolation regions 102 surround the source 96 and the drain 98. Herein, the back-gate region 92 is aligned below the channel 100. The gate dielectric 86 and the front-gate structure 88 are aligned over the channel 100. The epitaxial isolation regions 102 may be formed by STI.

The source 96, the drain 98, the channel 100, the gate dielectric 86, and the front-gate structure 88 are used to achieve a front-gate switch function of the exemplary FET 80. The source 96, the drain 98, the channel 100, the BOX layer 82, and the back-gate structure 90 are used to achieve a back-gate switch function of the FET 80. Consequently, the FET 80 formed by the front-gate structure 88, the gate dielectric 86, the source 96, the drain 98, the channel 100, the BOX layer 82, and the back-gate structure 90 is able to implement both front-gate switch function and back-gate switch function.

In addition, the FET 80 may also include a source contact 104 in contact with the source 96, a drain contact 106 in contact with the drain 98, a front-gate contact 108 in contact with the front-gate structure 88, and a front-side back-gate contact 110 coupled to the back-gate structure 90 via a front-side interconnect 112. The source contact 104, the drain contact 106, the front-gate contact 108, and the front-side back-gate contact 110 are over the epitaxial layer 84 and facing the same direction. The front-side interconnect 112 extends through the BOX layer 82 and one of the epitaxial isolation regions 102 of the epitaxial layer 84 to connect the back-gate structure 90 to the front-side back-gate contact 110. In this embodiment, the front-side interconnect 112 is in contact with one of the back-gate extensions 94, and the one of the epitaxial isolation regions 102 penetrated by the front-side interconnect 112 is adjacent to the drain 98 or the source 96 (not shown). The front-side interconnect 112 may be formed from polysilicon or a metal material, such as tungsten or aluminum. For simplification, other necessary elements of the FET 32 such as Field Oxide, Gate Spacers, and Metal layers are not depicted.

In order to provide individual per-FET back-gate manipulation, the first silicon layer 76 may also include back-gate isolation regions 114 as shown in FIG. 6. The back-gate isolation regions 114 extend through the first silicon layer 76 and surround the back-gate structure 90. The back-gate isolation regions 114 separate the back-gate structure 90 for the FET 80 from back-gate structures for other FETs (not shown).

According to another embodiment, the FET 80 has a back-side back-gate contact 116 instead of the front-side back-gate contact 110 as shown in FIG. 7. The back-side back-gate contact 116 is coupled to the back-gate structure 90 via a back-side interconnect 118, which may be formed from a low temperature deposition metal, like aluminum. The back-side interconnect 118 is formed by a backside process where an opening is selectively formed in the polymer material in 28C by using a laser ablation method, and a via metallization step. The back-side interconnect 118 extends through at least a portion of the thermal conductive component 28C and connects to one of the back-gate extensions 94. The back-side back-gate contact 116 and the back-side interconnect 118 may be formed after the formation of the thermal conductive component 28C shown in FIG. 4E.

In some cases, the back-side interconnect 118 extends through at least a portion of the thermal conductive component 28C and connects the back-gate region 92 instead of one of the back-gate extensions 94 (not shown). The actual location of the back-side back-gate contact 116 and the back-side interconnect 118 varies in different applications. Typically, the further the back-side back-gate contact 116 is away from the back-gate region 92, the higher the possibility that the back-gate region 92 is influenced by other external terminals.

Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.

Claims

1. An apparatus comprising:

a first buried oxide (BOX) layer;
a non-silicon thermal conductive component, wherein the first BOX layer resides over the non-silicon thermal conductive component;
a first epitaxial layer over the first BOX layer;
a second BOX layer over the first epitaxial layer;
a second epitaxial layer over the second BOX layer and having a source, a drain, and a channel between the source and the drain;
a gate dielectric aligned over the channel; and
a front-gate structure over the gate dielectric, wherein a back-gate structure is formed in the first epitaxial layer and has a back-gate region aligned below the channel; and a field effect transistor (FET) is formed by the front-gate structure, the source, the drain, the channel, and the back-gate structure.

2. The apparatus of claim 1 wherein:

the first epitaxial layer further comprises first isolation regions, which surround the back-gate structure; and
the second epitaxial layer further comprises second isolation regions, which surround the source and the drain.

3. The apparatus of claim 2 wherein the first isolation regions and the second isolation regions are formed by shallow trench isolation (STI).

4. The apparatus of claim 2 further comprising a front-side back-gate contact coupled to the back-gate structure via a front-side interconnect, which extends through the second BOX layer and one of the second isolation regions of the second epitaxial layer, wherein the one of the second isolation regions is adjacent to the drain or the source.

5. The apparatus of claim 4 wherein:

the back-gate structure further comprises a back-gate extension that extends from the back-gate region to one of the first isolation regions; and
the front-side interconnect is in contact with the back-gate extension.

6. The apparatus of claim 4 wherein the front-side interconnect is formed from polysilicon.

7. The apparatus of claim 1 further comprising a source contact directly over the source, a drain contact directly over the drain, and a front-gate contact directly over the front-gate structure.

8. The apparatus of claim 1 wherein the first BOX layer resides directly on the non-silicon thermal conductive component.

9. The apparatus of claim 1 wherein a silicon layer with a thickness no more than 2 82 m is between the first BOX layer and the non-silicon thermal conductive component.

10. The apparatus of claim 1 wherein the non-silicon thermal conductive component has a thermal conductivity greater than 1 w/m·k.

11. The apparatus of claim 1 wherein the non-silicon thermal conductive component has a thermal conductivity greater than 2.5 w/m·k.

12. The apparatus of claim 1 further comprising a back-side back-gate contact coupled to the back-gate structure via a back-side interconnect, which extends through the first BOX layer and the non-silicon thermal conductive component.

13. The apparatus of claim 12 wherein the back-side interconnect is in contact with the back-gate region.

14. The apparatus of claim 12 wherein the back-side interconnect is formed from polysilicon.

15. The apparatus of claim 12 wherein:

the first epitaxial layer further comprises first isolation regions, which surround the back-gate structure; and
the second epitaxial layer further comprises second isolation regions, which surround the source and the drain.

16. The apparatus of claim 15 wherein:

the back-gate structure further comprises a back-gate extension that extends from the back-gate region to one of the first isolation region; and
the back-side interconnect is in contact with the back-gate extension.

17. The apparatus of claim 1 wherein the first BOX layer has a thickness between 5 nm and 2000 nm, and the second BOX layer has a thickness between 5 nm and 2000 nm.

18. The apparatus of claim 1 wherein the first BOX layer has a thickness between 200 nm and 400 nm, and the second BOX layer has a thickness between 200 nm and 400 nm.

19. The apparatus of claim 1 wherein the first epitaxial layer has a thickness between 100 Å and 2 μm, and the second silicon epitaxial layer has a thickness between 100 Å and 2 μm.

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Patent History

Patent number: 10381289
Type: Grant
Filed: Jul 18, 2017
Date of Patent: Aug 13, 2019
Patent Publication Number: 20180019184
Assignee: Qorvo US, Inc. (Greensboro, NC)
Inventors: Julio C. Costa (Oak Ridge, NC), George Maxim (Saratoga, CA), Dirk Robert Walter Leipold (San Jose, CA), Baker Scott (San Jose, CA)
Primary Examiner: George R Fourson, III
Application Number: 15/652,826

Classifications

Current U.S. Class: Short Channel Insulated Gate Field Effect Transistor (257/327)
International Classification: H01L 23/373 (20060101); H01L 21/8234 (20060101); H01L 29/423 (20060101); H01L 23/535 (20060101); H01L 29/06 (20060101); H01L 29/786 (20060101); H01L 23/31 (20060101); H01L 23/498 (20060101); H01L 23/00 (20060101); H01L 21/762 (20060101);