finFET Device
A finFET, a method of fabricating the finFET and a design structure of the finFET. The method includes: forming a silicon fin on a top surface of a silicon substrate; forming a gate dielectric on opposite sidewalls of the fin; forming a gate electrode over a channel region of the fin, the gate electrode in direct physical contact with the gate dielectric layer on the opposite sidewalls of the fin; forming a first source/drain in the fin on a first side of the channel region and forming a second source/drain in the fin on a second side of the channel region; removing a portion of the substrate from under at least a portion of the first and second source/drains to create a void; and filling the void with a dielectric material. The finFET includes a body contact between the silicon body of the finFET and the substrate.
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This Application is a continuation-in-part and claims priority of copending U.S. patent application Ser. No. 11/427,486 filed on Jun. 29, 2006.
FIELD OF THE INVENTIONThe present invention relates to the field of semiconductor devices; more specifically, it relates to finFETs, methods of fabricating finFETs and design structures for finFETs.
BACKGROUND OF THE INVENTIONFinFET (fin field-effect-transistor) is an emerging technology, which allows smaller and higher performance devices. FinFET structures comprise narrow isolated bars of silicon (fins) with a gate(s) on the sides of the fin. Prior art finFET structures are formed on silicon-on-insulator (SOI) substrates. However, finFETs fabricated on SOI substrates suffer from floating body effects. The floating body of a finFET on an SOI substrate stores charge, which is a function of the history of the device. As such, floating body finFETs experience threshold voltages which are difficult to anticipate and control, and which vary in time. The body charge storage effects result in dynamic sub-Vt leakage and Vt mismatch among geometrically identical adjacent devices. FinFETs fabricated on bulk silicon substrates do not experience floating body effects, but they do experience greatly increased source/drain to substrate capacitance. Increased source-drain to substrate capacitance is a parasitic effect, which degrades performance (speed).
Therefore, there is a need for finFET devices and methods of fabricating finFET devices without floating body effects and with reduced parasitic capacitance.
SUMMARY OF THE INVENTIONA first aspect of the present invention is a structure comprising: a finFET having a silicon body formed on a bulk silicon substrate; a body contact between the silicon body and the substrate; and first and second source/drains formed in the silicon body and insulated from the substrate by a dielectric layer under the fins.
A second aspect of the present invention is a structure, comprising: a single crystal silicon fin extending in a first direction parallel to a top surface of a bulk silicon substrate, the fin having a channel region between first and a second source/drains; an electrically conductive gate electrode extending in a second direction parallel to the top surface of the substrate and crossing over the channel region, the second direction different from the first direction; a gate dielectric between the gate electrode and the fin; at least a portion of the channel region of the fin in direct physical and electrical contact with the substrate; and a dielectric layer between at least a portion of the first source/drain and the substrate and between at least a portion of the second source/drain and the substrate.
A third aspect of the present invention is a method, comprising: forming a silicon fin on a top surface of a silicon substrate; forming a gate dielectric on opposite sidewalls of the fin; forming a gate electrode over a channel region of the fin, the gate electrode in direct physical contact with the gate dielectric layer on the opposite sidewalls of the fin; forming a first source/drain in the fin on a first side of the channel region and forming a second source/drain in the fin on a second side of the channel region; removing a portion of the substrate from under at least a portion of the first and second source/drains to create a void; and filling the void with a dielectric material.
BRIEF DESCRIPTION OF DRAWINGSThe features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:
In one example, pad oxide layer 105 is formed by thermal oxidation of substrate 100 and between about 5 nm and about 20 nm thick. In one example, pad silicon nitride layer 110 is formed by chemical-vapor-deposition (CVD) and is between about 50 nm and about 500 nm thick. In one example, STI 115 comprises a CVD oxide such as tetraethoxysilane (TEOS) or high-density-plasma (HDP) oxide. In one example, liner 120 comprises less than 50 nm of silicon oxide, silicon nitride or a dual layer of silicon oxide under silicon nitride. In one example, STI 115 is between about 50 nm and about 500 nm thick. Pad silicon nitride layer 110 is then stripped selective to oxide and STI 115 is planarized to be approximately flush with the top surface of pad oxide layer 105.
In
In
In
In
In
Next a gate 155 is formed crossing over fin 140 and a capping layer 160 formed on the top (but not the sidewalls of the gate (see
performing a blanket CVD deposition of silicon nitride to form a blanket of layer first protective layer 165;
(2) performing a blanket deposition of a CVD oxide (as described supra) to form a blanket layer of second protective layer 170 over the blanket of layer first protective layer 165;
(3) performing a CMP of the CVD oxide to expose capping layer 160;
(4) performing a RIE recess etch to recess the CVD oxide below the top surface of capping layer 160;
(5) performing a blanket CVD silicon nitride deposition followed by a spacer RIE to form spacers 175; and
(6) performing a RIE to remove all CVD oxide not protected by spacers 175.
Contacts (not shown, but well known in the art) may be formed to the finFET by forming contact via holes through dielectric 205 and capping layers 145A and 160 to source-drains 180 and gate 155, filling the via holes with metal (e.g. barrier liner and tungsten) and performing a CMP. Next, standard processing including formation of levels of wiring and intervening dielectric layers are formed through completion of an integrated circuit chip containing finFET devices according to embodiments of the present invention.
Design process 310 may include using a variety of inputs; for example, inputs from library elements 330 which may house a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing technology (e.g., different technology nodes, 32 nm, 45 nm, 30 nm, etc.), design specifications 340, characterization data 350, verification data 360, design rules 370, and test data files 385 (which may include test patterns and other testing information). Design process 310 may further include, for example, standard circuit design processes such as timing analysis, verification, design rule checking, place and route operations, etc. One of ordinary skill in the art of integrated circuit design can appreciate the extent of possible electronic design automation tools and applications used in design process 310 without deviating from the scope and spirit of the invention. The design structure of the invention is not limited to any specific design flow.
Ultimately, design process 310 preferably translates the structure illustrated in
Thus, the embodiments of the present invention provide finFET, a method of fabricating finFET and a design structure of a finFET without floating body effects and with reduced parasitic capacitance.
The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not limited to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.
Claims
1. A design structure embodied in a machine readable medium used in a design process, the design structure comprising:
- a structure comprising: a finFET having a semiconductor body formed on a substrate; a body contact between said body and said substrate; and first and second source/drains formed in said body and insulated from said substrate by a dielectric layer under said fins.
2. The design structure of claim 1, wherein said body comprises single-crystal silicon or polysilicon and said substrate comprises single-crystal silicon.
3. The design structure of claim 1, wherein said body comprises an epitaxial layer on said substrate.
4. The design structure of claim 1, wherein said dielectric layer extends below a top surface of said substrate into said substrate.
5. The design structure of claim 1, wherein said body contact comprises a pedestal of said substrate contacting a channel region of said finFET, said channel region between said first and second source/drains and under a gate electrode of said finFET.
6. The design structure of claim 1, wherein the design structure comprises a netlist, which describes the circuit.
7. The design structure of claim 1, wherein the design structure resides on a GDS storage medium.
8. The design structure of claim 1, wherein the design structure includes at least one of test data files, characterization data, verification data, or design specifications.
9. A design structure embodied in a machine readable medium used in a design process, the design structure comprising:
- a structure comprising: a semiconductor fin extending in a first direction parallel to a top surface of a substrate, said fin having a channel region between first and a second source/drains; an electrically conductive gate electrode extending in a second direction parallel to said top surface of said substrate and crossing over said channel region, said second direction different from said first direction; a gate dielectric between said gate electrode and said fin; at least a portion of said channel region of said fin in direct physical and electrical contact with said substrate; and a dielectric layer and between at least a portion of said first source/drain and said substrate and between at least a portion of said second source/drain and said substrate.
10. The design structure of claim 9, wherein said dielectric layer extends under a portion of said channel region.
11. The design structure of claim 9, wherein said gate dielectric is formed on opposite sides of said fin and said gate electrode is in direct physical contact with said gate dielectric on said opposite sides of said fin and passes over a top surface of said fin.
12. The design structure of claim 9, further including voids in said dielectric layer.
13. The design structure of claim 9, wherein said dielectric layer extends below said top surface of said substrate into said substrate.
14. The design structure of claim 9, wherein said dielectric layer extends above a bottom surface of said fin into said fin,
15. The design structure of claim 9, wherein a bottom surface of said fin is in direct physical and electrical contact with said top surface of said substrate.
16. The design structure of claim 9, wherein the design structure comprises a netlist, which describes the circuit.
17. The design structure of claim 9, wherein the design structure resides on a GDS storage medium.
18. The design structure of claim 9, wherein the design structure includes at least one of test data files, characterization data, verification data, or design specifications.
Type: Application
Filed: Oct 24, 2007
Publication Date: Feb 21, 2008
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION (Armonk, NY)
Inventors: Roger Booth (Wappingers Falls, NY), William Hovis (Rochester, MN), Jack Mandelman (Flat Rock, NC)
Application Number: 11/923,121
International Classification: H01L 29/94 (20060101);