Metal-insulator-semiconductor (e.g., Mos Capacitor) (epo) Patents (Class 257/E29.345)
  • Patent number: 10320211
    Abstract: In regard to a hearing aid and a hearing aid charging system, frequent replacement of a battery is avoided even if power consumption is large, and the structure is simplified and waterproofness is improved. A Hearing aid includes a secondary battery having a nominal voltage higher than a nominal voltage of an air battery, a driving component driven by power supplied from the secondary battery, and a transformation unit configured to output the charging power of the secondary battery at a voltage suitable for driving the driving component.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: June 11, 2019
    Assignee: NITTO DENKO CORPORATION
    Inventors: Takezo Hatanaka, Hisashi Tsuda
  • Patent number: 10228402
    Abstract: A hearing aid (200), adapted for detection of congestion of a sound output. The invention also relates to a method of detection of congestion of a sound output.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: March 12, 2019
    Assignee: Widex A/S
    Inventors: Klaus Krogsgaard, Jorgen Cederberg
  • Patent number: 9401677
    Abstract: A novel and useful LC-tank digitally controlled oscillator (DCO) incorporating a split transformer configuration. The LC-tank oscillator exhibits a significant reduction in area such that it is comparable in size to conventional ring oscillators (ROs) while still retaining its salient features of excellent phase noise and low sensitivity to supply variations. The oscillator incorporates an ultra-compact split transformer topology that is less susceptible to common-mode electromagnetic interference than regular high-Q LC tanks which is highly desirable in SoC environments. The oscillator, together with a novel dc-coupled buffer, can be incorporated within a wide range of circuit applications, including clock generators and an all-digital phase-locked loop (ADPLL) intended for wireline applications.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: July 26, 2016
    Assignee: Short Circuit Technologies LLC
    Inventors: Augusto Ronchini Ximenes, Robert Bogdan Staszewski
  • Patent number: 8957403
    Abstract: Select devices including an open volume that functions as a high bandgap material having a low dielectric constant are disclosed. The open volume may provide a more nonlinear, asymmetric I-V curve and enhanced rectifying behavior in the select devices. The select devices may comprise, for example, a metal-insulator-insulator-metal (MIIM) diode. Various methods may be used to form select devices and memory systems including such select devices. Memory devices and electronic systems include such select devices.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: February 17, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Bhaskar Srinivasan, Gurtej S. Sandhu
  • Patent number: 8946719
    Abstract: In at least one embodiment, a TFT includes: a first capacitor formed of a first capacitor electrode connected to a source electrode and a second capacitor electrode; a second capacitor formed of a third capacitor electrode and a fourth capacitor electrode; a first lead-out line; a second lead-out line connected to a gate electrode; a third lead-out line; a fourth lead-out line; a first interconnection; and a second interconnection. This realizes a TFT which can be easily saved from being a defective product even if leakage occurs in a capacitor connected to a TFT body section.
    Type: Grant
    Filed: January 27, 2009
    Date of Patent: February 3, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Shinya Tanaka, Tetsuo Kikuchi, Hajime Imai, Hideki Kitagawa, Yoshiharu Kataoka
  • Patent number: 8907391
    Abstract: A semiconductor device includes a substrate including an active region having an isolated shape and a field region. A gate insulation layer is provided on an upper surface of the active region of the substrate. A gate electrode is provided on the gate insulation layer and spaced apart from the boundary of the active region to cover the middle portion of the active region. An impurity region is provided under a surface of the active region that is exposed by the gate electrode.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: December 9, 2014
    Assignee: SAMSUNG Electronics Co., Ltd.
    Inventors: Jung-Soo Nam, Joon-Suk Oh, Hye-Young Park
  • Patent number: 8884349
    Abstract: A semiconductor device includes, a semiconductor substrate, a first transistor of a first conductivity type, a second transistor of a second conductivity type, a first capacitor, and a first wiring. The semiconductor substrate includes first, second, and third regions. The third region is sandwiched between the first and second regions. The first transistor of the first conductivity type is disposed in the first region. The second transistor of the second conductivity type is disposed in the second region. The first capacitor is disposed in the third region. The first wiring electrically couples one of main electrodes of the first transistor and one of main electrodes of the second transistor. The first wiring passes above the first capacitor.
    Type: Grant
    Filed: April 11, 2011
    Date of Patent: November 11, 2014
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Yuki Miura
  • Patent number: 8878340
    Abstract: Devices or systems that include a composite thermal capacitor disposed in thermal communication with a hot spot of the device, methods of dissipating thermal energy in a device or system, and the like, are provided herein. In particular, the device includes a composite thermal capacitor including a phase change material and a high thermal conductivity material in thermal communication with the phase change material. The high thermal conductivity material is also in thermal communication with an active regeneration cooling device. The heat from the composite thermal capacitor is dissipated by the active regeneration cooling device.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: November 4, 2014
    Assignee: Georgia Tech Research Corporation
    Inventors: Andrei G. Fedorov, Craig Green, Yogendra Joshi
  • Patent number: 8841717
    Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate having a first groove; and a plurality of first pillars over the substrate. The plurality of first pillars is disposed beside the first groove. A first insulator is disposed in the first groove. A bit contact is disposed in the first groove and over the first insulator. The bit contact is coupled to side surfaces of the plurality of first pillars.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: September 23, 2014
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Noriaki Mikasa
  • Patent number: 8829584
    Abstract: A semiconductor device with a dynamic gate drain capacitance. One embodiment provides a semiconductor device. The device includes a semiconductor substrate, a field effect transistor structure including a source region, a first body region, a drain region, a gate electrode structure and a gate insulating layer. The gate insulating layer is arranged between the gate electrode structure and the body region. The gate electrode structure and the drain region partially form a capacitor structure including a gate-drain capacitance configured to dynamically change with varying reverse voltages applied between the source and drain regions. The gate-drain capacitance includes at least one local maximum at a given threshold or a plateau-like course at given reverse voltage.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: September 9, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Anton Mauder, Hans-Joachim Schulze, Carolin Tolksdorf, Winfried Kaindl, Armin Willmeroth
  • Patent number: 8829647
    Abstract: A first electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the first electrode layer contains a conductive metal oxide formed using a high temperature, low pressure ALD process. The high temperature ALD process results in a layer with enhanced crystallinity, higher density, reduced shrinkage, and lower carbon contamination. The high temperature ALD process can be used for either or both the bottom electrode and the top electrode layers.
    Type: Grant
    Filed: January 9, 2013
    Date of Patent: September 9, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Hanhong Chen, Edward Haywood, Sandra Malhotra, Hiroyuki Ode
  • Patent number: 8786002
    Abstract: In terms of achieving a reduction in the cost of an antenna switch, there is provided a technology capable of minimizing harmonic distortion generated in the antenna switch even when the antenna switch is particularly formed of field effect transistors formed over a silicon substrate. Between the source region and the drain region of each of a plurality of MISFETs coupled in series, a distortion compensating capacitance circuit is coupled which has a voltage dependency such that, in either of the cases where a positive voltage is applied to the drain region based on the potential of the source region and where a negative voltage is applied to the drain region based on the potential of the source region, the capacitance decreases to a value smaller than that in a state where the potential of the source region and the potential of the drain region are at the same level.
    Type: Grant
    Filed: June 2, 2011
    Date of Patent: July 22, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Masao Kondo, Masatoshi Morikawa, Satoshi Goto
  • Patent number: 8741730
    Abstract: A method of forming a field effect transistor (FET) capacitor includes forming a channel region; forming a gate stack over the channel region; forming a first extension region on a first side of the gate stack, the first extension region being formed by implanting a first doping material at a first angle such that a shadow region exists on a second side of the gate stack; and forming a second extension region on the second side of the gate stack, the second extension region being formed by implanting a second doping material at a second angle such that a shadow region exists on the first side of the gate stack.
    Type: Grant
    Filed: August 2, 2012
    Date of Patent: June 3, 2014
    Assignee: International Business Machines Corporation
    Inventors: Leland Chang, Brian L. Ji, Chung-Hsun Lin, Jeffrey W. Sleight
  • Patent number: 8703548
    Abstract: A method of manufacturing a semiconductor device includes providing a substrate having a first conductive layer disposed on a top surface of the substrate. A high resistivity layer is formed over the substrate and the first conductive layer. A dielectric layer is deposited over the substrate, first conductive layer and high resistivity layer. A portion of the dielectric layer, high resistivity layer, and first conductive layer forms a capacitor stack. A first passivation layer is formed over the dielectric layer. A second conductive layer is formed over the capacitor stack and a portion of the first passivation layer. A first opening is etched in the dielectric layer to expose a surface of the high resistivity layer. A third and fourth conductive layer is deposited over the first opening in the dielectric layer and a portion of the first passivation layer.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: April 22, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Robert C. Frye
  • Patent number: 8698280
    Abstract: In the semiconductor device composing MOS transistor on which impurities are added from the surface of a P-type substrate, the region of immediate below a gate layer is the P-type substrate on which the impurities are not added, and first and second MOS devices, having an N-type diffusion layer are provided on the surface region of the P-type substrate circumscribing the gate layer. The gate layer of the first MOS device, and the N-type diffusion layer of the second MOS device are connected, and the N-type diffusion layer of the first MOS device and the gate layer of the second MOS device are connected, and thereby a first capacitive element is composed.
    Type: Grant
    Filed: December 8, 2011
    Date of Patent: April 15, 2014
    Assignee: Spansion LLC
    Inventor: Koji Shimbayashi
  • Publication number: 20140091845
    Abstract: III-N high voltage MOS capacitors and System on Chip (SoC) solutions integrating at least one III-N MOS capacitor capable of high breakdown voltages (BV) to implement high voltage and/or high power circuits. Breakdown voltages over 4V may be achieved avoiding any need to series couple capacitors in an RFIC and/or PMIC. In embodiments, depletion mode III-N capacitors including a GaN layer in which a two dimensional electron gas (2DEG) is formed at threshold voltages below 0V are monolithically integrated with group IV transistor architectures, such as planar and non-planar silicon CMOS transistor technologies. In embodiments, silicon substrates are etched to provide a (111) epitaxial growth surface over which a GaN layer and III-N barrier layer are formed. In embodiments, a high-K dielectric layer is deposited, and capacitor terminal contacts are made to the 2DEG and over the dielectric layer.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Inventors: Han Wui THEN, Sansaptak DASGUPTA, Gerhard SCHROM, Valluri R. RAO, Robert S. CHAU
  • Patent number: 8686496
    Abstract: A semiconductor device includes a semiconductor substrate having a first gate groove having first and second side walls facing to each other. A first gate insulating film covers the first and second side walls. A first gate electrode is disposed on the first gate insulating film and in a lower portion of the first gate groove. A first burying insulating film buries the first gate groove and covers the first gate electrode. A first diffusion region is adjacent to a first upper portion of the first gate insulating film. The first upper portion is positioned on an upper portion of the first side wall of the first gate groove. A second diffusion region is in contact with an upper portion of the second side wall of the first gate groove.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: April 1, 2014
    Inventor: Noriaki Mikasa
  • Patent number: 8669605
    Abstract: A semiconductor device comprises a circuit cell and a basic end cell. The circuit cell includes a plurality of elements aligned in a first direction, and the basic end cell is arranged adjacent to the circuit cell in the first direction and has a compensation capacitor capable of being connected to a supply voltage of the circuit cell. In the semiconductor device, a diffusion layer forming the compensation capacitor extends along the first direction in a predetermined region of the circuit cell.
    Type: Grant
    Filed: March 11, 2010
    Date of Patent: March 11, 2014
    Inventor: Yoshiaki Shimizu
  • Patent number: 8642422
    Abstract: In the semiconductor device composing MOS transistor on which impurities are added from the surface of a P-type substrate, the region of immediate below a gate, layer is the P-type substrate on which the impurities are not added, and first and second MOS devices, having an N-type diffusion layer are provided on the surface region of the P-type substrate circumscribing the gate layer. The gate layer of the first MOS device, and the N-type diffusion layer of the second MOS device are connected, and the N-type diffusion layer of the first MOS device and the gate layer of the second MOS device are connected, and thereby a first capacitive element is composed.
    Type: Grant
    Filed: December 8, 2011
    Date of Patent: February 4, 2014
    Assignee: Spansion LLC
    Inventor: Koji Shimbayashi
  • Patent number: 8637958
    Abstract: A structure and method for forming isolation and a buried plate for a trench capacitor is disclosed. Embodiments of the structure comprise an epitaxial layer serving as the buried plate, and a bounded deep trench isolation area serving to isolate one or more deep trench structures. Embodiments of the method comprise angular implanting of the deep trench isolation area to form a P region at the base of the deep trench isolation area that serves as an anti-punch through implant.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: January 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Abhishek Dube, Subramanian S. Iyer, Babar Ali Khan, Oh-jung Kwon, Junedong Lee, Paul C. Parries, Chengwen Pei, Gerd Pfeiffer, Ravi Todi, Geng Wang
  • Patent number: 8633533
    Abstract: A capacitor and a method of manufacturing the same are provided. A dummy capacitor group is formed in the peripheral circuit area and includes a dummy storage node contact unit, a dielectric, and a dummy plate electrode. A metal oxide semiconductor (MOS) capacitor is formed in the peripheral circuit area and connected to the dummy capacitor group in parallel. Capacitance of the dummy capacitor group may be greater than that of the MOS capacitor.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: January 21, 2014
    Assignee: SK Hynix Inc.
    Inventor: Jong Su Kim
  • Patent number: 8633535
    Abstract: According to one embodiment, a nonvolatile semiconductor memory includes control gates provided in an array form, the control gates passing through the first semiconductor layer, data recording layers between the first semiconductor layer and the control gates, two first conductive-type diffusion layers at two ends in the first direction of the first semiconductor layer, two second conductive-type diffusion layers at two ends in the second direction of the first semiconductor layer, select gate lines extending in the first direction on the first semiconductor layer, and word lines extending in the second direction on the select gate lines. The select gate lines function as select gates shared by select transistors connected between the control gates and the word lines arranged in the first direction. Each of the word lines is commonly connected to the control gates arranged in the second direction.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: January 21, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kouji Matsuo, Toshiyuki Enda, Nobutoshi Aoki, Toshihiko Iinuma
  • Patent number: 8629506
    Abstract: A CMOS structure and a method for fabricating the CMOS structure include within a semiconductor substrate a first gate located over a first active region of a first polarity and a second gate located over a second active region of a second polarity different than the first polarity. The first active region and the second active region are separated by an isolation region. The first gate and the second gate are co-linear, with facing endwalls that terminate over the isolation region. The facing endwalls do not have a spacer located or formed adjacent or adjoining thereto, although sidewalls of the first gate and the second gate do. The CMOS structure may be fabricated using a sequential replacement gate method.
    Type: Grant
    Filed: March 19, 2009
    Date of Patent: January 14, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Haining S. Yang
  • Patent number: 8614472
    Abstract: An integrated circuit metal oxide metal (MOM) variable capacitor includes a first plate; one or more pairs of second plates positioned on both sides of the first plate; one or more pairs of control plates positioned on both sides of the first plate and positioned between the pairs of second plates; and a switch coupled to each control plate and a fixed potential.
    Type: Grant
    Filed: August 19, 2011
    Date of Patent: December 24, 2013
    Assignee: Integrated Device Technology, Inc.
    Inventors: Syed S. Islam, Mansour Keramat
  • Patent number: 8604587
    Abstract: An on-chip decoupling capacitor (106) and method of fabrication. The decoupling capacitor (106) is integrated at the top metal interconnect level (104) and includes surface protection cladding (109) for the copper metal (104b) of the top metal interconnect.
    Type: Grant
    Filed: January 19, 2010
    Date of Patent: December 10, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Edmund Burke, Satyavolu Srinivas Papa Rao, Timothy Alan Rost
  • Publication number: 20130320421
    Abstract: A MOS capacitor includes a substrate, a p-type MOS (pMOS) transistor positioned on the substrate, and an n-type MOS (nMOS) transistor positioned on the substrate. More important, the pMOS transistor and the nMOS transistor are electrically connected in parallel. The MOS transistor further includes a deep n-well that encompassing the pMOS transistor and the nMOS transistor.
    Type: Application
    Filed: May 29, 2012
    Publication date: December 5, 2013
    Inventors: Kai-Ling Chiu, Chao-Sheng Cheng, Chih-Yu Tseng, Yu-Jen Liu
  • Patent number: 8592897
    Abstract: A method for forming an opening within a semiconductor material comprises forming a neck portion, a rounded portion below the neck portion and, in some embodiments, a protruding portion below the rounded portion. This opening may be filled with a conductor, a dielectric, or both. Embodiments to form a transistor gate, shallow trench isolation, and an isolation material separating a transistor source and drain are disclosed. Device structures formed by the method are also described.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: November 26, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Venkatesan Anathan
  • Patent number: 8541770
    Abstract: Select devices including an open volume that functions as a high bandgap material having a low dielectric constant are disclosed. The open volume may provide a more nonlinear, asymmetric I-V curve and enhanced rectifying behavior in the select devices. The select devices may comprise, for example, a metal-insulator-insulator-metal (MIIM) diode. Various methods may be used to form select devices and memory systems including such select devices. Memory devices and electronic systems include such select devices.
    Type: Grant
    Filed: August 16, 2011
    Date of Patent: September 24, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Bhaskar Srinivasan, Gurtej S. Sandhu
  • Patent number: 8541868
    Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. A metal oxide second electrode layer is formed above the dielectric layer. The metal oxide second electrode layer has a crystal structure that is compatible with the crystal structure of the dielectric layer. Optionally, a second electrode bulk layer is formed above the metal oxide second electrode layer.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: September 24, 2013
    Assignees: Intermolecular, Inc., Elpida Memory, Inc.
    Inventors: Sandra G. Malhotra, Hanhong Chen, Wim Y. Deweerd, Hiroyuki Ode
  • Patent number: 8535999
    Abstract: Semiconductor substrate with a deformed gate region and a method for the fabrication thereof. The semiconductor substrate has improved device performance compared to devices without a deformed gate region and decreased dopant loss compared to devices with deformed source/drain regions.
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: September 17, 2013
    Assignee: International Business Machines Corporation
    Inventors: Lahir Adam, Bruce B. Doris, Sanjay Mehta, Zhengmao Zhu
  • Patent number: 8536633
    Abstract: The present invention relates to a metal-oxide-semiconductor field-effect transistor (MOSFET) with electrostatic-discharge (ESD) protection and a voltage-stabilizing capacitor, and a method for manufacturing the same and is applied to a chip, including a P-type substrate, a conductor layer, a first N-type doping region, a second N-type doping region, and an N-type well. The conductor layer is coupled to the ground; the first N-type doping region is coupled to the power supply; the second N-type doping region is coupled to a VDD pad (power-supply pad). Thereby, when the chip is not installed or not operating, the MOSFET can be used for ESD protection. When the chip is operating, the conductor layer, the first N-type doping region, the second N-type doing region, and the N-type well form a gate capacitor as a voltage-stabilizing capacitor between the power supply and the ground. Hence, the objective of fully utilization is achieved. In addition, the chip size is saved and thus the cost thereof is reduced.
    Type: Grant
    Filed: January 3, 2008
    Date of Patent: September 17, 2013
    Assignee: Realtek Semiconductor Corp.
    Inventor: Yi-Lin Chen
  • Publication number: 20130222045
    Abstract: An electronic component is described which includes a first transistor encased in a first package, the first transistor being mounted over a first conductive portion of the first package, and a second transistor encased in a second package, the second transistor being mounted over a second conductive portion of the second package. The component further includes a substrate comprising an insulating layer between a first metal layer and a second metal layer. The first package is on one side of the substrate with the first conductive portion being electrically connected to the first metal layer, and the second package is on another side of the substrate with the second conductive portion being electrically connected to the second metal layer. The first package is opposite the second package, with at least 50% of a first area of the first conductive portion being opposite a second area of the second conductive portion.
    Type: Application
    Filed: February 24, 2012
    Publication date: August 29, 2013
    Applicant: TRANSPHORM INC.
    Inventor: Yifeng Wu
  • Publication number: 20130193499
    Abstract: A device comprises a semiconductor substrate having first and second implant regions of a first dopant type. A gate insulating layer and a gate electrode are provided above a resistor region between the first and second implant regions. A first dielectric layer is on the first implant region. A contact structure is provided, including a first contact portion conductively contacting the gate electrode, at least part of the first contact portion directly on the gate electrode. A second contact portion directly contacts the first contact portion and is formed directly on the first dielectric layer. A third contact portion is formed on the second implant region.
    Type: Application
    Filed: January 31, 2012
    Publication date: August 1, 2013
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Chung-Hui CHEN
  • Publication number: 20130181269
    Abstract: A device comprises a semiconductor substrate having first and second implant regions and an electrode above and between the first and second implant regions of a first dopant type. A contact structure is in direct contact with the first and second implant regions and the electrode. A third implant region has a second dopant type different from the first dopant type. A bulk contact is provided on the third implant.
    Type: Application
    Filed: January 13, 2012
    Publication date: July 18, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Chung-Hui CHEN
  • Publication number: 20130175590
    Abstract: A semiconductor device includes: an element isolation region formed in a substrate that defines an active region, a conductive layer formed on the active region, a first insulating film formed between the active region and the conductive layer and having a first thickness, and a second insulating film formed between the active region and the conductive layer and spans at least part of a boundary between the active region and the element isolation region and having a second thickness which is greater than the first thickness.
    Type: Application
    Filed: September 13, 2012
    Publication date: July 11, 2013
    Inventor: Myoung-Soo Kim
  • Publication number: 20130161711
    Abstract: A semiconductor device includes a substrate including an active region having an isolated shape and a field region. A gate insulation layer is provided on an upper surface of the active region of the substrate. A gate electrode is provided on the gate insulation layer and spaced apart from the boundary of the active region to cover the middle portion of the active region. An impurity region is provided under a surface of the active region that is exposed by the gate electrode.
    Type: Application
    Filed: September 13, 2012
    Publication date: June 27, 2013
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jung-Soo NAM, Joon-Suk Oh, Hye-Young Park
  • Patent number: 8471362
    Abstract: A three-dimensional (3D) semiconductor device including a plurality of stacked layers and a through-silicon via (TSV) electrically connecting the plurality of layers, in which in signal transmission among the plurality of layers, the TSV transmits a signal that swings in a range from an offset voltage that is higher than a ground voltage to a power voltage, thereby minimizing an influence of a metal-oxide-semiconductor (MOS) capacitance of TSV.
    Type: Grant
    Filed: April 5, 2011
    Date of Patent: June 25, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jong-joo Lee
  • Patent number: 8472251
    Abstract: A single polycrystalline silicon floating gate nonvolatile memory cell has a MOS capacitor and a storage MOS transistor fabricated with dimensions that allow fabrication using current low voltage logic integrated circuit process. The MOS capacitor has a first plate connected to a gate of the storage MOS transistor to form a floating gate node. The physical size of the MOS capacitor is relatively large (approximately 10 time greater) when compared to a physical size of the storage MOS transistor to establish a large coupling ratio (greater than 80%) between the second plate of the MOS capacitor and the floating gate node. When a voltage is applied to the second plate of the MOS capacitor and a voltage applied to the source region or drain region of the MOS transistor establishes a voltage field within the gate oxide of the MOS transistor such that Fowler-Nordheim edge tunnel is initiated.
    Type: Grant
    Filed: February 10, 2009
    Date of Patent: June 25, 2013
    Assignee: Aplus Flash Technology, Inc.
    Inventors: Peter Wung Lee, Fu-Chang Hsu
  • Patent number: 8471363
    Abstract: A semiconductor device includes a substrate, a first single conductor, a single insulator, and a second single conductor. The substrate includes first and second regions located adjacent to each other. The first region has blind holes, each of which has an opening on a front surface of the substrate. The second region has a through hole penetrating the substrate. A width of each blind hole is less than a width of the through hole. The first single conductor is formed on the front surface of the substrate in such a manner that an inner surface of each blind hole and an inner surface of the through hole are covered with the first single conductor. The single insulator is formed on the first single conductor. The second single conductor is formed on the single insulator and electrically insulated form the first single conductor.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: June 25, 2013
    Assignee: Denso Corporation
    Inventors: Kazushi Asami, Yasuhiro Kitamura
  • Publication number: 20130146958
    Abstract: A method for fabricating a semiconductor device includes: etching a semiconductor substrate and forming a plurality of bodies separated from one another by a plurality of trenches; forming a protective layer with open parts to expose both sidewalls of each of the bodies; forming buried bit lines in the bodies by silicidizing exposed portions of the bodies through the open parts; and forming a dielectric layer to gap-fill the trenches and define air gaps between adjacent buried bit lines.
    Type: Application
    Filed: April 13, 2012
    Publication date: June 13, 2013
    Inventors: You-Song Kim, Jin-Ki Jung
  • Publication number: 20130126953
    Abstract: Methods and apparatus for polysilicon MOS capacitors in a replacement gate process. A method includes disposing a gate dielectric layer over a semiconductor substrate; disposing a polysilicon gate layer over the dielectric layer; patterning the gate dielectric layer and the polysilicon gate layer to form a plurality of polysilicon gates spaced by at least a minimum polysilicon to polysilicon pitch; defining a polysilicon resistor region containing at least one of the polysilicon gates and not containing at least one other of the polysilicon gates, which form dummy gates; depositing a mask layer over an inter-level dielectric layer; patterning the mask layer to expose the dummy gates; removing the dummy gates and the gate dielectric layer underneath the dummy gates to leave trenches in the inter-level dielectric layer; and forming high-k metal gate devices in the trenches in the inter-level dielectric layer. An apparatus produced by the method is disclosed.
    Type: Application
    Filed: November 22, 2011
    Publication date: May 23, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pai-Chieh Wang, Tung-Heng Hsieh, Yimin Huang, Chung-Hui Chen
  • Publication number: 20130126955
    Abstract: Methods and apparatus for hybrid MOS capacitors in replacement gate process. A method is disclosed including patterning a gate dielectric layer and a polysilicon gate layer to form a polysilicon gate region over a substrate; forming an inter-level dielectric layer over the substrate and surrounding the polysilicon gate region; defining polysilicon resistor regions each containing at least one portion of the polysilicon gate region and not containing at least one other portion of the polysilicon gate region, forming dummy gate regions removing the dummy gate regions and the gate dielectric layer underneath the dummy gate regions to leave trenches; and forming high-k metal gate devices in the trenches. A capacitor region including a high-k metal gate and a polysilicon gate next to the high-k metal gate is disclosed. Additional hybrid capacitor apparatuses are disclosed.
    Type: Application
    Filed: November 22, 2011
    Publication date: May 23, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pai-Chieh Wang, Tung-Heng Hsieh, Yimin Huang
  • Publication number: 20130119449
    Abstract: A seal ring for semiconductor devices is provided with embedded decoupling capacitors. The seal ring peripherally surrounds an integrated circuit chip in a seal ring area. The at least one embedded decoupling capacitor may include MOS capacitors, varactors, MOM capacitors and interdigitized capacitors with multiple capacitor plates coupled together. The opposed capacitor plates are coupled to different potentials and may advantageously be coupled to Vdd and Vss.
    Type: Application
    Filed: November 15, 2011
    Publication date: May 16, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Ji CHEN, Wei Yu MA, Ta-Pen GUO, Hsien-Wei CHEN, Hao-Yi TSAI
  • Publication number: 20130107630
    Abstract: Vertically fabricated non-volatile memory devices having capacitive coupling between a drain region and a floating gate. A two terminal programmable non-volatile device includes a floating gate disposed vertically about a substrate, wherein the floating gate comprises a first side, a second side, and a bottom portion. A source region is coupled to a first terminal and formed adjacent to the first side of the floating gate. A drain region is coupled to a second terminal and formed adjacent to the second side of the floating gate. The non-volatile device includes a channel coupling the source region and drain region for programming and erasing operations. The drain region is capacitively coupled to the floating gate.
    Type: Application
    Filed: October 28, 2011
    Publication date: May 2, 2013
    Applicant: INVENSAS CORPORATION
    Inventors: David Edward Fisch, Michael Curtis Parris
  • Patent number: 8431982
    Abstract: A semiconductor device includes capacitors connected in parallel. Electrode active portions and a discharge active portion are defined on a semiconductor substrate, and capping electrodes are disposed respectively on the electrode active portions. A capacitor-dielectric layer is disposed between each of the capping electrodes and each of the electrode active portions that overlap each other. A counter doped region is disposed in the discharge active portion. A lower interlayer dielectric covers the entire surface of the semiconductor substrate. Electrode contact plugs respectively contact the capping electrodes through the lower interlayer dielectric, and a discharge contact plug contacts the counter doped region through the lower interlayer dielectric. A lower interconnection is disposed on the lower interlayer dielectric and contacts the electrode contact plugs and the discharge contact plug.
    Type: Grant
    Filed: January 19, 2011
    Date of Patent: April 30, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myoungsoo Kim, Yoonkyung Choi, Eun Young Lee, Sungil Jo
  • Patent number: 8426867
    Abstract: A plurality of thin film capacitor parts are provided in respective regions each surrounded by a plurality of gate metal lines (12) and a plurality of data signal lines (11) intersecting perpendicularly to each other on a glass substrate (1), and each of the thin film capacitor parts has a lower electrode (3), a gate insulating film, and an upper electrode (5), which are provided in this order. Adjacent upper electrodes (5) are electrically connected to each other via a corresponding first wire (8), which is positioned above the adjacent upper electrodes (5) and intersects with one of the data signal lines (11). This makes it possible to provide a thin film capacitor, which includes the lower electrodes (3) each having the same thickness in a center portion and an edge portion, and the upper electrodes (5) that are connected to each other by using a corresponding connecting wire with low possibility of disconnection.
    Type: Grant
    Filed: July 2, 2008
    Date of Patent: April 23, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Hiroyuki Moriwaki
  • Publication number: 20130092993
    Abstract: A semiconductor device includes a substrate, an interlayer insulation layer, first transistors, a multilayered interconnect layer, capacitance devices, metal interconnects, and first contacts. Interlayer insulation films are disposed over the substrate. The first transistors are disposed to the substrate and buried in the interlayer insulation layer. The first transistor has at least a gate electrode and a diffusion electrode. A multilayered interconnect layer is disposed over the interlayer insulation film. The capacitance devices are disposed in the multilayered interconnect layer. The metal interconnect is in contact with the upper surface of the gate electrode and buried in the interlayer insulation layer. The first contact is coupled to the diffusion layer of the first transistor and buried in the interlayer insulation layer. The metal interconnect includes a material identical with that of the first contact.
    Type: Application
    Filed: October 16, 2012
    Publication date: April 18, 2013
    Applicant: Renesas Electronics Corporation
    Inventor: Renesas Electronics Corporation
  • Patent number: 8410578
    Abstract: A semiconductor component and methods for manufacturing the semiconductor component that includes a monolithically integrated passive device. In accordance with embodiments, the monolithically integrated passive device includes an inductor formed from damascene structures.
    Type: Grant
    Filed: December 7, 2010
    Date of Patent: April 2, 2013
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Sallie Hose, Peter A. Burke, Li Jiang, Sudhama C. Shastri
  • Patent number: 8410534
    Abstract: Disclosed are integrated circuit structures each having a silicon germanium film incorporated as a local interconnect and/or an electrical contact. These integrated circuit structures provide improved local interconnects between devices and/or increased capacitance to devices without significantly increasing structure surface area or power requirements. Specifically, disclosed are integrated circuit structures that incorporate a silicon germanium film as one or more of the following features: as a local interconnect between devices; as an electrical contact to a device (e.g., a deep trench capacitor, a source/drain region of a transistor, etc.); as both an electrical contact to a deep trench capacitor and a local interconnect between the deep trench capacitor and another device; and as both an electrical contact to a deep trench capacitor and as a local interconnect between the deep trench capacitor and other devices.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: April 2, 2013
    Assignee: International Business Machines Corporation
    Inventor: Steven H. Voldman
  • Publication number: 20130075801
    Abstract: A method for producing a capacitive structure in a semiconductor body includes forming a first trench in a first surface of the semiconductor body, forming a first dielectric layer on sidewalls and the bottom of the first trench, forming a first electrode layer on the first dielectric layer, forming at least one second trench by removing at least one part of the first dielectric layer to form a first gap in the first surface, and by widening the first gap, forming a second dielectric layer on sidewalls and the bottom of the at least one second trench, and forming a second electrode layer on the second dielectric layer.
    Type: Application
    Filed: September 23, 2011
    Publication date: March 28, 2013
    Applicant: Infineon Technologies Austria AG
    Inventors: Hans Weber, Roman Knoefler, Kurt Sorschag