METHOD OF FORMING A MULTILAYER STRUCTURE
Method of forming a multilayer structure by electroetching or electroplating on a substrate. A seed layer is arranged on the substrate and a master electrode is applied thereto. The master electrode has a pattern layer forming multiple electrochemical cells with the substrate. A voltage is applied for etching the seed layer or applying a plating material to the seed layer. A dielectric material (9) is arranged between the structures (8) thus formed. The dielectric layer is planarized for uncovering the structure below and another structure layer is formed on top of the first. Alternatively, the dielectric layer is applied with a thickness two layers and the structure below is accessed by selective etching of the dielectric layer for selectively uncovering the top surface of the structure below. Multiple structure layer may also be formed in one step.
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The present invention relates to an etching and/or plating method for simplifying production of applications involving micro and nano structures in multiple layers. The method is particularly useful for fabrication of PWB (printed wiring boards), PCB (printed circuit boards), MEMS (micro electro mechanical systems), IC (integrated circuit) interconnects, above IC interconnects, sensors, flat panel displays, magnetic and optical storage devices, etc. Different types of structures in conductive polymers, structures in semiconductors, structures in metals, and others are possible to produce using this method. Even 3D-structures in silicon, by using formation of porous silicon, are possible to produce.
BACKGROUND ARTWO 02/103085 relates to an electrochemical pattern replication method, ECPR, and a construction of a conductive electrode for production of applications involving micro and nano structures. An etching or plating pattern, which is defined by a conductive electrode, master electrode, is replicated on an electrically conductive material, a substrate. The master electrode is put in close contact with the substrate and the etching/plating pattern is directly transferred onto the substrate by using a contact etching/plating process. The contact etching/plating process is preformed in local etching/plating cells that are formed in closed or open cavities between the master electrode and the substrate.
Patent application US 2005/0202180 discloses electrochemical fabrication methods for forming single and multilayer mesoscale and microscale structures. In the method, diamond machining (e.g. fly cutting or turning) is used to planarize layers. Moreover, sacrificial and structural materials are described, which are useful in electrochemical fabrication and which can be diamond machined with minimal tool wear (e.g. Ni—P and Cu, Au and Cu, Cu and Sn, Au and Cu, Au and Sn and Au and Sn—Pb, where the first material or materials are the structural materials and the second is the sacrificial material). Methods for reducing tool wear are also described when using diamond machining to planarize structures being electrochemically fabricated using difficult-to-machine materials, e.g. by depositing difficult to machine materials selectively and potentially with little excess plating thickness, and/or pre-machining depositions to within a small increment of desired surface level (e.g. using lapping or a rough cutting operation) and then using diamond fly cutting to complete the process and/or forming structures or portions of structures from thin walled regions of hard-to-machine material as opposed to wide solid regions of structural material.
A master electrode, which may be used in the present invention, is described in Swedish patent application No. 0502539-2 entitled: “Electrode and method of forming the electrode” The content of this patent specification is incorporated herein by reference.
A problem of prior art multilayer methods is the fact that during the planarization step, at least two materials are required to be removed at the same time. The problem is larger if the two materials have different properties, such as if one of the material is hard, such as a metal, and the other material is soft, such as a plastics material, glass material or porous material, for example a dielectricum.
If the planarization takes place by a mechanical polishing action or chemical-mechanical polishing action, several problems may arise. Such polishing action is performed by a plate which moves relative to the material to be planarized, such as by rotation, translation or rolling.
During the initial stage of the planarization, material is removed only at the top or ridges of the material. During this stage, there is a risk that the underlying structure may be damaged, especially if the abrasion speed is high. This risk may be decreased by partly dissolving the material by chemical means.
During the intermediate stage of the planarization, no specific problems arise, but the abrasion is relatively straight forward, as long as only the soft or hard material is encountered.
During a final stage of the planarization, both soft material and hard material may be removed. This may result in that the soft material is removed at a higher rate than the hard material, known as erosion or dishing, resulting in recessions in the soft material between the hard material. The final result may be unsuitable for the following processing.
Another problem with mechanical planarization, it that there is a risk that the plate is not completely parallel with the structure layer formed. A small angular deviation may result in that part of the structure is not uncovered as desired.
A further problem of prior art multilayer methods is the fact that the thickness of the structure layer may be difficult to control.
A still further problem of prior art multilayer methods is the fact that the prior art method requires many process steps, which makes the process cumbersome and expensive.
A yet further problem of prior art multilayer methods is the fact that it cannot fill vias or holes in the structure in an even manner.
Yet another problem is that it may be difficult to achieve a plane final result if the structures are relatively uneven from the start.
Further problems may be gathered from that stated below.
SUMMARY OF THE INVENTIONAn object of the present invention is to provide a method for forming multilayer structures, in which the risk of erosion or dishing has been reduced or even eliminated.
A further object is to provide a method of forming multilayer structures, in which the number of steps may be reduced.
A still further object is to provide a method of forming multilayer structures, in which vias can be filled in a uniform manner.
In an aspect of the invention, there is provided a method of forming a multilayer structure by electroplating on a substrate, comprising: a) arranging an electrically conducting seed layer on at least a part of the substrate or a substrate layer; b) applying a master electrode on said seed layer, said master electrode having an electrically conducting electrode layer, an anode material and an insulating pattern layer for forming at least one electrochemical cell comprising an electrolyte in the area enclosed by said anode material, said insulating pattern layer and said seed layer; wherein said anode material is being in electrical contact with said conducting electrode layer; c) applying a voltage between said conducting electrode layer and said seed layer so that said seed layer forms a cathode for transferring at least some of said anode material in said at least one cell to said seed layer for forming plated structures corresponding to the cavities of the insulating pattern layer on the master electrode; d) separating said master electrode from said substrate; e) removing said seed layer in non-plated areas; f) arranging a material in the areas in between the plated structures for forming a material layer that at least partly covers said plated structures; g) planarization of the material layer, until at least part of the structures is uncovered; h) repeating at least some of said steps for providing a multilayer structure.
In another aspect, there is provided a method of forming a multilayer structure by electrochemical etching of a substrate, comprising: a) arranging an electrically conducting seed layer on at least a part of the substrate or a substrate layer; b) applying a master electrode on said seed layer, said master electrode having an electrically conducting electrode layer and an insulating pattern layer for forming at least one electrochemical cell comprising an electrolyte in the area enclosed by said conducting electrode layer, said insulating pattern layer and said seed layer; c) applying a voltage between said conducting electrode layer and said seed layer so that said seed layer forms an anode for etching the seed layer and that said conducting electrode layer forms a cathode for depositing etched material in said at least one cell for forming etched structures corresponding to the insulating pattern layer on the master electrode; d) separating said master electrode from said substrate; e) removing possible remaining seed layer in between the etched structures; f) arranging a material in the areas between the etched structures for forming a material layer that at least partly covers said etched structures; g) planarization of the material layer, until at least part of the structures is uncovered; h) repeating at least some of said steps for providing a multilayer structure.
In an embodiment, the method may further comprise: planarization of the material layer, until at least part of the structures is almost uncovered; removing further material by a removal method having substantially uniform removal rate over the entire surface until at least a part of the structures is uncovered. The method may further comprise: between the steps d) and e) applying a further master electrode for forming electrochemical cells with the structures previously formed; and applying a voltage for forming a further layer of plated structures on top of the previously formed layer of structures. The step of planarization may be performed by at least one polishing and/or etching step. The step of polishing may comprise removing a portion of said material layer by an abrasive action. The at least one polishing step may be performed by a method selected from the group comprising: mechanical-polishing, chemical-polishing, chemical-mechanical-polishing (CMP), contact planarization (CP), planarization with a doctor blade, and combinations thereof. The polishing step may be performed by CMP or CP. The at least one etching step may be performed by a method selected from the group comprising: dry-etching methods, ion-sputtering, reactive-ion-etching (RIE), plasma-assisted-etching, laser-ablation, ion-milling, and combinations thereof.
In a further aspect, there is provided a method of forming a multilayer structure by electroplating on a substrate, comprising: a) arranging an electrically conducting seed layer on at least a part of the substrate or a substrate layer; b) applying a master electrode on said seed layer, said master electrode having an electrically conducting electrode layer, an anode material and an insulating pattern layer for forming at least one electrochemical cell comprising an electrolyte in the area enclosed by said anode material, said insulating pattern layer and said seed layer; wherein said anode material is being in electrical contact with said conducting electrode layer; c) applying a voltage between said conducting electrode layer and said seed layer so that said seed layer forms a cathode for transferring at least some of said anode material in said at least one cell to said seed layer for forming plated structures corresponding to the cavities of the insulating pattern layer on the master electrode; d) separating said master electrode from said substrate; e) removing said seed layer in non-plated areas; f) arranging a material in the areas in between the plated structures for forming a material layer that covers said plated structures; i) providing recesses in said material layer for uncovering at least a part of the plated structure there below; h) repeating at least some of said steps for providing a multilayer structure.
In a still further aspect, there is provided a method of forming a multilayer structure by electrochemical etching of a substrate, comprising: a) arranging an electrically conducting seed layer on at least a part of the substrate or a substrate layer; b) applying a master electrode on said seed layer, said master electrode having an electrically conducting electrode layer and an insulating pattern layer for forming at least one electrochemical cell comprising an electrolyte in the area enclosed by said conducting electrode layer, said insulating pattern layer and said seed layer; c) applying a voltage between said conducting electrode layer and said seed layer so that said seed layer forms an anode for etching the seed layer and that said conducting electrode layer forms a cathode for depositing etched material in said at least one cell for forming etched structures corresponding to the insulating pattern layer on the master electrode; d) separating said master electrode from said substrate; e) removing possible remaining seed layer in between the etched structures; f) arranging a material in the areas between the etched structures for forming a material layer that covers said etched structures; i) providing recesses in said material layer for uncovering at least a part of the etched structure there below; h) repeating at least some of said steps for providing a multilayer structure.
In an embodiment, the step of providing recesses in said material layer may be performed by a lithographic method selected from the group comprising: photolithography, laser lithography, E-beam lithography, nanoimprinting and combinations thereof. The lithographic method may further comprise patterning an etch-mask and etching said material layer with dry-etching methods, such as ion-sputtering, reactive-ion-etching, plasma-assisted-etching, laser-ablation, ion-milling or combinations thereof. The etch-mask may comprise a material selected from the group comprising: a resist, such as a photoresist; a hard-mask, such as SiN, SiO2, SiC, tetraethyl orthosilicate (TEOS), SiON, SiOC, SiCN:H, (non-porous) fluorine doped silicon glass (FSG), (non-porous) organic doped silicon glass (OSG), a low-k dielectric barrier/etch stop film such as BLok™, Pt, Ti, TiW, TiN, Al, Cr, Au, Ni, Cu, Ag, metals and by combinations thereof. The etch-mask may be dry-etched using a resist, such as a photoresist, as a mask; whereas said resist may be patterned with said lithographic method. The etch-mask may be formed by said structure layer in said step c). The step of arranging material in the areas between the plated or etched structures may be performed for forming a material layer having at least the thickness of two structure layers.
In another embodiment, the material layer may be planarized before providing recesses.
In a further embodiment, the method may further comprise applying a barrier/capping layer before step a). The method may further comprise applying a barrier/capping coating before step f).
The seed layer may be made of a material selected from the group comprising: Ru, Os, Hf, Re, Cr, Au, Ag, Cu, Sn, Ti, Ni, Al, alloys of these material, Si, conducting polymers such as polyaniline; solder materials, such as SnPb, SnAg, SnAgCu, SnCu; alloys, such as monel and permalloy; and combinations thereof. The seed layer may be applied by a method selected from the group comprising: chemical-vapor-deposition (CVD), metallorganic-chemical-vapor-deposition (MOCVD), physical-vapor-deposition (PVD), atomic layer deposition (ALD), sputtering, electroless plating, electroplating, electro-grafting, and immersion deposition.
The material layer may be a layer of a dielectric material and is applied by a method selected from the group comprising: spin-coating, spray-coating, powder-coating, dip-coating, roller-coating, sputtering, PVD, CVD, Plasma-Enhanced-Chemical-Vapor-Deposition (PECVD), electrodeposition, and combinations thereof. The dielectric material may comprise at least one layer of a material selected from the group comprising: low-k dielectric materials, ultra low-k dielectrics, dielectric materials with k-value less than 4, dielectric materials with k-value less than 2.5; organic compounds, insulating in-organic compounds, oxides, nitrides, polymer materials, polyimide, siloxane modified polyimide, BCB, SU-8, polytetrafluoroethylene (PTFE), silicones, elastomeric polymers, E-beam resists, ZEP (Sumitomo), photoresists, thinfilm resists, thickfilm resists, polycyclic olefins, polynorborene, polyethene, polycarbonate, PMMA, BARC materials, Lift-Off-Layer (LOL) materials, PDMS, polyurethane, epoxy polymers, fluoro elastomers, acrylate polymers, (natural) rubber, silicones, lacquers, nitrile rubber, EPDM, neoprene, PFTE, parylene, fluoromethylene cyanate ester, inorganic-organic hybrid polymers, (fluorinated and/or hydrogenated) amorphous carbon, organic doped silicon glass (OSG), fluorine doped silicon glass (FSG), PFTE/silicon compound, tetraethyl orthosilicate (TEOS), SiN, SiO2, SiON, SiOC, SiCN:H, SiOCH materials, SiCH materials, silicates, silica based materials, silsesquioxane (SSQ) based material, (nanoporous) methyl-silsesquioxane (MSQ), hydrogen-silsesquioxane (HSQ), TiO2, Al2O3, TiN and combinations thereof.
In a yet further aspect, there is provided a method of forming a multilayer structure by electrochemical plating on a substrate, wherein said substrate or said substrate layer comprises a via, the method comprising; a) arranging an electrically conducting seed layer on at least a part of the substrate or a substrate layer and said via; b) applying a master electrode, in which said insulating pattern layer is provided with cavities at least opposite to said vias, and wherein said cavities have a width which is slightly smaller, equal or slightly larger than the width of said via; and a predeposited anode material is arranged in said cavities; c) applying a voltage between said conducting electrode layer and said seed layer for transferring at least some parts of said anode material for forming plated structures in said vias.
In an embodiment, the seed layer is made of a material selected from the group comprising: Ru, Os, Hf, Re, Cr, Au, Ag, Cu, Sn, Ti, Ni, Al, alloys of these material, Si, conducting polymers such as polyaniline; solder materials, such as SnPb, SnAg, SnAgCu, SnCu; alloys, such as monel and permalloy; and combinations thereof. The seed layer may be applied by a method selected from the group comprising: chemical-vapor-deposition (CVD), metallorganic-chemical-vapor-deposition (MOCVD), physical-vapor-deposition (PVD), atomic layer deposition (ALD), sputtering, electroless plating, electroplating, electro-grafting, and immersion deposition.
In a yet still further aspect, there is provided a method of forming a structure by electrochemical plating on a substrate provided with a conducting material structure, comprising: a) arranging an electrically conducting seed layer on at least a part of the substrate; b) applying a master electrode on said seed layer, said master electrode having an electrically conducting electrode layer, an anode material and an insulating pattern layer for forming at least one electrochemical cell comprising an electrolyte in the area enclosed by said anode material, said insulating pattern layer and said seed layer, said cavity enclosing at least a part of said conducting material structure; wherein said anode material is being in electrical contact with said conducting electrode layer; c) applying a voltage between said conducting electrode layer and said seed layer so that said seed layer forms a cathode for transferring at least some of said anode material in said at least one cell to said seed layer for forming plated structures onto said seed layer and said conducting material structures corresponding to the cavities of the insulating pattern layer on the master electrode; d) separating said master electrode from said substrate.
The method may further comprise: b1) applying a further master electrode on said seed layer, said master electrode having an electrically conducting electrode layer, an anode material and an insulating pattern layer for forming at least one electrochemical cell comprising an electrolyte in the area enclosed by said anode material, said insulating pattern layer and said seed layer, said cavity enclosing at least a part of said conducting material structure and plated structures; wherein said anode material is being in electrical contact with said conducting electrode layer; c1) applying a voltage between said conducting electrode layer and said seed layer so that said seed layer forms a cathode for transferring at least some of said anode material in said at least one cell to said seed layer for forming plated structures onto said seed layer and said conducting material structures and plated structures corresponding to the cavities of the insulating pattern layer on the master electrode; d1) separating said master electrode from said substrate. The method may further comprise: e) removing said seed layer in non-plated areas.
In an embodiment, the planarization step may comprise performing a polishing step until said material surface is substantially planar and a subsequent etching step of said material surface until at least part of said structures is uncovered. A planarizing material may be applied into said material layer prior to performing said planarization step of said material layer. The planarizing material may be applied with a method selected from the group comprising: spin-coating, spray-coating, powder-coating, dip-coating, roller-coating, sputtering, PVD, CVD, PECVD, electrodeposition, and combinations thereof.
In another embodiment, an end-point detection method may be used so as to determine when said planarization step is completed. The end-point detection method may be selected from the group comprising: detecting when said structure material is being abraded or etched; determining the height of said material layer; and analyzing the color of said material layer. The detection may be based on interferometry of spectral analysis of said abraded material or said height is being determined by laser measurements or said color of said material is analyzed by using a sensor and a camera. The step of contact planarization may comprise: applying a plate above said material layer and applying a pressure on said plate for equalizing the material in said material layer, while in a flowable condition. The flowable condition may be obtained by heating said material layer, whereupon the material is cooled after planarization. The step of applying the plate is performed before curing said material, whereupon the material is cured after planarization, such as by applying infrared or ultraviolet radiation.
In a further embodiment, the seed layer is applied by a method selected from the group comprising: chemical-vapor-deposition (CVD), metallorganic-chemical-vapor-deposition (MOCVD), physical-vapor-deposition (PVD), atomic layer deposition (ALD), sputtering, electroless plating, electroplating, electro-grafting, immersion deposition, and combinations thereof. The arranging of a seed layer; and/or said arranging of a material; and/or said plating; and/or said etching; are performed by a method resulting in a controlled thickness.
In yet an embodiment, the method further comprises applying a barrier/capping layer before step a) and/or before step f). The barrier/capping material may comprise at least one layer of material that prevents corrosion, diffusion or electromigration of layers, which are interfacing with said barrier/capping material. The barrier/capping material may be selected from the group comprising: Ti, TiN, TiW, Cr, Ni, NiB, NiP, NiCo NiBW, NiM-P, Pd, Pt, Au, Ag, W, Ru, Ta, TaN, Re, Os, Hf, Rh, Wo, Co, CoReP, CoP, CoWP, CoWB, CoWBP, alloys thereof and combinations thereof. The barrier/capping material may be applied by a method selected from the group comprising electrodeposition, MOCVD, CVD, PVD, ALD, sputtering, electroless deposition, immersion deposition, electrografting and combinations thereof. The barrier/capping material may be applied with a mask-less selective deposition method, such as electroless deposition, wherein deposition is obtained only in surfaces active to said deposition process, such as on said structure layer and not on said arranged material layer.
The said barrier/capping material may be used as a seed layer in said step a). The seed layer may be made of a material selected from the group comprising: Ru, Os, Hf, Re, Cr, Au, Ag, Cu, Sn, Ti, TiN, TiW, Ni, NiB, NiP, NiCo NiBW, NiM-P, Al, Pd, Pt, W, Ta, TaN, Rh, Wo, Co, CoReP, CoP, CoWP, CoWB, CoWBP alloys of these material, Si, conducting polymers such as polyaniline; solder materials, such as SnPb, SnAg, SnAgCu, SnCu; alloys, such as monel and permalloy; and alloys thereof and combinations thereof. The seed layer may be cleaned and activated, wherein said cleaning and activation comprise using organic solvents, such as acetone or alcohols; and/or inorganic solvents, such as nitric acid, sulfuric acid, phosphoric acid, hydrochloric acid, acetic acid, hydrofluoric acid; strong oxidizing agents, such as peroxides, such as hydrogen-peroxide; persulfates, such as sodium-persulfate or ammonium-persulfate; ferric-chloride; and/or oxygen plasma; argon plasma; hydrogen plasma; and/or by mechanically removing impurities.
In yet a further embodiment, the method may further comprise applying an adhesion layer before applying said seed layer and/or before applying said barrier/capping material; wherein said adhesion layer increase the adhesion of said seed layer or barrier/capping layer to said arranged material layer or structures. The adhesion layer may comprise at least one material selected from the group comprising: Cr, Ti, TiW, AP-3000 (Dow Chemicals), AP-100 (Silicon Resources), AP-200 (Silicon Resources), AP-300 (Silicon Resources) and combinations thereof.
In a yet further embodiment, the forming of at least one electrochemical cell comprises a method for aligning said insulating pattern layer to a patterned layer on said substrate. The aligning method may comprise using alignment marks on the front side and/or backside of said master electrode, which marks are aligned to corresponding alignment marks on said substrate. The aligning method may be performed prior to forming at least one electrochemical cell. The formed electrochemical cell may comprise a solution of cations, such as copper or nickel ions, and anions, such as sulfate ions, for electrochemical etching and/or plating. The electrolyte may comprise suppressors, levelers and/or accelerators, for instance PEG (poly-ethylene glycol) together with chloride ions and/or with SPS (bis-(3-sulfopropyl)-disulfide), MPSA and/or sodium-lauryl-sulphate.
In an embodiment, the structure layer may be a material selected from the group comprising: Au, Ag, Ni, Cu, Sn, Pb, SnAg, SnAgCu, AgCu and combinations thereof. The structure layer may comprise Cu or Ni. The anode material may be arranged onto said conducting electrode layer in the cavities of said insulating pattern layer using a method selected from the group comprising: electroplating, electroless plating, immersion plating, CVD, MOCVD, powder-coating, chemical grafting, electrografting and combinations thereof. The method for arranging said anode material may comprise electroplating or electroless plating. The forming of structures is stopped, by disconnecting said voltage, prior to dissolving all or substantially of the anode material. At least 5% of the anode material may be remaining when said forming of structures is stopped. The depth of said etched structures or the thickness of said plated structures may be controlled by monitoring the time and current passing through said at least one electrochemical cell.
In a further embodiment, the separation step d) may be performed by holding said substrate in a fixed position and moving said master electrode in a direction perpendicular to the substrate surface; or by holding said master electrode in a fixed position and moving said substrate in a direction perpendicular to the master electrode surface; or by performing the separation in a less parallel manner so as to ease the separation; or by a combination thereof. The step e) removing said seed layer may be performed by wet-etching, dry-etching, electrochemical etching or by combinations thereof.
In an embodiment, the method further comprises applying a protective coating which is covering all or substantially all of said seed layer, barrier/capping layer and/or structure layer; treating said protective coating with an anisotropic etch, thereby uncovering the top of said seed layer, barrier/capping layer and/or structure layer between the structures while leaving a protective layer on the side walls of said structures; removing said seed layer and/or barrier layer between said structures.
The material layer may be at least one layer of a dielectric material and may be applied by a method selected from the group comprising: spin-coating, spray-coating, powder-coating, dip-coating, roller-coating, sputtering, PVD, CVD, Plasma-Enhanced-Chemical-Vapor-Deposition (PECVD), electrodeposition, and combinations thereof. The material layer may be at least one layer of a metal and may be applied by a method selected from the group comprising: electrodeposition, MOCVD, CVD, PVD, ALD, sputtering, electroless deposition, immersion deposition, electrografting and combinations thereof. The dielectric material may comprise at least one layer of a material selected from the group comprising: low-k dielectric materials, ultra low-k dielectrics, dielectric materials with k-value less than 4, dielectric materials with k-value less than 2.5; organic compounds, insulating in-organic compounds, oxides, nitrides, polymer materials, polyimide, siloxane modified polyimide, BCB, SU-8, polytetrafluoroethylene (PTFE), silicones, elastomeric polymers, E-beam resists, ZEP (Sumitomo), photoresists, thinfilm resists, thickfilm resists, polycyclic olefins, polynorborene, polyethene, polycarbonate, PMMA, BARC materials, Lift-Off-Layer (LOL) materials, PDMS, polyurethane, epoxy polymers, fluoro elastomers, acrylate polymers, (natural) rubber, silicones, lacquers, nitrile rubber, EPDM, neoprene, PFTE, parylene, fluoromethylene cyanate ester, inorganic-organic hybrid polymers, (fluorinated and/or hydrogenated) amorphous carbon, organic doped silicon glass (OSG), fluorine doped silicon glass (FSG), PFTE/silicon compound, tetraethyl orthosilicate (TEOS), SiN, SiO2, SiON, SiOC, SiCN:H, SiOCH materials, SiCH materials, silicates, silica based materials, silsesquioxane (SSQ) based material, (nanoporous) methyl-silsesquioxane (MSQ), hydrogen-silsesquioxane (HSQ), TiO2, Al2O3, TiN and combinations thereof.
In a further embodiment, the method further comprises: arranging an etch-stop layer on top of the structures before the step f) of arranging the material. The etch-stop layer may comprise at least one layer of a material selected from the group comprising: SiC, SiN, films, low-k dielectric barrier/etch stop films, such as BLOk™; Ti, TiN, TiW, Cr, Ni, NiB, NiP, NiCo NiBW, NiM-P, Pd, Pt, Au, Ag, W, Ru, Ta, TaN, Re, Os, Hf, Rh, Wo, Co, CoReP, CoP, CoWP, CoWB, CoWBP, alloys thereof and combinations thereof. The material layer may be a porous low-k dielectric material and a pore sealing operation may be performed prior to applying further layers of material onto it.
In a further embodiment, the material layer may be a sacrificial polymer, wherein said sacrificial polymer is being decomposed into gaseous phase when treated with heat or radiation. The sacrificial polymer may be a copolymer of butylnorbornene and triethoxysilyl norbornene, such as Unity Sacrificial Polymer™ (Promerus).
In a further embodiment, the method may further comprise: forming a structure layer before step h); wherein forming a structure layer may comprise lithography methods; deposition methods such as electrodeposition, electroless deposition; wet-etching or dry-etching methods.
Further objects, features and advantages of the invention will appear from the following detailed description of several embodiments with reference to the drawings, in which:
Below, embodiments including the best mode of the invention will be described in great detail in order to enable a skilled person to carry out the invention.
All embodiments described below comprise one or several of a number of method steps. Each of these steps will be described separately in detail below.
Generally, the method steps comprises one or several of the following six steps, namely:
a) arranging a seed layer on top of a substrate, or on top of a previous layer;
b) putting a master electrode in contact with the substrate, such as the seed layer, to form multiple electrochemical cells;
c) forming structures in said seed layer by etching or forming structures on said seed layer by plating;
d) removal of the master electrode;
e) possible removal of seed layer;
f) applying a dielectric material layer; and
possible planarizing and/or patterning of the dielectric material layer.
In a first step (a) the substrate is prepared by applying a seed layer on top of said supplied substrate. In some embodiments, a barrier/capping and/or adhesion layer is deposited on the substrate prior to applying the seed layer or arranged below the seed layer before being applied on the substrate.
Said seed layer comprises at least one, normally relatively thin layer of conducing material onto which material, such as predeposited anode material in the master electrode, can be plated with the ECPR plating process. Alternatively, the seed layer comprises at least one, normally relatively thick layer of conducing material in which structures can be etched with the ECPR etching process.
Since the seed layer forms one of the electrodes of the electrochemical cell, the seed layer must be applied at least where a cell is to be formed. Moreover, the seed layer must be able to be electrically contacted from the outside of the substrate or through conducting parts of the substrate, which is connected with the seed layer, or via the master electrode. Thus, the seed layer can be arranged covering only the required surfaces. However, the seed layer can be applied over the entire surface of the substrate to be acted upon.
The seed layer can be comprised of one or several layers of any of the materials Ru, Os, Hf, Re, Cr, Au, Ag, Cu, Sn, Ti, Ni, Al, alloys of these material, Si, other metals such as used for barrier/capping and/or adhesion layers mentioned below, conducting polymers such as polyaniline, solder materials such as SnPb, SnAg, SnAgCu, SnCu, alloys such as monel or permalloy and/or combinations thereof.
The seed layer can be applied by chemical-vapor-deposition (CVD), metallorganic-chemical-vapor-deposition (MOCVD), physical-vapor-deposition (PVD), atomic layer deposition (ALD), sputtering, electroless plating, electroplating, electro-grafting, immersion deposition and/or by other processes including applying layers of conducting material. When the seed layer is to be arranged on conducting as well as non-conducting areas of the substrate at the same time, vapor-deposition or sputtering techniques can be used. If the seed layer is to be relatively thick, electroplating may be used to form a layer having a relatively uniform upper surface independent on any recesses in the substrate surface. More in detail, a uniform upper surface can be achieved by using additives such as suppressors, levelers, accelerators and/or wetting agents, for instance PEG (poly-ethylene glycol) and chloride ions, SPS (bis-(3-sulfopropyl)-disulfide) and/or sodium-lauryl-sulphate used for copper plating, that increase the electrodeposition speed in the recess and/or by using pulse plating, for instance pulse-reverse-plating which also evens out height differences in the deposited layer. Using any application method, a uniform upper surface can be achieved independent on any recess in the substrate, specifically if the thickness of the seed layer is significantly larger than the depth of the recesses.
The seed layer of the substrate can be cleaned and activated before usage in the ECPR process. The cleaning method can include the use of organic solvents e.g. acetone or alcohols; and/or inorganic solvents e.g. nitric acid, sulfuric acid, phosphoric acid, hydrochloric acid, acetic acid, hydrofluoric acid, strong oxidizing agents, e.g. peroxides, persulfates, ferric-chloride, and/or de-ionized water. Cleaning can also be performed by applying oxygen plasma, argon plasma and/or hydrogen plasma or by mechanically removing impurities. Activation of the seed layer surface can be performed with solutions removing oxides, e.g. sulfuric acid, nitric acid, hydrochloric acid, hydrofluoric acid, phosphoric acid and etchants, e.g. sodium-persulfate, ammonium-persulfate, hydrogen-peroxide, ferric-chloride and/or other solutions comprising oxidizing agents.
Said barrier/capping layer can be comprised of at least one layer of at least one material or a combination of materials that: prevents said conducting material from corrosion; prevents said conducting material from diffusing into interfacing materials; prevents electro-migration and/or prevents other phenomena having negative effect on the electrical properties of the manufactured substrate. The barrier/capping layer can be comprised of Ti, TiN, TiW, Cr, Ni, NiB, NiP, NiCo NiBW, NiM-P, Pd, Pt, Au, Ag, W, Ru, Ta, TaN, Re, Os, Hf, Rh, Wo, Co, CoReP, CoP, CoWP, CoWB, CoWBP, alloys thereof and/or combinations thereof.
Said adhesion layer can be comprised of material or a combination of materials that increase the adhesion of the conducting seed layer material or barrier/capping material to the dielectric layer. The adhesion layer can be comprised of Cr, Ti, TiW, AP-3000 (Dow Chemicals), AP-100 (Silicon Resources), AP-200 (Silicon Resources) and/or AP-300 (Silicon Resources). The adhesion layer can in some embodiments also function as a catalytic layer facilitating and/or improving the deposition of the seed layer. The barrier/capping and/or adhesion layers can be applied by using deposition methods such as electrodeposition, MOCVD, CVD, PVD, ALD, sputtering, electroless deposition, immersion deposition, electrografting and/or other deposition methods suitable for the barrier/capping and/or adhesion materials.
The barrier/capping layer and/or adhesion layer can, in some embodiments, be applied with a mask-less selective deposition process such as electroless deposition and/or chemical grafting, whereby deposition is obtained only on surfaces active in relation to said deposition processes, for instance on a structure layer and not on a dielectric layer.
In some embodiments the seed layer also functions as a barrier/capping layer, for instance when applying a Ru layer. In other embodiments, a barrier/capping layer can be used as a seed layer. In some embodiments, said barrier/capping layer needs to be activated in order to function as a seed layer. Such surface activation can be Sn, or Pd activation, for instance by treating the surface with a PdCl2 and/or SnCl2 solution. A solution for Pd activation can be PdCl2 in diluted HCl. In some embodiments, HF is added to the activation solution, for instance when activating a TiN barrier/capping layer.
In a second step (b) a master electrode comprising an electrically conducting electrode layer, of at least one inert material, such as platinum, and an insulating pattern layer, is put in close physical contact with the conducting top layer, such as the seed layer, on the substrate in the presence of an electrolyte, forming electrochemical cells, filled with electrolyte, defined by the cavities of the insulating structures on the master. Putting the master in close contact with the top layer on the substrate includes aligning the master electrode insulating pattern to the patterned layer on the substrate. This step can include the use of alignment marks on the front side or backside of the master electrode that can be aligned to the corresponding alignment marks on the substrate. The alignment procedure can be performed before or after applying the electrolyte. Predeposited anode material may previously be arranged onto said conducting electrode layer in the cavities of the insulating pattern layer prior to putting the master in contact with a substrate. Predeposited material in the master electrode cavities can be cleaned and activated in advance, in the same manner as described for the substrate seed layer in the first step “(a)”, before putting the master into contact with the substrate.
Said electrolyte comprises a solution of cations and anions appropriate for electrochemical etching and/or plating, such as conventional electroplating baths. For instance, when the ECPR etched or plated structures are copper, a copper sulphate bath can be used, such as an acidic copper sulphate bath. Acidic may include a pH<4, such as between pH=2 and pH=4. In some embodiments, additives can be used, such as suppressors, levellers and/or accelerators, for instance PEG and chloride ions and/or SPS. In another example, when the ECPR etched or plated structures are Ni, a Watt's bath can be used. Appropriate electrolyte systems for different materials of ECPR etched or plated structures are described in: Lawrence J. Durney, et al, Electroplating Engineering Handbook, 4th ed., (1984).
In a third step (c) structures of conducting material are formed using ECPR etching or plating by applying a voltage, using an external power source, to the master electrode and to the seed layer on the substrate for creating an electrochemical process simultaneously inside each of the electrochemical cells defined by the cavities of the master electrode and the top layer on the substrate. When the voltage is applied in such a manner that the seed layer on the substrate is anode and the conducting electrode layer in the master electrode is cathode, the seed layer material is dissolved and at the same time material is deposited inside the cavities of the master electrode. The grooves created by dissolving the seed layer separate the remaining structures of the seed layer. The structures formed from the remaining seed layer is a negative image of the cavities of the insulating pattern layer of the master electrode; and these structures are referred to as “ECPR etched structures” below in this description. When the voltage is applied in such a manner that the conducting electrode layer in the master electrode is anode and the seed layer of the substrate is cathode, the predeposited anode material inside the cavities of the master electrode is dissolved and at the same time material is deposited on the conducting layer on the substrate in the cavities that are filled with electrolyte. The deposited material on the conducting layer on the substrate forms structures that are a positive image of the cavities of the insulating pattern layer of the master electrode; and these structures are referred to as “ECPR plated structures” below in this description.
Said ECPR etched or ECPR plated structures can be comprised of conducting materials, such as metals or alloys, for instance Au, Ag, Ni, Cu, Sn, Pb and/or SnAg, SnAgCu, AgCu and/or combinations thereof, for example Cu.
In one embodiment, said anode material is predeposited in the cavities of the master electrode by using ECPR etching of a material, which is anode, and depositing said material onto the conducting electrode, which is cathode, in the cavities of the insulating pattern layer of the master electrode. In other embodiments, said anode material is predeposited by regular electroplating, electroless plating, immersion plating, CVD, MOCVD, (charged) powder-coating, chemical grafting and/or electrografting said material selectively onto the conducting electrode layer in the cavities of the insulating pattern layer of the master electrode.
The voltage can be applied in a manner that improves the uniformity and/or properties of the etched and/or plated structures. The applied voltage can be a DC voltage, a pulsed voltage, a square pulsed voltage, a pulse reverse voltage and/or a combination thereof.
The uniformity of the etched and/or plated structures can be increased by choosing an optimized combination of applied voltage waveform, amplitude and frequency. The etch depth or plating height can be controlled by monitoring the time and the current passing through the master electrode. If the total electrode area is known, the current density can be predicted from the current passing through the electrode area. The current density corresponds to an etching or plating rate and hence the etching depth or plating height can be predicted from the etching or plating rate and time.
In some embodiments, the etching or plating process is stopped by disconnecting the applied voltage before reaching the underlying surface of the dissolving anode material. For the etching process, this means that the process is stopped when a layer is still remaining in the bottom of the etched grooves in the seed layer, covering the underlying substrate layer. Otherwise, there is a risk that the electric connection to certain portions of the seed layer may be broken. For the plating process, this means that the process is stopped when a layer of predeposited anode material still remains, such as 5% to 50%, covering the conducting electrode layer. Otherwise, uneven current distribution may occur in the respective electrochemical cells.
In some embodiments, the desired height of the plated structures is significantly less than the thickness of the predeposited anode material. This implies that several layers of structures can be plated onto one or several substrates before having to predeposit new anode material. In some examples the height of the predeposited material can be at least twice as thick as the height of the plated structures.
In some embodiments, multiple layers of ECPR plated structures are applied directly onto each other.
In a fourth step (d) after the ECPR etched or plated structures are formed, the master is separated from the substrate in a manner that minimizes damages on the master or on the ECPR etched or plated structures on the substrate. The method can be performed by holding the substrate in a fixed position and moving the master electrode in a direction perpendicular to the substrate surface or by holding the master electrode in a fixed position and moving the substrate in a direction perpendicular to the master electrode surface. In other embodiments, the separation can be performed in a less parallel manner in order to ease the separation.
In a fifth step (e) after ECPR plating, the seed layer on the substrate is removed so that the deposited structures are not connected to each other by the seed layer. After ECPR etching, remaining residues of the seed layer, which were not etched away, such as remaining debris or particles or even portions of the seed layer, inside the grooves separating the structures, can be removed. The seed layer removing step can include applying wet etching chemicals suitable for globally etching the materials that the seed layer is comprised of. An anisotropic etching method can be used in order to avoid or reduce the etching of the sidewalls and/or undercutting of the ECPR plated structures. In some cases the seed layer can be removed with dry-etching, for instance ion-sputtering, reactive-ion-etching (RIE), plasma-assisted-etching, laser-ablation, ion-milling. Dry-etching may remove the material by evaporation and removal in gaseous form. In some embodiments, the seed layer can be removed by a combination of dry-etching and wet-etching methods. For instance, a dry-etching method can sometimes leave residues or bi-products from etching the seed layer. These residues or bi-products can in some embodiments be removed by wet-etching methods. One example is: when dry-etching copper, a bi-product is formed which can be rinsed away with a wet-etch method containing hydrochloric acid. In some embodiments, said seed layer removing step can include electrochemical etching methods by applying a voltage making the seed layer anode and thereby dissolving (etching) at least some portions of said seed layer. Said electrochemical etching methods can in some embodiments include ECPR etching of at least some portions of the seed layer. In some embodiments, a protective coating is applied uniformly all over said ECPR etched or plated structures; said protective coating is treated with an anisotropic etch, said etch having the property of etching with a higher rate in a vertical direction than in lateral direction such as said dry-etching methods, thereby uncovering the top of said structures and/or the seed layer between the structures while leaving a protective layer on the side walls of said structures. In this case, the seed layer can be removed using said etching methods without etching the side walls and/or creating corner rounding of the ECPR etched or plated structures. Said protective coating can comprise materials, and can be applied with methods, such as used for an etch-mask layer described below. Said protective coating on the sidewalls of said structures can be removed after finishing the seed layer etching. In the case that a barrier/capping layer and/or adhesion layer have been applied on the substrate prior to applying the seed layer, these layers can be removed in the areas between the ECPR etched or plated structures using the same methods as mentioned above for the seed layer. In some cases, the seed layer, barrier/capping layer and/or adhesion layer are comprised of materials that can be selectively etched in relation to the material of the ECPR plated structures.
In some embodiments, said seed layer, barrier/capping layer and/or adhesion layer can be treated with methods converting said layers into insulating material. Such methods can for instance include: electrochemical anodization, such as anodizing a Ti layer to TiO2; thermal and/or plasma based treatment in an environment including gases or precursors, such as nitrogen and/or oxygen, that converts said layers into insulating layers; and/or chemical treatment for instance by strong oxidizing agents, such as peroxides and/or hydroxides. In this case, said layers being converted into insulating layers do not necessarily have to be removed.
After the ECPR etching or plating step, remaining material deposited inside the cavities of the master electrode can be removed using the same methods as for removing the seed layer on the substrate. The remaining material can in some embodiments also be removed by regular plating and/or ECPR plating onto a cathode and/or dummy substrate, respectively. In some embodiments this is done prior to using the master electrode in another ECPR etching step or prior to predepositing new material inside the cavities of the master used for the ECPR plating step. Alternatively, during plating, only a portion of the predeposited material may be used in a single procedure and another portion of the predeposited material may be used in the next procedure, for a number of procedures. Alternatively, during etching, the material deposited on the cathode, i.e. the master electrode, may not need to be removed between each procedure, but may be removed between each second, third, etc., procedure.
In a sixth step (f) a dielectric layer is applied onto the top layer of the substrate. In some embodiments, a barrier/capping layer and/or adhesion layer are applied onto the top layer of the substrate prior to applying said dielectric layer in order to improve the adhesion properties and/or prevent contamination, migration (electromigration) and/or diffusion of material; said barrier/capping layer and/or adhesion layer may be comprised of materials mentioned above and can be applied with methods described above. In some embodiments, said barrier/capping and/or adhesion layer can comprise materials such as for an etch-stop layer described below. Said dielectric layer can comprise one or several layers of materials with low dielectric constants.
The dielectric layer can be applied by spin-coating, spray-coating, powder-coating, dip-coating, roller-coating, sputtering, PVD, CVD, Plasma-Enhanced-Chemical-Vapor-Deposition (PECVD), electrodeposition, by other suitable deposition processes and/or by combinations thereof. The dielectric layer can be applied so that it completely covers the ECPR etched or plated structures as well as fills up the cavities. The layer is applied as uniformly as possible in order to avoid or minimize the use of a planarization process.
After application, a process can be performed to uncover the top of at least some parts of said structures from the dielectric layer. In an embodiment this is done by planarizing the dielectric layer to the same level as the top of said structures. Said planarization can be done by polishing and/or etching methods. The polishing methods can be mechanical and/or chemical. In some embodiments, chemical-mechanical-polishing (CMP) can be used. CMP includes planarizing the dielectric material using a mechanical force from a rotating or translating polishing pad together with a chemical component from a polishing slurry that is applied on the polishing pad which is put in close contact with the dielectric material or directly onto the material. The slurry chemistry is relevant for proper polishing. It can consist of micro or nano sized silica or aluminum particles in a carrier solution. During the CMP planarization, a chemical reaction occurs at the dielectric surface, which makes the surface susceptible to mechanical abrasion by the particles suspended in the slurry. The abraded particles are then swept away from the vicinity of the substrate surface and flushed from the system as fresh slurry is added and used slurry is removed from the system.
Another planarization method is to use a doctor blade.
A further planarization method is contact planarization (CP), which comprises applying a force or a pressure with a planar disc, which for instance is comprised of silicon, glass and/or quartz, onto a layer thereby reducing the unevenness of the layer surface. In some embodiments, a planarizing material layer is applied onto the dielectric layer prior to using said planarization methods. The planarizing material layer results in a more planar surface, than of the underlying layer, when applied. Said planarizing material layer can be applied with methods such as spin-coating, spray-coating, powder-coating, dip-coating, roller-coating, sputtering, PVD, CVD, PEVCD, electrodeposition and/or by combinations thereof. In some embodiments, the dielectric material and/or said planarization material layer is not cured prior to using said planarization methods which means that the material is in a more or less soft or flowable condition so that the material moves and planarize under the influence of the pressure. When using CP methods, said planar disc can be optically transparent, and UV-light and/or heat radiation can pass there through and be applied in order to cure said planarization material layer and/or dielectric layer. In other embodiments, the dielectric and/or planarizing material layer is brought into contact with said planar disc without applying a pressure. Thereafter, the dielectric and/or planarizing material layer can be heated (for example above the glass temperature Tg) followed by applying a mechanical force by the planar disc onto the dielectric and/or planarizing material layer during sufficient time for planarization to occur. The heating may occur by having the disc at an elevated temperature or heating the disc. After releasing the pressure, the dielectric and/or planarizing material layer can be cooled (for example below Tg) and the planar disc can be removed from the planarized surface.
In some embodiments, planarization using said etching methods (commonly referred to as etch-back methods) include dry-etching methods such as ion-sputtering, reactive-ion-etching (RIE), plasma-assisted-etching, laser-ablation, ion-milling and/or combinations thereof. Said etching methods may give a uniform etching rate over the entire surface that is planarized.
Planarization can in some embodiments be preformed by combining different planarization methods. In some cases it can be suitable first to use CMP and/or CP to planarize the top surface and then use said etching methods to further planarize or further remove said planarizing material layer and/or dielectric layer until it uncovers the top of the ECPR etched or ECPR plated structures. The etching may be global or only affect the dielectric material. For instance, the planarization speed can be significantly higher on the dielectric material than on the ECPR etched or plated structures. This minimizes the amount of abraded material from the ECPR etched or plated structures during said planarization step. The structure material or metal may include an etch-stop layer or coating for preventing etching thereof. The etching can be continued until all structure portions are uncovered. The etching can be further continued in order to ensure that all structure portions are safely uncovered, such as less than about 20% extra, for example less than about 10%, for instance less than about 1%.
In some embodiments, end-point detection can be used to determine when said etching or planarization method is completed. The end-point detection method can comprise the use of a sensor that detects when the material of the ECPR etched or plated structures is being abraded and/or etched by said planarization methods. The detection can be based on interferometry or spectral analysis of the etching plasma that detects molecules or atoms of the ECPR etched or ECPR plated structures, which are abraded/etched by said etching or planarization methods. Other end detection methods may be used such as laser measurement of the height of the layer. Yet further end-point detection methods can include a sensor for analysis of the color of the planarized material, such as by using a camera, for example an LCD-camera.
In some embodiments, the tops of at least some parts of said structures are uncovered from the dielectric layer, which covers at least some parts of the structures, by patterning said dielectric layer with for example a lithographic process. Said lithographic process can be photolithography, laser lithography, E-beam lithography, nanoimprinting or other lithographic processes suitable for the dielectric material.
In another embodiment, at least some parts of the top of said structures as delimited by an etch-mask, are uncovered by dry-etching the dielectric layer with methods such as ion-sputtering, reactive-ion-etching (RIE), plasma-assisted-etching, laser-ablation, ion-milling. The patterned material used as an etch-mask for the dry-etching process can be a photoresist and/or another polymer material that can be patterned by said lithographic processes. The etch-mask material for dry-etching the dielectric layer can also comprise materials such as SiN, SiO2, SiC, tetraethyl orthosilicate (TEOS), SiON, SiOC, SICN:H, (non-porous) fluorine doped silicon glass (FSG), (non-porous) organic doped silicon glass (OSG), a low-k dielectric barrier/etch stop film such as BLOk™ (Applied Materials), Pt, Ti, TiW, TiN, Al, Cr, Au, Ni, Cu, Ag, other metals, other hard materials and/or combinations thereof. The etch-mask material can in turn be etched using a patterned photoresist and/or another resist, which is patterned with said lithographic processes, as a mask. In some embodiments, the etch-mask can comprise at least one layer of ECPR etched or plated structures. In some embodiment, said etch-mask is removed after the etching step. However, in other embodiments, such as when the etch-mask comprise and insulating material, removing the etch-mask is not required, for instance in order to improve mechanical properties of the multilayer structure.
In some embodiments, said dielectric layer can be applied with a thickness corresponding to multiple structure layers and patterned in several layers prior to applying at least one structure layer. Alternatively, said dielectric layer can be applied and patterned repeatedly, thereby creating a patterned dielectric layer with a thickness corresponding to multiple structure layers, prior to applying at least one structure layer.
In all embodiments, the method for uncovering at least some parts of the ECPR etched or plated structures from the dielectric material can include a combination of said planarization methods and said patterning methods.
In some embodiments, the dielectric materials can be comprised of materials having dielectric constants less than 4.0. Such materials are generally referred to as low-k materials. The low-k materials can comprise carbon-doped dielectrics, such as OSG, FSG, organic polymers, and the like. In other embodiments, ultra-low-k dielectric materials can be used with a k-value ranging from less than 2.5. For all embodiments, the dielectric material can be comprised of organic compounds, such as polymers, as well as insulating inorganic compounds such as oxides and/or nitrides. Used polymer materials can for instance be: polyimide, siloxane modified polyimide, BCB, SU-8, polytetrafluoroethylene (PTFE), silicones, elastomeric polymers, E-beam resists (such as ZEP (Sumitomo)), photoresists, thinfilm resists, thickfilm resists, polycyclic olefins, polynorborene, polyethene, polycarbonate, PMMA, BARC materials, Lift-Off-Layer (LOL) materials, PDMS, polyurethane, epoxy polymers, fluoro elastomers, acrylate polymers, (natural) rubber, silicones, lacquers, nitrile rubber, EPDM, neoprene, PFTE, parylene, fluoromethylene cyanate ester, inorganic-organic hybrid polymers, (fluorinated and/or hydrogenated) amorphous carbon, by other polymers and/or by combinations thereof. Used inorganic compounds can for instance be organic doped silicon glass (OSG), fluorine doped silicon glass (FSG), PFTE/silicon compound, tetraethyl orthosilicate (TEOS), SiN, SiO2, SiON, SiOC, SiCN:H, SiOCH materials, SiCH materials, silicates, silica based materials, silsesquioxane (SSQ) based material, (nanoporous) methyl-silsesquioxane (MSQ), hydrogen-silsesquioxane (HSQ), TiO2, Al2O3, TiN and/or combinations thereof.
Said dielectric material can also comprise other available low-k dielectrics listed in the publication: K. Maex, M. R. Baklanov, D. Shamiryan, F. Iacopi, S. H. Brongersma, Z. S. Yanovitskaya, J. Appl. Phys. 93, 8793 (2003).
In some embodiments, an etch-stop layer is deposited onto the top layer on the substrate prior to applying the dielectric layer. The etch-stop material can be comprised of a material that is much less effected by said dry-etching processes than the dielectric material, and which can be used for selectively etch cavities in the dielectric layer down to the underlying etch-stop layer on top of underlying layer of the substrate or etch down the dielectric layer to slightly below the top of the structure layer. For instance, the etch-stop material can be comprised of SiC, SiN, Pt and/or TiW films. A low-k dielectric barrier/etch stop film, such as BLOk™ may be used. Material used for said barrier/capping, adhesion and/or etch-mask layer may also be used for the etch-stop layer. This silicon carbide film is deposited using trimethylsilane ((CH3)3SiH) and has a lower dielectric constant (k<5) than that of conventional SiC films (k>7) generated by SiH4 and CH4, and that of plasma silicon nitride (k>7). In some embodiments, said etch-stop layer can also function as a barrier/capping layer and/or adhesion layer, which adhesion layer also may improve the adhesion between the lower dielectric layer and the upper dielectric layer.
In some aspects, for instance when the dielectric material is a porous ultra low-k dielectric material, a pore sealing operation can be done prior to applying any material layer onto the dielectric. In other embodiments, said dielectric material can be a sacrificial polymer material wherein the sacrificial polymer is decomposed into a gaseous phase when for instance treating the material with heat or radiation. In this case, said dielectric material can be removed, by decomposing said material and allowing the byproducts to diffuse away, after the multiple structure layers are formed and thereby creating voids or air gaps in the areas that were occupied by the dielectric layer. Said sacrificial polymer used can be a copolymer of butylnorbornene and triethoxysilyl norbornene, such as Unity Sacrificial Polymer™ (Promerus). Further more, by using mechanically stable and insulating barrier/capping and/or etch-mask layers that are not removed from the multiple structure layers, said multiple structure layers are prevented from collapsing.
In some embodiments, forming multiple layers of conducting and/or dielectric materials includes creating at least one layer with ECPR etching and/or plating and creating at least another layer with known masking and deposition techniques such as lithography followed by electrodeposition, electroless deposition, wet etching, dry etching or other methods for creating a patterned layer of a conducting material.
Below, several of the method steps for producing a multilayer substrate will be disclosed on the drawings, which show several embodiments of the method steps.
If polishing is used in the planarization steps of
If a polishing method is used, the polishing will be performed on two layers having different hardness, such as the hard structure layer of metal and the soft material layer of dielectric material. This can result in dishing and erosion of the soft material and crack formation on the structure layer. The dishing and erosion problems are directly related to the amount of structure material that is planarized. By carefully controlling the thickness of the structure layer, by using a master electrode with predeposited anode material, dishing, erosion and overall planarity problems can be significantly reduced or even eliminated.
The process is repeated until the desired number of layers is built.
ECPR plating can be used for creating metallic interconnects in semiconductor device. A substrate 2 is patterned with a pre-metal dielectric 12, which is arranged covering possible semiconductors or transistors formed in the substrate. The cavities or the pattern are filled for creating connection plugs 13 of a suitable material, for instance tungsten. A first barrier/capping layer 14 is applied onto the connection plugs 13 and the pre-metal dielectric layer 12. The barrier/capping layer can be of the same materials and can be applied with the same methods as described for the barrier/capping layers in said step “(f)”. On top of the barrier/capping layer, a first layer of dielectric material 9 is applied with methods in said step “(f)”. The dielectric material may comprise a suitable low-k or ultra low-k material, also described in said step “(f)”. The result of performing the mentioned steps is shown in
Finally, a passivation layer 17 is applied on top of the ECPR plated structures and dielectric material 9. The passivation layer can be one or several barrier/capping layers and/or dielectric material layers.
Finally, a passivation layer 17 is applied to cover the dielectric material and the top of the ECPR plated structures, which are covered with a barrier/capping coating. In some embodiments, forming multiple metallic interconnect layers and dielectric layers in a semiconductor device includes creating at least one layer of ECPR plated structures and dielectric material, as illustrated in
Some embodiments, such as when forming metallic interconnects for integrated circuits (IC), includes fabricating said interconnects by forming multiple ECPR plated structure layers, for instance comprising Cu, and arranging a dielectric material, such as a low-k material, between said structures. In said known damascene process, the dielectrics layers are firstly etched and subsequently interconnects are electroplated filling the cavities etched. In order to decrease the RC-delay of an IC device, dielectric materials with lower dielectric constant is required. However, with ultra low-k dielectric material, etching and post-etch-cleaning may result in various problems such as too high line width variations and k-value increase. As described above, the method of the present process can eliminate or reduce the number of etching steps of said layers of dielectric material, for instance ultra low-k dielectric layers. Said elimination or reduction of number of etching steps results in less line width variations and less k-value increase which enables the use of ultra low-k materials in an IC device and hence a lower RC-delay as well as less RC-delay variations can be achieved.
ECPR plating can be used to fill vias or other grooves in a substrate and/or in a patterned material onto a substrate.
The master electrode comprises at least one insulating pattern layer and at least one conducting electrode layer (normally inert in the ECPR process) and possibly a predeposited anode material in the cavities of the master electrode. For instance, the insulting pattern of the master layer is a polymer, e.g. a photoresist, an oxide, e.g. SiO2, a nitride, e.g. SiN, or combinations thereof. The electrolyte comprises suitable substances for dissolving and depositing the conducting material in which the structures are formed during the ECPR process. For instance, when the conducting material is copper, the electrolyte comprises an aqueous solution of Cu2+, SO42−, H+ and/or Cl− and additives such as levelers, accelerators, brighteners, suppressors and wetting agents. Appropriate additives can be poly-ethylene-glycol (PEG), chloride ions, MPSA, SPS and/or sodium-lauryl-sulfate.
In some embodiments, an etching pattern is created with an electrochemical process by using the conducting electrode layer of the master electrode as cathode whereby material is dissolved from the substrate, transferred in the electrolyte and deposited on the cathode thereby creating ECPR etched structures on the substrate corresponding to the pattern of insulating pattern layer on the master electrode. Since the material that is being dissolved from the substrate, which is anode, also is deposited at the conducting electrode layer, which is cathode, the amount of dissolved anode material in the electrolyte remains close to constant during the electrochemical process. If the deposition rate of the dissolved material is zero, the concentration of dissolved anode material ions in the electrolyte increases quickly, this slows down the electrochemical reaction until it eventually stops. A too high ion concentration can also result in precipitation of salts. In this case, only small amounts could be dissolved from the substrate and only thin layers could be patterned. Instead, by making sure that the dissolution reaction has an appropriate deposition reaction, substrates with thicker layers can be etched. The dissolution and deposition reaction in the electrochemical process is determined by the thermodynamic and kinetic reaction at a given applied potential in a specific system of anode, cathode and electrolyte. By choosing the appropriate anode material, cathode material and electrolyte, the desired dissolution and deposition reaction can be achieved since they are thermodynamically and kinetically favorable in the chosen system.
One example of appropriate anode, cathode and electrolyte system is Ni as anode material, Au as a cathode material and a Watt's bath used as electrolyte. In some aspects, the deposition reaction does not have to be corresponding to the dissolution reaction exactly. As long as the deposition rate of the dissolved material is larger than zero, the buildup of ion concentration of anode material in the electrolyte will be slow which means that it will take longer time before the reaction stops and hence thicker layers on the substrate can be etched. For instance, the deposition rate of the dissolved ions can be 90-100% of the dissolution rate. In this example, the ion concentration of dissolved anode will increase slowly, but in some aspects a desired etched thickness can be achieved before the concentration becomes too high. In some cases, the dissolution rate can be lower than the deposition speed, which eventually leads to depletion of ion concentration in the electrolyte. However, if the dissolution reaction is not too low compared to the deposition reaction (e.g. >90% of the deposition rate), a desired thickness can still be etched from the substrate before depletion of anode material ions in the electrolyte. One example of an inappropriate system is Ag as anode material, Al as cathode material and an alkaline silver cyanide bath as an electrolyte. In this example, the deposition rate of silver ions is zero, which will lead to a fast buildup of silver ions in the electrolyte.
A plating pattern is created by an electrochemical process by using the conducting electrode layer of the master electrode as anode and having predeposited anode material on the anode inside the cavities defined by the master electrode whereby said anode material is dissolved, transferred in the electrolyte and deposited on the substrate, being cathode, thereby creating ECPR plated structures on the substrate corresponding to the cavities of the insulating pattern layer on the master electrode.
One problem with prior art processes which do not have a predeposited material is that anode material is dissolved directly from conducting electrode layer 6 in the master 4, the master electrode will eventually wear out since the dissolved material is undercutting the insulating pattern layer 5, as illustrated in
Another problem with prior art processes, which do not have predeposited material is that the dissolved material that is undercutting the insulating pattern layer leads to that the anode area increases differently in large contra small cavities in the insulating pattern layer. In large cavities, the area increase due to undercutting is smaller than in small cavities, as illustrated in
Also, the dissolution of predeposited material prevents the depletion of the concentration of ions in the electrolyte that are deposited on the cathode. A depletion of ions in the electrolyte would gradually slow down the deposition process until it eventually stops and only thin layers of plated structures would be achievable. By having a sufficient amount of predeposited material that is being dissolved during the electrochemical deposition reaction, the ion concentration remains stable and thicker layers of plated structures can be achieved. By choosing the appropriate predeposited material (anode), seed layer material (cathode) and electrolyte, the desired dissolution and deposition reaction can be achieved since they are thermodynamically and kinetically favorable in the chosen system. One example of an appropriate choice of electrochemical system is: having Cu as predeposited material (anode), Cu as seed layer (cathode) and an acidic copper sulfate bath as an electrolyte. In some cases, the deposition reaction does not have to be corresponding to the dissolution reaction exactly. As long as the dissolution rate of the predeposited material is larger than zero, the depletion of ion concentration in the electrolyte will be slower which means that it will take longer time before the reaction stops and hence thicker layers can be plated. For instance, the dissolution rate can be 90-100% of the deposition rate. In this example, the ion concentration of material being deposited will decrease slowly, but in some aspects a desired plated thickness can be achieved before the concentration becomes too low.
As mentioned above, the method may include applying a barrier/capping coating 16 onto the top layer on the substrate 2 prior to applying a dielectric material 9. This may be done with a mask-less method, as mentioned in said step “(f)”, selectively coating the ECPR plated structures 11. In some embodiments, it can be suitable not to remove the barrier/capping layer 14 after removing the seed layer 1 and prior to applying the barrier/capping coating 16. In this way, top layer on the substrate 2, for instance a dielectric material layer, is protected by the barrier/capping layer 14 in the following step of applying the barrier/capping coating 16. The barrier/capping layer 14 can be of a material onto which no barrier/capping coating 16 is deposited during the mask-less method used for applying the coating onto the ECPR plated structures 11. After applying the barrier/capping coating selectively onto the ECPR plated structures 11, the barrier/capping layer 14 between the structures can be removed using said removing methods for the layer described in said step “(e)”. The barrier/capping material may comprise a material that can be etched with a dry-etch method described in said step “(e)”. The barrier/capping coating 16 may comprise a material that is not affected by the removing method used for the barrier/capping layer 14 or at least less affected than the material used for the barrier/capping layer 14.
In some embodiments, a conducting or semiconducting layer is used instead of said dielectric layer. In some cases, a sacrificial layer may be used instead of said dielectric layer, said sacrificial layer being removed after forming said multiple structure layers. In further cases, the same layer may comprise structural material, sacrificial material and dielectric material.
The height of the different material layers is indicated in the drawings to be of the same size. However, each individual layer can be of any dimension as required by the construction. However, normally, each layer is of a uniform height over the entire surface of the substrate, i.e. the layer has a substantially constant thickness.
Herein above, several method steps have been described in different combinations and constellations. However, it is emphasized that other combinations may be performed as occur to a skilled person reading this specification, and such combinations are within the scope of the present invention. Moreover, the different steps can be modified or altered still within the scope of the invention. The invention is only limited by the appended patent claims.
Claims
1-76. (canceled)
77. A method of forming a multilayer structure by electrochemical plating on a substrate, wherein said substrate or said substrate layer comprises a via, the method comprising:
- a) arranging an electrically conducting seed layer on at least a part of the substrate or a substrate layer and said via;
- b) applying a master electrode, in which said insulating pattern layer is provided with cavities at least opposite to said vias, and wherein said cavities have a width which is slightly smaller, equal or slightly larger than the width of said via; and a predeposited anode material is arranged in said cavities;
- c) applying a voltage between said conducting electrode layer and said seed layer for transferring at least some parts of said anode material for forming plated structures in said vias.
78. A method of forming a structure by electrochemical plating on a substrate provided with a conducting material structure, comprising:
- a) arranging an electrically conducting seed layer on at least a part of the substrate;
- b) applying a master electrode on said seed layer, said master electrode having an electrically conducting electrode layer, an anode material and an insulating pattern layer for forming at least one electrochemical cell comprising an electrolyte in the area enclosed by said anode material, said insulating pattern layer and said seed layer, said cavity enclosing at least a part of said conducting material structure; wherein said anode material is being in electrical contact with said conducting electrode layer;
- c) applying a voltage between said conducting electrode layer and said seed layer so that said seed layer forms a cathode for transferring at least some of said anode material in said at least one cell to said seed layer for forming plated structures onto said seed layer and said conducting material structures corresponding to the cavities of the insulating pattern layer on the master electrode;
- d) separating said master electrode from said substrate.
79. The method of claim 78, further comprising:
- b1) applying a further master electrode on said seed layer, said master electrode having an electrically conducting electrode layer, an anode material and an insulating pattern layer for forming at least one electrochemical cell comprising an electrolyte in the area enclosed by said anode material, said insulating pattern layer and said seed layer, said cavity enclosing at least a part of said conducting material structure and plated structures; wherein said anode material is being in electrical contact with said conducting electrode layer;
- c1) applying a voltage between said conducting electrode layer and said seed layer so that said seed layer forms a cathode for transferring at least some of said anode material in said at least one cell to said seed layer for forming plated structures onto said seed layer and said conducting material structures and plated structures corresponding to the cavities of the insulating pattern layer on the master electrode; and
- d1) separating said master electrode from said substrate.
80. The method of any one of claims 77 and 78, further comprising:
- e) removing said seed layer in non-plated areas.
81. The method of any one of claims 77 and 78, wherein said planarization step comprises performing a polishing step until said material surface is substantially planar and a subsequent etching step of said material surface until at least part of said structures is uncovered.
82. The method of any one of claims 77 and 78, wherein a planarizing material is applied into said material layer prior to performing said planarization step of said material layer.
83. The method of claim 82, wherein said planarizing material is applied with a method selected from the group comprising: spin-coating, spray-coating, powder-coating, dip-coating, roller-coating, sputtering, PVD, CVD, PECVD, electrodeposition, and combinations thereof.
84. The method of any one of claims 77 and 78, wherein an end-point detection method is used so as to determine when said planarization step is completed.
85. The method of any one of claims 77 and 78, wherein the step of planarization comprises:
- applying a plate above said material layer and applying a pressure on said plate for equalizing the material in said material layer, while in a flowable condition.
86. The method of claim 85, wherein said flowable condition is obtained by heating said material layer, whereupon the material is cooled after planarization.
86. The method of claim 85, wherein said step of applying the plate is performed before curing said material, whereupon the material is cured after planarization, such as by applying infrared or ultraviolet radiation.
87. The method of any one of claims 77 and 78, wherein the seed layer is made of a material selected from the group comprising: Ru, Os, Hf, Re, Cr, Au, Ag, Cu, Sn, Ti, TiN, TiW, Ni, NiB, NiP, NiCo NiBW, NiM-P, Al, Pd, Pt, W, Ta, TaN, Rh, Wo, Co, CoReP, CoP, CoWP, CoWB, CoWBP alloys of these material, Si, conducting polymers such as polyaniline; solder materials, such as SnPb, SnAg, SnAgCu, SnCu; alloys, such as monel and permalloy; and alloys thereof and combinations thereof.
88. The method of claim 87, wherein the seed layer is applied by a method selected from the group comprising: chemical-vapor-deposition (CVD), metallorganic-chemical-vapor-deposition (MOCVD), physical-vapor-deposition (PVD), atomic layer deposition (ALD), sputtering, electroless plating, electroplating, electrografting, immersion deposition, and combinations thereof.
89. The method of any one of claims 77 and 78, further comprising applying a barrier/capping layer before step a) or f).
90. The method of claim 89, wherein said barrier/capping material comprises at least one layer of material that prevents corrosion, diffusion or electromigration of layers which are interfacing with said barrier/capping material.
91. The method of claim 89, wherein said barrier/capping material is applied by a method selected from the group comprising: electrodeposition, MOCVD, CVD, PVD, ALD, sputtering, electroless deposition, immersion deposition, electrografting and combinations thereof.
92. The method of claim 91, wherein said barrier/capping material is applied with a mask-less selective deposition method, such as electroless deposition, wherein deposition is obtained only in surfaces active to said deposition process, such as on said structure layer and not on said arranged material layer.
93. The method of any one of claims 77 and 78, wherein said barrier/capping material is used as a seed layer in said step a).
94. The method of any one of claims 77 and 78, further comprising applying an adhesion layer before applying said seed layer and/or before applying said barrier/capping material; wherein said adhesion layer increase the adhesion of said seed layer or barrier/capping layer to said arranged material layer or structures.
95. The method of any one of claims 77 and 78, wherein said forming of at least one electrochemical cell comprises a method for aligning said insulating pattern layer to a patterned layer on said substrate, wherein said aligning method comprises using alignment marks on the front side and/or back side of said master electrode which are aligned to corresponding alignment marks on said substrate.
96. The method of any one of claims 77 and 78, wherein said formed electrochemical cell comprises a solution of cations, such as copper or nickel ions, and anions, such as sulfate ions, for electrochemical etching and/or plating.
97. The method of claim 96, wherein said electrolyte comprises suppressors, levelers and/or accelerators, for instance PEG (poly-ethylene glycol) together with chloride ions and/or with SPS (bis-(3-sulfopropyl)-disulfide), MPSA and/or sodium-lauryl-sulphate.
98. The method of any one of claims 77 and 78, wherein said anode material is arranged onto said conducting electrode layer in the cavities of said insulating pattern layer using a method selected from the group comprising: electroplating, electroless plating, immersion plating, CVD, MOCVD, powder-coating, chemical grafting, electrografting and combinations thereof.
99. The method of any one of claims 77 and 78, wherein said separation step d) is performed by holding said substrate in a fixed position and moving said master electrode in a direction perpendicular to the substrate surface; or
- by holding said master electrode in a fixed position and moving said substrate in a direction perpendicular to the master electrode surface; or
- by performing the separation in a less parallel manner so as to ease the separation; or by a combination thereof.
100. The method of any one of claims 77 and 78, wherein said step e) removing said seed layer is performed by wet-etching, dry-etching, electrochemical etching or by combinations thereof.
101. The method of claim 100, further comprising applying a protective coating which is covering all or substantially all of said seed layer, barrier/capping layer and/or structure layer; treating said protective coating with an anisotropic etch, thereby uncovering the top of said seed layer, barrier/capping layer and/or structure layer between the structures while leaving a protective layer on the side walls of said structures; removing said seed layer and/or barrier layer between said structures.
102. The method of any one of claims 77 and 78, wherein said material layer is at least one layer of a dielectric material and is applied by a method selected from the group comprising: spin-coating, spray-coating, powder-coating, dip-coating, roller-coating, sputtering, PVD, CVD, Plasma-Enhanced-Chemical-Vapor-Deposition (PECVD), electrodeposition, and combinations thereof.
103. The method of any one of claims 77 and 78, wherein said material layer is at least one layer of a metal and is applied by a method selected from the group comprising: electrodeposition, MOCVD, CVD, PVD, ALD, sputtering, electroless deposition, immersion deposition, electrografting and combinations thereof.
104. The method of any one of claims 77 and 78, further comprising:
- arranging an etch-stop layer on top of the structures before the step f) of arranging the material.
105. The method of any one of claims 77 and 78, wherein said material layer is a porous low-k dielectric material and a pore sealing operation is performed prior to applying further layers of material onto it.
106. The method of any one of claims 77 and 78, further comprising forming a structure layer before step h); wherein forming a structure layer comprises lithography methods; deposition methods such as electrodeposition, electroless deposition; wet-etching or dry-etching methods.
Type: Application
Filed: Mar 26, 2009
Publication Date: Jul 23, 2009
Applicant:
Inventors: Mikael FREDENBERG (Stockholm), Patrik Moller (Stockholm), Peter Wiwen-Nilsson (Stockholm)
Application Number: 12/412,322
International Classification: C25D 21/12 (20060101); B44C 1/22 (20060101); B05D 5/12 (20060101); C25D 5/02 (20060101); C25D 5/00 (20060101); C25D 5/34 (20060101); C25D 5/54 (20060101);
