MICROPACKAGING METHOD AND DEVICES
A method of micro-packaging a component wherein at least a first and a second semi-conductor substrate are provided, one of which has electrical through connections (vias). A depression in either one of the substrates or in both is etched. A component is provided above vias and connected thereto. The substrates are joined to form a sealed package. A micro-packaged electronic or micromechanic device, including a thin-walled casing of a semi-conductor material having electrical through connections through the bottom of the casing is also disclosed. An electronic or micromechanic component is attached to the electrical through connections, and the package is hermetically sealed for maintaining a desired atmosphere, suitably vacuum inside the box.
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The present invention relates to packaging of components for electronic devices, in particular devices requiring small components, such as but not limited to electrical and micromechanical surface micromachined oscillators for computers, mobile phones and the like.BACKGROUND OF THE INVENTION
Certain components for surface mounting on circuit boards must be packaged in protective casings, quite often in vacuum or other controlled atmosphere/ambient and also need to be provided with connector legs for mounting or solder bumps for surface mounting. Today most encapsulating casings are made of polymers or ceramic materials. The latter is commonly used for packaged components that are hermetically sealed.
The inner compartment of such ceramic casings is made by milling processes. These processes have inherent drawbacks.
One thing is that the thickness of the package has an inherent lower limit. For e.g. mobile phone applications thickness is a vital parameter, and thus it would be desirable to further reduce the component thicknesses.
Sealing of individual packages is required, i.e. each individual item has to be handled separately for attaching a lid under vacuum, which requires elaborate equipment.
Also, there will always be rounded corners in the interior compartment because of the nature of the milling tools. Also, it is difficult to make very thin walls in such ceramic materials. This puts a lower limit of the size of such casings.
The smallest dimensions are dependent on the dimensions and the pitch between the interconnecting vias to the outside of the package. Package-through vias with small dimensions and small separation/pitch is desired to further reduce the package size.
Furthermore, there will be material incompatibility between the ceramic in the casing of the package and the components inside, which often are silicon based, as for example MEMS (Microelectromechanical Systems) devices. Differences in e.g. thermal expansion coefficients can cause artefacts.SUMMARY OF THE INVENTION
The object of the invention is to enable further miniaturization of such packaged components.
This object is achieved by the method and the device as defined in the independent claims.
The present invention provides a method of micro-packaging a component. At least a first and second substrate is provided of which the first substrate is a semiconductor substrate being provided with at least one electrical through connection. A compartment is formed in either one or a plurality of the substrates by etching. A component is provided above the first semiconductor substrate so that it covers the at least one through wafer connections and will be located within the compartment. The component is connected to at least one through wafer connection and the substrates are joined to form a sealed micro-packaged device. P There may also be provided a plurality of through wafer connections. Preferably the substrates are semiconductor substrates. Preferably the substrates comprising through wafer connections are thick enough to easily be handled during the manufacturing.
A device according to present invention is a micro-packaged electronic or micromechanic device that comprises a thin walled casing which encloses a compartment. Electrical through connections through the bottom of the casing are connected to an electronic or micromechanic component and the micro-packaged device is hermetically sealed for maintaining a desired atmosphere, suitable vacuum inside. The casing is made of a semiconducting material and the component is located immediately above the through connections.
By the method according to the invention the thickness of packaged components can be reduced at least by 50%.
Hermetic sealing can be made at wafer-level using wafer bonding which significantly simplifies the manufacturing process thereby reducing costs.
Furthermore, a higher density of vias is possible in silicon based packages by using photolithography and etching processes than possible by using mechanical machining processes.
Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter and the accompanying drawings which are given by way of illustration only, and thus not to be considered limiting on the present invention.
Preferred embodiments of the invention will now be described with reference to the accompanying drawings, wherein
The invention is based on the use of electrical through connections (or “vias”), which enables connection of packaged micro-components to circuit boards or to other components with the provision of bulky connector legs or pins, and wafer-level hermetic encapsulation. The terms electrical through connection and via are interchangeably used in this application.
Preferably the starting wafers having said vias are semiconductor wafers, more preferably single crystalline silicon wafers, however not limited to this. The term “semiconductor wafer” also comprises other wafer materials typically used in the field, such as glass wafers and ceramic wafers. The terms wafer and substrate are interchangeably used throughout this application since processing preferably is made on wafer level, i.e. many devices are manufactured in parallel.
Preferably, the packaged component is made by using a wafer having been provided with vias in accordance with the teachings of the International Patent Publication WO 2004/084300 A1 (Silex Microsystems), the content of which is incorporated herein in its entirety. In particular the invention of WO2004/084300 relates to a method of making an electrical through connection between a first (top) and a second (bottom) surface of a semiconductor substrate. The method comprises creating a trench in the first surface and establishing an insulating enclosure entirely separating a portion of said substrate, defined by said trench, i.e. an insulated through connection. One product manufactured according the method is usable as a starting substrate, a so called interposer, for further manufacturing of micro-electronic and/or micro-mechanic devices. One advantage of this kind of product (interposer) is that the through connections are made of the wafer material and therefore are suitable for the processing usually applied to such wafers, i.e. the wafers can withstand temperatures, chemicals that commonly are used in conventional processing of semiconductor wafers. Another advantage of a wafer having these vias is that the wafer may have a thickness of 300-700 μm, which makes it possible to handle the wafers during the further processing.
For different applications, such as RF (radio frequency) applications comprising e.g. switches or resonators, there is a need for low resistivity through wafer connections. For such applications other via technologies than the one explained above using the wafer material or e.g. polysilicon as a conductor may have to be used. The international patent application WO 2007/089206 teaches a method to provide a wafer with closely spaced metallic through wafer connections. This wafer is also suitable as a starting substrate for further manufacturing of electronic and or micro-mechanic devices.
Another kind of starting substrates with pre-made vias is a so called SOI (silicon on insulator) wafer, wherein the pre-made vias are made in the device layer of the wafer, i.e. not extending entirely through the whole wafer. The through connections are instead exposed in subsequent process steps.
Thus, the starting substrate for the process according to the invention is a wafer 1 having pre-made vias 2, as can be seen in
The starting wafer should be thicker than about 300 μm in order to provide enough rigidity to enable handling of the wafer during processing without risk of breaking it. Preferably the starting wafer comprising the through wafer connections has a thickness of >100 μm, preferably >200 μm, more preferably >300 μm, still more preferred >400 μm, and most preferred >500 μm.
For the purpose of this application the term “compartment” 3 refers to a volume that has been formed in one or a plurality of substrates in order to receive a component, which subsequently is encapsulated therein. The compartment 3 may, before the encapsulation, be a depression 3a or a hole 3b in one or in a plurality of the substrates (1, 10, 11).
A suitable etch is applied to the patterned wafer, and a suitably shaped depression, typically rectangular but not limited to this, is thus formed in any of the via wafer or the lid wafer or in both. An advantage with an etching process as compared to the prior art milling, is that it is possible to make very sharp corners in the “box”-like depression, and furthermore silicon processing using lithography and etching enables making very small “boxes” with accurate dimensions. Then, a second pattern is applied to define mounting members corresponding to the vias 2, i.e. the surface of the vias 2 are covered with etch resistant material. A second etch is applied to etch a deeper depression, whereby protruding members 2 are formed. The depression is suitably 150 μm deep, and the height of the protruding members is suitably of the order 20 μm, but these measures can of course vary depending on the application in question.
On top of these protruding members 2 pads 5 or bumps of gold (Au), solder, AuSn., PbSn, etc. are formed by any suitable method such as plating, sputtering etc. If the box is made in the lid wafer 10 these bumps 5 are preferably made on the flat via wafer 1 which simplifies the manufacturing.
The component 4 to be mounted in the protective casing can be attached directly to the through wafer connections 2 e.g. by soldering, ultrasonic welding, gluing and wire bonding, in an automated processing using standard surface mounting machines. “Directly” is for the purpose of this application interpreted to mean that there is no additional routing needed to form a contact pad, but as illustrated in
On the other hand the gold can be applied to the layer 6-T and instead having the lid “silicon clean”, i.e. letting the silicon in the lid 10 bond to the gold on the component wafer 1.
A second method is to apply a gold layer on both the lid wafer 10 and the component wafer 1 and apply what is referred to as a thermocompression bonding process.
Thirdly, a solder (e.g. PbSn or AuSn) can be applied on one of the wafers (1, 10, 11) and gold on the other and a soldering process is made.
Optionally the bonded wafers can be grinded or polished to reduce the total thickness to a desired thickness suitable for the application in question. E.g. for mobile phones thin packages are essential.
On the back side of the wafer 1 an insulating layer 6-B of e.g. oxide, or any other suitable material is applied. This layer could have been applied before any other processing is done, as could the insulting layer 6-T on the top side of the wafer. In this layer 5 openings are made by patterning/etching to expose the via to enable contacting to other components or to a circuit board. Suitably there is provided a metallization 7 of e.g. Al that contacts the via material and can be provided as narrow contact strips from the via to the edges of the entire packaged structure.
This can be seen in the bottom view in
Although the figures show only one micro-packaged device, it is to be understood that there can be made several thousand items on one wafer in one batch. With this wafer-level packaging approach according to the invention it is possible on a wafer level to provide several thousands of micro-packaged components wherein the exterior dimensions can be made substantially smaller than with presently used technology.
In a final step in a manufacturing process the wafers are cut up in individual micro-packaged components by e.g. sawing.
Using the silicon via technology, disclosed in Swedish patent No. SE-526 366 (Silex) a great advantage can be obtained. Namely, the device can be substantially simplified since all lateral metal routing could be avoided because of the vias located immediately below each component. However, routing on both wafers (i.e. component and lid wafer, respectively) and both the front side and back side of the via wafer is still possible to do like in prior art techniques (compare
Wafer level encapsulation of these microstructures under vacuum (or other controlled ambient) is obtained by bonding the LID wafer and via wafer together. Among the different wafer level bonding alternatives are:
Au—Au for thermo compression bonding
AuSn, PbSn etc against Au etc for solder bonding
Au—Si for eutectic bonding
Si—Si, SiO—Si or SiO—SiO (or other alternative isolating materials such as SiN) for fusion bonding (optional plasma enhanced low temp bonding)
Si-glass for anodic bonding (optional Al on Si for Al/glass anodic bonding)
Among the many available ways of adding these bonding materials on the wafer are (but not limited to): conventional sputter/evaporation metallization followed by photolithography and etching, lift-off, shadow evaporation/sputtering, screen printing, preform.
Bonding alternatives as well as methods for applying the materials are well known for the skill man in art.
After the two wafers are bonded together processing as described in
For certain applications it may be necessary to provide wafer through connections by “vias” that are so closely spaced that it will be impossible to make separate vias having the necessary close pitch. A typical centre-to-centre distance for circular vias is about 250 μm, if trenches are 10-30 μm wide and the diameter of vias is 100 μm. The starting wafer is typically 300-450 μm in order to be processed without a handling wafer attached thereto. For such thickness of the wafer the typical trench width is 15-20 μm and the via diameter is about 50-100 μm.
Closely spaced through wafer connections can also be accomplished if using a SOI-substrate having a device layer thickness of about 50-200 μm, as illustrated in
However, referring to
However, in the process of making arrays of contiguous vias of this type, the problem of varying etch performance over the surface of a wafer is noticeable and will have an influence on the result. In order to make what is referred to as an “etch load compensation”, in accordance with an aspect of the invention there will always be made a redundant via at each end of the array. These outermost vias in the array will not be used in operation of the array, but are only present for the above mentioned reason. See
However, there is a further problem associated with the manufacture of this kind of via arrays. This problem occurs in the corners where trenches meet, i.e. at 58 in
A still further problem can occur with very long trenches, i.e. where the “via” itself occupies a large surface area on the wafer. Namely, in view of the trenches in a standard situation are about 8 μm wide, it will suffice if one single particle with conductive properties gets “caught” in the trench and forms a bridge between the via and the surrounding wafer material in order that the via will be short-circuited. The probability of this happening becomes increasingly larger as the length of the trench increases, and will inevitably cause high rejection rates and thus low manufacturing yields.
By making a trench structure introducing a redundancy, this problem can be ameliorated.
The way this is solved by the invention is as follows.
As illustrated in
As illustrated in
As illustrated in
In the first step of the manufacturing of the micro-packaged component in
In a micro-packaged device according to the present invention it is possible to obtain a controlled atmosphere, i.e. vacuum, protective gas, etc., in the sealed compartment. The long term stability of this controlled atmosphere is dependent on the gas permeability of the joint between the wafers of the package, the gas permeability of the wafers and release of gases from components or other structures enclosed within the compartment. Preferably a getter means 17 in the form of e.g. a plate, a thin film, a bump, etc. is enclosed within the compartment to remove gas molecules that find its way into the compartment. A person skilled in the art is familiar with the different getter materials used, since such is commonly used in other hermetically sealed devices.
There are several alternatives to the eutectic bonding that provide bonding at low temperatures, such as thermocompression bonding or solder bonding. AuSn to Au bonding is for example performed above 280° C. but there is other solders having lower melting temperature. Another alternative is plasma enhanced bonding, whereby the micro-packaged component has to withstand at least 400° C. There are also polymer bonding methods which can be used to join the substrates of the micro-packaged component.
One advantage with fusion bonded micro-packaged devices is that the package can be made even smaller. The fusion bonding provides a good sealing and the sealing area can be made smaller than for e.g. thermocompression bonding. Furthermore the bond strength may be so high that a possible breakage of the package will likely take place in the substrate and not in the joint between the substrates.
A micro-packaged device according to the invention can be made much smaller than a conventional micro-packaged device for a given component size. Usually ceramic materials are used to package and hermetically seal electrical and micromechanical components, but the smallest packages available are about 3×2 mm2 and with a thickness of more than 1 mm. This technology does not allow substantial miniaturisation. The present invention provides substantially smaller packages. The thickness is preferably less than 0.6 mm and the lateral dimensions are preferably less than 1×1 mm2, depending on the size of the component.
While the invention has been described in connection with what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention is not to be limited to the disclosed embodiments, on the contrary, is intended to cover various modifications and equivalent arrangements within the appended claims.
43. A method of micro-packaging a component (4), comprising the steps of:
- providing a plurality of substrates (1, 10, 11) comprising at least a first and a second substrate (1, 10), the first substrate (1) being a semiconductor substrate and being provided with an electrical through connection (2);
- forming a compartment (3) in at least one of the plurality of the substrates (1, 10, 11) by etching;
- providing the component (4) above the first semiconductor substrate (1) so that it covers at least the through connection (2);
- connecting the component (4) to the through connection (2); and
- joining the substrates (1, 10, 11) to form a sealed micro-packaged device (15).
44. The method of micro-packaging a component (4) according to claim 43, wherein the first substrate (1) is provided with a plurality of through connections (2).
45. The method of micro-packaging a component (4) according to claim 43, wherein the second substrate (10) is a semiconductor substrate.
46. The method of micro-packaging a component (4) according to claim 43, wherein one of the plurality of substrates (1, 10, 11) is an intermediate semiconductor substrate (11), interposed between the first and the second substrates (1, 10).
47. The method of micro-packaging a component (4) according to claim 43, wherein the first substrate (1) which is provided with electrical through connections (2) has a thickness of >100 μm, preferably >200 μm, more preferably >300 μm, still more preferred >400 μm, and most preferred >500 μm.
48. The method of micro-packaging a component (4) according to claim 43, wherein the step of providing the component (4) further comprises the step of attaching the component (4) directly to the through connections (2).
49. The method of micro-packaging a component (4) according to claim 48, further comprising the steps of:
- etching a depression (3a) in the first substrate (1) which is provided with electrical through connections (2), the depression (3a) defining the compartment (3); and
- sealing the depression (3a) with the second substrate (10).
50. The method of micro-packaging a component (4) according to claim 48, further comprising the steps of:
- etching a depression (3a) in the second substrate (10), the depression (3a) defining the compartment (3); and
- sealing the depression (3a) with the first substrate (1).
51. The method of micro-packaging a component (4) according to claim 48, further comprising the steps of:
- etching a depression (4a) in each of the first and the second substrates (1, 10), the depressions (3a) defining the compartment (3); and
- sealing the depressions (4a) by joining the substrates (1, 10).
52. The method of micro-packaging a component (4) according to claim 48, further comprising the steps of:
- etching a hole (3b) in the intermediate substrate (11), the hole (3b) defining the compartment (3); and
- sealing the compartment (3) by joining the substrates (1, 10, 11).
53. The method of micro-packaging a component (4) according to claim 49, further comprising the steps of:
- etching a hole (3b) in the intermediate substrate (11), the depression (3a)/depressions (3a) and the hole (3b) defining the compartment (3); and
- sealing the compartment (3) by joining the substrates (1, 10, 11).
54. The method of micro-packaging a component (4) according to claim 48, wherein the component (4) is a discrete component which is attached by surface mounting such as any of flip chip mounting, soldering, ultrasonic welding, thermocompression bonding, gluing, etc.
55. The method of micro-packaging a component (4) according to claim 48, wherein a depression (3) is made in the first substrate (1) by etching, and the component (4) is monolithically integrated in the depression in the first substrate (1) using surface micromachining or bulk micromachining, and wherein the second substrate (10) is a planar substrate forming a lid covering the depression (3).
56. The method of micro-packaging a component (4) according to claim 55, wherein the step of joining further comprises the step of fusion bonding the substrates.
57. The method of micro-packaging a component (4) according to claim 55, wherein the step of joining further comprises the step of anodic bonding the substrates.
58. The method of micro-packaging a component (4) according to claim 47, wherein the through connections (2) are extending entirely through the first substrate (1).
59. The method of micro-packaging a component (4) according to claim 47, wherein the through connections (2) are provided in a SOI substrate, the through connections (2) extending entirely through the device layer of the SOI substrate.
60. A micro-packaged electronic or micromechanic device (15) comprising a casing (13) which encloses a compartment (3); electrical through connections (2) through the bottom of the casing (13); and an electronic or micromechanic component (4) connected to the electrical through connections (2), the micro-packaged device (15) being hermetically sealed for maintaining a desired atmosphere, suitable vacuum inside, characterised in that the casing (13) is made of a semiconducting material comprising a first substrate (1), optionally an intermediate substrate (11), and a second substrate (10) forming a lid, and in that the component (4) is located immediately above and attached to the through connections (2).
61. The micro-packaged electronic or micromechanic device (15) according to claim 60, wherein the component (4) is directly attached to the through connections (2).
62. The micro-packaged electronic or micromechanic device (15) according to claim 61, wherein the component (4) is a discrete component attached by surface mounting such as any of flip chip mounting, soldering, ultrasonic welding, thermocompression bonding, gluing.
63. The micro-packaged electronic or micromechanic device (15) according to claim 61, wherein the component (4) is monolithically integrated with the casing (13) by surface micromachining or bulk micromachining.
64. The micro-packaged electronic or micromechanic device (15) according to claim 63, wherein the casing (13) is bonded by fusion bonding or anodic bonding.
65. The micro-packaged electronic or micromechanic device (15) according to claim 60, wherein the casing (13) comprises large contact areas (8) for surface mounting on an outer bottom surface.
International Classification: H01R 9/00 (20060101); H01L 21/302 (20060101);