To Change Their Surface-physical Characteristics Or Shape, E.g., Etching, Polishing, Cutting (epo) Patents (Class 257/E21.214)

  • Patent number: 10269836
    Abstract: A display apparatus includes a substrate and a plurality of pixels disposed on the substrate. Each pixel includes a gate electrode on the substrate, a common electrode insulated from the gate electrode on the substrate, a first insulating layer covering the gate electrode and the common electrode, a semiconductor pattern disposed on the first insulating layer to overlap with the gate electrode, source and drain electrodes disposed on the semiconductor pattern and spaced apart from each other, and a pixel electrode disposed on the first insulating layer to cover the drain electrode and form an electric field with the common electrode. The display apparatus may be manufactured by first to fourth photolithography processes using first to fourth masks, and the first mask may be a slit mask or a diffraction mask.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: April 23, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: JeongMin Park, Jung-Soo Lee, Ji-Hyun Kim, Sanggab Kim
  • Patent number: 10186602
    Abstract: The disclosure relates to a fin field effect transistor (FinFET). An exemplary FinFET comprises a substrate comprising a major surface; a fin structure protruding from the major surface comprising an upper portion comprising a first semiconductor material having a first lattice constant, wherein the upper portion comprises a first substantially vertical portion having a first width and a second substantially vertical portion having a second width less than the first width over the first substantially vertical portion; and a lower portion comprising a second semiconductor material having a second lattice constant less than the first lattice constant, wherein a top surface of the lower portion has a third width less than the first width; and a gate structure covering the second substantially vertical portion.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: January 22, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Yen-Yu Chen, Hung-Yao Chen, Chi-Yuan Shih, Ling-Yen Yeh, Clement Hsingjen Wann
  • Patent number: 10175588
    Abstract: Disclosed herein is a decompression processing apparatus for processing a wafer in a decompressed state including a chamber having a decompressing unit configured to decompress the inside of the chamber, an opening and closing door configured to open and close a carrying-in-and-out opening for carrying the wafer into and out of the chamber, and an inert gas supply source configured to supply an inert gas to the inside of the chamber. The inside of the chamber is maintained in a dry state by continuing to supply the inert gas in a state in which the opening and closing door is opened.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: January 8, 2019
    Assignee: Disco Corporation
    Inventor: Hidekazu Iida
  • Patent number: 10155294
    Abstract: A polishing unit of a polishing apparatus according to an embodiment includes: a polishing head having a pressing member configured to hold a polishing tape and press the polishing tape against a peripheral portion of a substrate from above; a tape supply and recovery mechanism configured to supply the polishing tape to the polishing head and recover the polishing tape from the polishing head; a first moving mechanism configured to move the polishing head in a radial direction of the substrate; and a second moving mechanism configured to move the tape supply and recovery mechanism in the radial direction of the substrate. The positioning unit includes a positioning block having a contacting surface, and alignment of the polishing tape is conducted by the second moving mechanism moving the tape supply and recovery mechanism so that a substrate-side edge of the polishing tape makes contact with the contacting surface.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: December 18, 2018
    Assignee: Ebara Corporation
    Inventors: Masaya Seki, Tetsuji Togawa, Kenya Ito
  • Patent number: 10121849
    Abstract: A semiconductor structure and a method of fabricating thereof are provided. The method includes the following steps. A substrate with an upper surface and a lower surface is received. A first recess extending from the upper surface to the lower surface is formed and the first recess has a first depth. A second recess extending from the upper surface to the lower surface is formed and the second recess has a second depth less than the first depth. A first conducting layer is formed in the first recess and the second recess. A first insulating layer is formed over the first conducting layer. A second conducting layer is formed over the first insulating layer and isolated from the first conducting layer with the first insulating layer. The substrate is thinned from the lower surface to expose the second conducting layer in the first recess.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: November 6, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Tieh-Chiang Wu, Shing-Yih Shih
  • Patent number: 10109527
    Abstract: An optical device wafer processing method includes a shield tunnel forming step of applying a pulsed laser beam having a transmission wavelength to a sapphire substrate along an area corresponding to each division line from the back side of the sapphire substrate in the condition where the focal point of the pulsed laser beam is set inside the sapphire substrate, thereby forming a plurality of shield tunnels arranged along the area corresponding to each division line, each shield tunnel being composed of a fine hole and an amorphous region formed around the fine hole for shielding the fine hole. The optical device wafer processing method further includes a dividing step of applying an external force to the optical device wafer after performing a light emitting layer forming step, thereby dividing the optical device wafer along the division lines to obtain the individual optical device chips.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: October 23, 2018
    Assignee: DISCO CORPORATION
    Inventors: Ryugo Oba, Takumi Shotokuji, Naotoshi Kirihara
  • Patent number: 10014245
    Abstract: A method for removing material from a substrate includes providing the substrate with first and second opposing major surfaces. A masking layer is disposed along one of the first major surface and the second major surface, and is provided with a plurality of openings. The substrate is placed within an etching apparatus and material is removed from the substrate through openings using the etching apparatus. The thickness of the substrate is measured within the etching apparatus using a thickness transducer. The measured thickness is compared to a predetermined thickness and the material removal step is terminated responsive to the measured thickness corresponding to the predetermined thickness. In one embodiment, the method is used to more accurately form recessed regions in semiconductor die, which can be used in, for example, stacked device configurations.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: July 3, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. Seddon, Francis J. Carney
  • Patent number: 10008695
    Abstract: A flexible display device includes a display module and a window member disposed on the display module. The window member includes a base film, elastomer patterns disposed on one surface of the base film, and a hard coating layer disposed on the one surface of the base film to cover the elastomer patterns.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: June 26, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventors: Youngsang Park, Inseo Kee, Jungho Park, Kyu-taek Lee, Chulho Jeong, Hwal Choi
  • Patent number: 9955949
    Abstract: A method for manufacturing a capacitive transducer is provided having a structure in which a vibrating film is supported to be able to vibrate. The method includes forming a sacrificial layer on a first electrode; forming a layer on the sacrificial layer, the layer forming at least part of the vibrating film; removing the sacrificial layer, including forming etching holes to communicate with the sacrificial layer; forming a sealing layer for sealing the etching holes; and etching at least part of the sealing layer. Before forming the sealing layer, an etching stop layer is formed on the layer forming at least part of the vibrating film. In the step of etching at least part of the sealing layer, the sealing layer is removed until the etching stop layer is reached.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: May 1, 2018
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kazutoshi Torashima, Takahiro Akiyama, Kenji Hasegawa, Kazuhiko Kato
  • Patent number: 9929326
    Abstract: According to some embodiments of the invention, a light-emitting device package includes a body including top and bottom surfaces and a cavity in the body, the cavity extending from the top surface towards the bottom surface and having a floor. The light-emitting device package also includes a plurality of LED (light-emitting-diode) dies disposed on the floor of the cavity. A socket is formed over the plurality of LED dies. The socket includes a top surface, a socket sidewall, and a bottom surface, the socket sidewall disposed between the top surface and the bottom surface of the socket. A lens is disposed over the over the socket. The lens includes two or more optical materials with different indices of refraction. The lens includes a cap and a plug. The cap has an upper surface and a lower surface, and the plug has a lower surface and a plug sidewall between the lower surface of the plug and the lower surface of the cap.
    Type: Grant
    Filed: May 1, 2015
    Date of Patent: March 27, 2018
    Assignee: LedEngin, Inc.
    Inventor: Xiantao Yan
  • Patent number: 9914196
    Abstract: A polishing unit of a polishing apparatus according to an embodiment includes: a polishing head having a pressing member configured to hold a polishing tape and press the polishing tape against a peripheral portion of a substrate from above; a tape supply and recovery mechanism configured to supply the polishing tape to the polishing head and recover the polishing tape from the polishing head; a first moving mechanism configured to move the polishing head in a radial direction of the substrate; and a second moving mechanism configured to move the tape supply and recovery mechanism in the radial direction of the substrate. The positioning unit includes a positioning block having a contacting surface, and alignment of the polishing tape is conducted by the second moving mechanism moving the tape supply and recovery mechanism so that a substrate-side edge of the polishing tape makes contact with the contacting surface.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: March 13, 2018
    Assignee: Ebara Corporation
    Inventors: Masaya Seki, Tetsuji Togawa, Kenya Ito
  • Patent number: 9902137
    Abstract: A thin metal substrate having high thermal conductivity includes a copper foil layer, an insulating polymer layer and a thermal conductive adhesive layer. The thermal conductive adhesive layer has a resin and a thermal conductive powder dispersed in the resin. The insulating polymer layer is disposed between the copper foil layer and the thermal conductive adhesive layer. Since the thermal conductive adhesive layer has the thermal conductive powder and the insulating polymer layer has insulating and anti-breakdown abilities, the substrate has a reduced thickness, high heat dissipating efficiency and improved insulating performance.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: February 27, 2018
    Assignee: AISA ELECTRONIC MATERIAL CO., LTD
    Inventors: Meng Hao Chang, Chien Hui Lee, J. King Chen
  • Patent number: 9808903
    Abstract: A polishing method which can remove foreign matters from an entire back surface of a substrate at a high removal rate is provided. The polishing method includes placing a polishing tool in sliding contact with an outer circumferential region of a back surface of a substrate while holding a center-side region of the back surface of the substrate, and placing a polishing tool in sliding contact with the center-side region of the back surface of the substrate while holding a bevel portion of the substrate to polish the back surface in its entirety.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: November 7, 2017
    Assignee: EBARA CORPORATION
    Inventors: Yu Ishii, Kenya Ito, Masayuki Nakanishi, Tetsuji Togawa
  • Patent number: 9780021
    Abstract: To provide a method of manufacturing an element chip in which creep-up of a conductive material can be suppressed in a mounting step. In a plasma processing step that is used in the method of manufacturing the element chip for manufacturing a plurality of element chips by dividing a substrate which has a plurality of element regions and of which an element surface is covered by an insulating film, the substrate is divided into the element chips by exposing the substrate to a first plasma, the element chips having a first surface, a second surface, and a side surface are held spaced from each other on a carrier, and the side surface and the insulating film are in a state of being exposed.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: October 3, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Atsushi Harikai, Shogo Okita, Noriyuki Matsubara
  • Patent number: 9748089
    Abstract: A method for producing mirror-polished wafer, the method produces a plurality of mirror-polished wafers by performing, on plurality of silicon wafers obtained by slicing a silicon ingot, slicing strain removing step of removing strain on a surface caused by slicing, etching step of removing strain caused by the slicing strain removing step, and double-side polishing step of performing mirror polishing on both surfaces of the silicon wafers subjected to etching, each step being performed by batch processing, wherein silicon wafers which are processed in double-side polishing step by batch processing are selected from silicon wafers processed in same batch in the slicing strain removing step and the number of silicon wafers to be selected is made to be equal to the number of silicon wafers processed in the slicing strain removing step or submultiple thereof. As a result, a method that can produce mirror-polished wafers having high flatness is provided.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: August 29, 2017
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Hiromasa Hashimoto, Yoshihiro Usami, Kazuaki Aoki, Shigeru Oba
  • Patent number: 9679789
    Abstract: A wafer in which a modified layer is internally formed along planned dividing lines is placed on a placement table and a water tank allows the wafer placed on the placement table to be submerged in cleaning water. An ultrasonic supply unit supplies ultrasonic waves to the wafer submerged in the cleaning water. By the ultrasonic waves supplied by the ultrasonic supply unit, the wafer is divided along the planned dividing lines and is turned into small pieces to generate plural chips and the generated chips are cleaned.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: June 13, 2017
    Assignee: Disco Corporation
    Inventor: Tsukuru Obata
  • Patent number: 9673096
    Abstract: According to various embodiments, a method for processing a semiconductor substrate may include: covering a plurality of die regions of the semiconductor substrate with a metal; forming a plurality of dies from the semiconductor substrate, wherein each die of the plurality of dies is covered with the metal; and, subsequently, annealing the metal covering at least one die of the plurality of dies.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: June 6, 2017
    Assignees: INFINEON TECHNOLOGIES AG, Technische Universitaet Graz
    Inventors: Joachim Hirschler, Michael Roesner, Markus Juch Heinrici, Gudrun Stranzl, Martin Mischitz, Martin Zgaga
  • Patent number: 9659805
    Abstract: A method includes forming an adhesive layer over a carrier, forming a sacrificial layer over the adhesive layer, forming through-vias over the sacrificial layer, and placing a device die over the sacrificial layer. The Method further includes molding and planarizing the device die and the through-vias, de-bonding the carrier by removing the adhesive layer, and removing the sacrificial layer.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: May 23, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hsiang (James) Hu, Chung-Shi Liu, Hung-Jui Kuo, Ming-Da Cheng
  • Patent number: 9541806
    Abstract: A method for forming a thin film pattern includes: forming a first resist pattern on a substrate; forming a second resist pattern on the substrate and the first resist pattern, forming a first metal layer overlapping an exposed portion of the substrate and exposed portions of the first and second resist patterns; removing the second resist pattern and a portion of the first metal layer, through a first lift-off process to expose portions of the substrate and the first resist pattern; forming a second metal layer overlapping portions of each of the substrate, the first resist pattern and the first metal layer; and removing the first resist pattern and the first and second metal layers, through a second lift-off process, to form first and second metal patterns from remaining portions of the first and second metal layers. The first and second resist patterns have different dissolution characteristics.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: January 10, 2017
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Jun Hwang
  • Patent number: 9493890
    Abstract: Growth of GaP and III-V GaP alloys in the wurtzite crystal structure by vapor phase epitaxy (VPE) is provided. Such material has a direct band gap and is therefore much more useful for optoelectronic devices than conventional GaP and GaP alloys having the zincblende crystal structure and having an indirect band gap.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: November 15, 2016
    Assignee: Technische Universiteit Eindhoven
    Inventors: Simone Assali, Ilaria Zardo, Jozef Everardus Maria Haverkort, Erik Petrus Antonius Maria Bakkers
  • Patent number: 9484210
    Abstract: In one embodiment, semiconductor die are singulated from a semiconductor wafer having a backmetal layer by placing the semiconductor wafer onto a carrier tape with the backmetal layer adjacent the carrier tape, forming singulation lines through the semiconductor wafer to expose the backmetal layer within the singulation lines, and separating portions of the backmetal layer using a fluid.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: November 1, 2016
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: William F. Burghout, Dennis Lee Conner, Michael J. Seddon, Jay A. Yoder, Gordon M. Grivna
  • Patent number: 9484324
    Abstract: A semiconductor device includes a first semiconductor chip including a first surface, a second surface and a first terminal arranged on the first surface, a second semiconductor chip including a first surface, a second surface and a second terminal arranged on the first surface of the second semiconductor chip, a support substrate including a first surface bonded to the second surfaces of the first semiconductor chip and the second semiconductor chip, and an isolation groove formed on the first surface of the support substrate. The isolation includes a pair of side surfaces continuously extending from opposing side surfaces of the first semiconductor chip and the second semiconductor chip, respectively, and the isolation groove is formed into the support substrate to extend from the first surface of the support substrate. The isolation groove has a depth less than a thickness of the support substrate.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: November 1, 2016
    Assignee: Rohm Co., Ltd.
    Inventor: Toshio Nakasaki
  • Patent number: 9455211
    Abstract: A package includes a molding compound, a through-via penetrating through the molding compound, a device die molded in the molding compound, and a buffer layer on and contacting the molding compound. An opening is through the buffer layer to the through-via. The buffer layer has ripples in a plane parallel to an interface between the molding compound and the buffer layer and around a circumference of the opening. Other embodiments contemplate an additional package bonded to the package, and methods for forming the package.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: September 27, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wu Sen Chiu, Li-Hui Cheng, Po-Hao Tsai, Jing-Cheng Lin
  • Patent number: 9437820
    Abstract: A substrate laminating low film, a substrate laminated structure and a method of manufacturing an organic light emitting display are disclosed. One inventive aspect includes a base member, a first adhesion layer formed on the base member, and a second adhesion layer formed on the first adhesion layer. The second adhesion layer has a second adhesion strength less than the first adhesion strength of the first adhesion layer.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: September 6, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventor: Jin Han Park
  • Patent number: 9422462
    Abstract: An adhesive sheet of the invention includes a substrate and an adhesive composition laminated thereon, the substrate including polyvinyl chloride and a polyester-based plasticizer, wherein the adhesive composition includes two different (meth)acrylate copolymer components (A) and (B) in a mass ratio ranging from 10:90 to 90:10, wherein a content of a cross-linking agent which reacts with functional groups of the component (A) and the component (B) is in a range of 0.5 to 20 mass parts with respect to 100 mass parts of a sum of the component (A) and the component (B), and wherein 10 to 95 mass % of the monomer unit composing the component (A) is 2-ethylhexyl acrylate, and 10 to 95 mass % of the monomer unit composing the component (B) is butyl acrylate.
    Type: Grant
    Filed: May 28, 2012
    Date of Patent: August 23, 2016
    Assignee: DENKA COMPANY LIMITED
    Inventors: Takeshi Saito, Tomomichi Takatsu
  • Patent number: 9368407
    Abstract: A method for separating a layer for transfer includes forming a crack guiding layer on a substrate and forming a device layer on the crack-guiding layer. The crack guiding layer is weakened by exposing the crack-guiding layer to a gas which reduces adherence at interfaces adjacent to the crack guiding layer. A stress inducing layer is formed on the device layer to assist in initiating a crack through the crack guiding layer and/or the interfaces. The device layer is removed from the substrate by propagating the crack.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: June 14, 2016
    Assignee: GlobalFoundries, Inc.
    Inventors: Stephen W. Bedell, Cheng-Wei Cheng, Devendra K. Sadana, Katherine L. Saenger, Kuen-Ting Shiu
  • Patent number: 9343314
    Abstract: A method of making a split gate non-volatile memory (NVM) includes forming a charge storage layer on the substrate, depositing a first conductive layer, and depositing a capping layer. These layers are patterned to form a control gate stack. A second conductive layer is deposited over the substrate and is patterned to leave a first portion of the second conductive layer over a portion of the control gate stack and adjacent to a first side of the control gate stack. The first portion of the second conductive layer and the control gate stack are planarized to leave a dummy select gate from the first portion of the second conductive layer, where a top surface of a remaining portion of the first conductive layer is lower relative to a top surface of the dummy select gate. The dummy select gate is replaced with a select gate including metal.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: May 17, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Konstantin V. Loiko, Brian A. Winstead
  • Patent number: 9224744
    Abstract: A NAND flash memory chip includes narrow word lines that are directly patterned from sidewall spacers and larger structures that are patterned from sidewall spacers with covering material. Sidewall spacers with covering material define wider features than sidewalls alone. Closely spaced sidewalls with covering material define large structures such as contact pads and select lines.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: December 29, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Toshiya Yokota, Chia-Lin Hsiung, Fumiaki Toyama
  • Patent number: 9041177
    Abstract: Various embodiments of the present invention include a semiconductor device, the semiconductor device including a first semiconductor chip disposed on a substrate, a first sealing resin sealing the first semiconductor chip, a built-in semiconductor device disposed on the first sealing resin, and a second sealing resin sealing the first sealing resin and the built-in semiconductor device and covering a side surface of the substrate. According to an aspect of the present invention, it is possible to provide a high-quality semiconductor device, in which downsizing and cost reduction can be realized.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: May 26, 2015
    Assignee: VALLEY DEVICE MANAGEMENT
    Inventors: Masanori Onodera, Kouichi Meguro, Junji Tanaka
  • Patent number: 9040425
    Abstract: Methods of forming integrated circuit devices include forming a sacrificial layer on a handling substrate and forming a semiconductor active layer on the sacrificial layer. A step is performed to selectively etch through the semiconductor active layer and the sacrificial layer in sequence to define an semiconductor-on-insulator (SOI) substrate, which includes a first portion of the semiconductor active layer. A multi-layer electrical interconnect network may be formed on the SOI substrate. This multi-layer electrical interconnect network may be encapsulated by an inorganic capping layer that contacts an upper surface of the first portion of the semiconductor active layer. A step can be performed to selectively etch through the capping layer and the first portion of the semiconductor active layer to thereby expose the sacrificial layer.
    Type: Grant
    Filed: July 17, 2014
    Date of Patent: May 26, 2015
    Assignee: Semprius, Inc.
    Inventors: Christopher Bower, Etienne Menard, Matthew Meitl, Joseph Carr
  • Patent number: 9035319
    Abstract: The present disclosure relates to nitride semiconductor and a fabricating method thereof, and a nitride semiconductor according to an exemplary embodiment of the present disclosure includes a nitride based first and second electrode placed with a distance on a substrate, a nitride based channel layer which connects the first and second electrode, an insulating layer which covers the channel layer, and a third electrode which is formed to cover the insulating layer on the insulating layer.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: May 19, 2015
    Assignee: KYUNGPOOK NATIONAL UNIVERSITY INDUSTRY-ACADEMIC COOPERATION FOUNDATION
    Inventors: Jung-hee Lee, Ki-sik Im, Dong-seok Kim, Hee-sung Kang, Dong-hyeok Son
  • Patent number: 9034733
    Abstract: In one embodiment, semiconductor die are singulated from a semiconductor wafer having a backmetal layer by placing the semiconductor wafer onto a carrier tape with the backmetal layer adjacent the carrier tape, forming singulation lines through the semiconductor wafer to expose the backmetal layer within the singulation lines, and separating portions of the backmetal layer within the singulation lines using a pressurized fluid applied to the carrier tape.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: May 19, 2015
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: William F. Burghout, Dennis Lee Conner, Michael J. Seddon, Jay A. Yoder, Gordon M. Grivna
  • Patent number: 9035418
    Abstract: A shallow trench isolation (STI) structure includes a top surface formed completely of silicon nitride. The top surface of the STI structure is coplanar with a top substrate surface or extends above the top substrate surface. The STI structures include further dielectric materials beneath the silicon nitride and an oxide liner and any portions that extend above the substrate surface are formed of silicon nitride.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: May 19, 2015
    Assignee: WAFERTECH, LLC
    Inventors: Daniel Piper, Franklin Chiang, Ganesh Yerubandi
  • Patent number: 9013008
    Abstract: A semiconductor structure has embedded stressor material for enhanced transistor performance. The method of forming the semiconductor structure includes etching an undercut in a substrate material under one or more gate structures while protecting an implant with a liner material. The method further includes removing the liner material on a side of the implant and depositing stressor material in the undercut under the one or more gate structures.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: April 21, 2015
    Assignee: International Business Machines Corporation
    Inventors: Xi Li, Viorel C. Ontalus
  • Patent number: 8999844
    Abstract: Methods for forming semiconductor structures are disclosed, including a method that involves forming sets of conductive material and insulating material, forming a first mask over the sets, forming a first number of contact regions, forming a second mask over a first region of the sets, and removing material from of the sets in a second, exposed region laterally adjacent the first region to form a second number of contact regions. Another method includes forming first and second contact regions on portions of sets of conductive materials and insulating materials, each of the second contact regions more proximal to an underlying substrate than each of the first contact regions. Apparatuses such as memory devices including laterally adjacent first and second regions each of which including contact regions of a different portion of a plurality of conductive materials and related methods of forming such devices are also disclosed.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: April 7, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Eric H. Freeman, Michael A. Smith
  • Patent number: 8993362
    Abstract: A method and structure for fabricating a monolithic integrated MEMS device. The method includes providing a substrate having a surface region and forming at least one conduction material and at least one insulation material overlying at least one portion of the surface region. At least one support structure can be formed overlying at least one portion of the conduction and insulation surface regions, and at least one MEMS device can be formed overlying the support structure(s) and the conduction and insulation surface regions. In a variety of embodiments, the support structure(s) can include dielectric or oxide materials. The support structure(s) can then be removed and a cover material can be formed overlying the MEMS device(s), the conduction and insulation materials, and the substrate. In various embodiments, the removal of the support structure(s) can be accomplished via a vapor etching process.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: March 31, 2015
    Assignee: mCube Inc.
    Inventor: Anthony F. Flannery, Jr.
  • Patent number: 8993449
    Abstract: There is provided an etching method which can form trenches or via holes having desired aspect ratios and shapes in a to-be-processed object made of silicon. The etching method includes: a hydrogen halide-containing gas-based etching step of etching a silicon substrate by introducing a hydrogen halide-containing gas into a vacuum chamber; a fluorine-containing gas-based etching step of etching the silicon substrate by introducing a fluorine-containing gas into the vacuum chamber; a protective film formation step forming a protective film on the silicon substrate by sputtering a solid material; and a protective film removal step of removing part of the protective film by applying radio frequency bias power to a substrate electrode. The fluorine-containing gas-based etching step, the protective film formation step, and the protective film removal step are repeatedly performed in this order.
    Type: Grant
    Filed: August 12, 2010
    Date of Patent: March 31, 2015
    Assignee: Ulvac, Inc.
    Inventors: Yasuhiro Morikawa, Koukou Suu
  • Patent number: 8993451
    Abstract: Etch stabilizing ions (37) are introduced, e.g., by ion implantation (34), into a portion (36) of a substrate (20) underlying an etch window (24) in a masking layer (22) covering the substrate (20), where a trench (26) is desired to be formed. When the portion (36) of the substrate (20) containing the etch stabilizing ions (37) is etched to form the trench (26), the etch stabilizing ions (37) are progressively released at the etch interface (28?) as etching proceeds, substantially preventing gas micro-bubbles or other reaction products at the etch interface (28?) from disrupting etching. Using this method (700), products containing trenches (26) are much more easily formed and such trenches (26) have much smoother interior surface (28).
    Type: Grant
    Filed: April 15, 2011
    Date of Patent: March 31, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Srivatsa G. Kundalgurki, James F. McHugh
  • Patent number: 8980748
    Abstract: A substrate polishing method, a semiconductor device and a fabrication method for a semiconductor device are disclosed by which high planarization polishing can be achieved. In the substrate polishing method, two or more different slurries formed from ceria abrasive grains having different BET values from each other are used to carry out two or more stages of chemical-mechanical polishing processing of a polishing object oxide film on a substrate to flatten the polishing object film.
    Type: Grant
    Filed: January 3, 2008
    Date of Patent: March 17, 2015
    Assignee: Sony Corporation
    Inventors: Hiroko Nakamura, Takaaki Kozuki, Takayuki Enomoto, Yuichi Yamamoto
  • Patent number: 8975106
    Abstract: A method for forming a chip package includes: providing a substrate having a first and a second surfaces; removing a portion of the substrate to form openings in the substrate, wherein the openings extend from the first surface towards the second surface or from the second surface towards the first surface; after forming the openings, at least a first portion of the substrate serves as a first movable bulk, and at least a second portion of the substrate serves as a second movable bulk, wherein the first movable bulk and the second movable bulk are respectively located between the openings; disposing a protecting substrate on the second surface of the substrate; forming a through-hole in the protecting substrate; and forming a conducting layer on the protecting substrate, wherein the conducting layer extends from a surface of the protecting substrate into the through-hole to electrically connect the second movable bulk.
    Type: Grant
    Filed: July 5, 2011
    Date of Patent: March 10, 2015
    Inventor: Chien-Hung Liu
  • Patent number: 8969207
    Abstract: One illustrative method disclosed herein includes forming a patterned hard mask layer comprised of a plurality of discrete openings above a structure, wherein the patterned hard mask layer is comprised of a plurality of intersecting line-type features, forming a patterned etch mask above the patterned hard mask layer that exposes at least one, but not all, of the plurality of discrete openings, and performing at least one etching process through the patterned etch mask and the at least one exposed opening in the patterned hard mask layer to define an opening in the structure.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: March 3, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Gerard M. Schmid, Jeremy A. Wahl, Richard A. Farrell, Chanro Park
  • Patent number: 8963820
    Abstract: A semiconductor device includes: a trimming object circuit configured to use a trimming circuit to adjust an output based on a trimming value; and a trimming value setting circuit configured to set the trimming value. The trimming value setting circuit includes: a register configured to volatilely store a pseudo-trimming value set with reference to a trimming table such that an output value of the trimming object circuit becomes equal to a target value; a trimming value storage configured to non-volatilely store a final trimming value, wherein the final trimming value is set by correcting the pseudo-trimming value with reference to a trimming value correction table such that the output value of the trimming object circuit, which is obtained based on the pseudo-trimming value, becomes equal to the target value; and a selector configured to select one of the pseudo-trimming value and the final trimming value as the trimming value.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: February 24, 2015
    Assignee: Rohm Co., Ltd.
    Inventors: Takateru Yamamoto, Dai Onimatsu
  • Patent number: 8956498
    Abstract: A method for removing material from surfaces of at least a portion of at least one recess or at least one aperture extending into a surface of a substrate includes pressurizing fluid so as to cause the fluid to flow into the at least one recess or the at least one aperture. The fluid may be pressurized by generating a pressure differential across the substrate, which causes the fluid to flow into or through the at least one aperture or recess. Apparatus for pressurizing fluid so as to cause it to flow into or through recesses or apertures in a substrate are also disclosed.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: February 17, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Ross S. Dando
  • Patent number: 8956976
    Abstract: A method of processing a semiconductor substrate in forming scribe line alignment marks includes forming pitch multiplied non-circuitry features within scribe line area of a semiconductor substrate. Individual of the features, in cross-section, have a maximum width which is less than a minimum photolithographic feature dimension used in lithographically patterning the substrate. Photoresist is deposited over the features. Such is patterned to form photoresist blocks that are individually received between a respective pair of the features in the cross-section. Individual of the features of the respective pairs have a laterally innermost sidewall in the cross-section. Individual of the photoresist blocks have an opposing pair of first pattern edges in the cross-section that are spaced laterally inward of the laterally innermost sidewalls of the respective pair of the features.
    Type: Grant
    Filed: February 4, 2014
    Date of Patent: February 17, 2015
    Assignee: Micron Technology, Inc.
    Inventors: William R. Brown, David Kewley, Adam Olson
  • Patent number: 8946054
    Abstract: A method for separating a layer for transfer includes forming a crack guiding layer on a substrate and forming a device layer on the crack-guiding layer. The crack guiding layer is weakened by exposing the crack-guiding layer to a gas which reduces adherence at interfaces adjacent to the crack guiding layer. A stress inducing layer is formed on the device layer to assist in initiating a crack through the crack guiding layer and/or the interfaces. The device layer is removed from the substrate by propagating the crack.
    Type: Grant
    Filed: April 19, 2013
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Cheng-Wei Cheng, Devendra K. Sadana, Katherine L. Saenger, Kuen-Ting Shiu
  • Patent number: 8946749
    Abstract: A semiconductor light emitting device includes a substrate having a wiring pattern formed thereon, and a semiconductor light emitting element mounted on one main surface of the substrate and electrically connected to the wiring pattern. The substrate has, on the one main surface, a serrated structure reflecting at least part of light emitted from said semiconductor light emitting element to the substrate, to a direction perpendicular to the one main surface.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: February 3, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Katsuji Iguchi
  • Patent number: 8932936
    Abstract: A method for fabricating a device is disclosed. An exemplary method includes providing a substrate and forming a plurality of fins over the substrate. The method further includes forming a first opening in the substrate in a first longitudinal direction. The method further includes forming a second opening in the substrate in a second longitudinal direction. The first and second longitudinal directions are different. The method further includes depositing a filling material in the first and second openings.
    Type: Grant
    Filed: April 17, 2012
    Date of Patent: January 13, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chu Liu, Kuei-Shun Chen, Chih-Hsiung Peng, Chi-Kang Chang, Chiang Mu-Chi, Sheng-Yu Chang, Hua Feng Chen, Chao-Cheng Chen, Ryan Chia-Jen Chen
  • Patent number: 8927319
    Abstract: There is disclosed methods of making photosensitive devices, such as flexible photovoltaic (PV) devices, through the use of epitaxial liftoff. Also described herein are methods of preparing flexible PV devices comprising a structure having a growth substrate, wherein the selective etching of protective layers yields a smooth growth substrate that us suitable for reuse.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: January 6, 2015
    Assignee: The Regents of the University of Michigan
    Inventors: Stephen R. Forrest, Jeramy Zimmerman, Kyusang Lee, Kuen-Ting Shiu
  • Patent number: 8927999
    Abstract: An edge terminated semiconductor device is described including a GaN substrate; a doped GaN epitaxial layer grown on the GaN substrate including an ion-implanted insulation region, wherein the ion-implanted region has a resistivity that is at least 90% of maximum resistivity and a conductive layer, such as a Schottky metal layer, disposed over the GaN epitaxial layer, wherein the conductive layer overlaps a portion of the ion-implanted region. A Schottky diode is prepared using the Schottky contact structure.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: January 6, 2015
    Assignee: Avogy, Inc.
    Inventors: Isik C. Kizilyalli, Hui Nie, Andrew P. Edwards, Linda Romano, David Bour, Richard J. Brown, Thomas R. Prunty
  • Patent number: 8906730
    Abstract: A method of modifying stress characteristics of a membrane in one embodiment includes providing a membrane layer, determining a desired stress modification, and forming at least one trough in the membrane layer based upon the determined desired stress modification.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: December 9, 2014
    Assignee: Robert Bosch GmbH
    Inventors: Andrew B. Graham, Gary Yama, Gary O'Brien