Complementary Mis (epo) Patents (Class 257/E27.062)
  • Patent number: 10402529
    Abstract: A method of designing a layout includes identifying a cell having a cell height being a non-integral multiple of a minimum pitch, generating, using a processor, possibilities of an ordered arrangement of a plurality of virtual grid lines parallel to the top boundary and the bottom boundary, and placing at least two conductive patterns on the plurality of virtual grid lines. The cell height is defined by a top boundary and a bottom boundary, and the minimum pitch is based on a manufacturing process. The plurality of virtual grid lines are separated from each other by a plurality of spacings, and the top boundary overlaps a first virtual grid line of the plurality of virtual grid lines and the bottom boundary overlaps a second virtual grid line of the plurality of virtual grid lines. At least one spacing is different from another spacing of the plurality of spacings.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: September 3, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Mahantesh Hanchinal, Chi Wei Hu, Min-Yuan Tsai, Shu-Yi Ying
  • Patent number: 10389359
    Abstract: Apparatuses for providing buffer circuits a semiconductor device are described. An example apparatus includes a plurality of inverters and a transistor having one diffusion region coupled to a diffusion region of a transistor of one inverter of the plurality of inverters, another diffusion region coupled to a diffusion region of a transistor of another inverter of the plurality of inverters. The transistor having a gate coupled to one power supply voltage and diffusion regions coupled to another power supply voltage functions as a power voltage compensation capacitor.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: August 20, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Hiroki Hosaka, Satoru Sugimoto, Hayato Oishi
  • Patent number: 10355694
    Abstract: A level shifting circuit receives a first input signal and complement of the first input signal as inputs and generates a level shifted first output signal and complement of the first output signal as outputs. The level shifting circuit includes a number of transistors that support body biasing. One set of body bias signals applied to certain ones of those transistors is generated as a function of the logical combination of the first input signal and the first output signal. Another set of body bias signals applied to certain other ones of those transistors is generated as a function of the logical combination of the complement of the first input signal and the complement of the first output signal. The conditional body bias applied to the transistors of the level shifting circuit makes the circuit operational for level shift at very low supply voltage levels.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: July 16, 2019
    Assignee: STMicroelectronics International N.V.
    Inventor: Ravinder Kumar
  • Patent number: 10333497
    Abstract: A calibration circuit is connected to an input/output driver, a voltage bias generator is connected to the calibration circuit and the input/output driver, and a temperature sensor is connected to the voltage bias generator. The calibration circuit and input/output driver each include a bank of resistors and corresponding switches. Bodies of the switches are connected to the voltage bias generator, and the switches are biased by a bias signal output from the voltage bias generator. The calibration circuit includes a comparator device connected to the switches and to a reference resistor. Activation and deactivation of selected ones of the switches is made to match the reference resistor. Also, the voltage bias generator adjusts the bias signal when a temperature change is sensed by the temperature sensor. Thus, the switches change current flow as the bias signal changes, without changing which of the switches are activated or deactivated.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: June 25, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Anil Kumar, Mahbub Rashed, Sushama Davar, Navneet Jain
  • Patent number: 10290653
    Abstract: An integrated circuit layout structure having dual-height standard cells includes at least a first standard cell including a first cell height and at least a second standard cell including a second cell height. The second cell height is one half of the first cell height. The first standard cell includes one first doped region formed in a middle of the first standard cell and a plurality of second doped regions formed at a top side and a bottom side of the first standard cell. The first doped region includes a first conductivity type and the second doped regions include a second conductivity type complementary to the first conductivity type. And an area of the first doped region is smaller than an area of the total second doped regions.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: May 14, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Hung Chen, Chun-Hsien Wu
  • Patent number: 10211834
    Abstract: A low-voltage-drop rectifier circuit includes a first MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a second MOSFET, a comparator, and a level adjustment circuit. The first MOSFET has a gate terminal for receiving a control voltage, a source terminal connected to a connection node, a drain terminal connected to an input node, and a body terminal connected to the connection node. The second MOSFET has a gate terminal for receiving the control voltage, a source terminal connected to an output node, a drain terminal connected to the connection node, and a body terminal connected to the output node. The comparator generates a first comparison voltage and a second comparison voltage according to an input voltage at the input node and an output voltage at the output node. The level adjustment circuit generates and fine-tunes the control voltage according to the first comparison voltage and the second comparison voltage.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: February 19, 2019
    Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
    Inventor: Yeong-Sheng Lee
  • Patent number: 10177166
    Abstract: An integrated circuit includes a complex logic cell. The complex logic cell includes a first logic circuit providing a first output signal from a first input signal group and a common input signal group, and a second logic circuit providing a second output signal from a second input signal group and the common input signal group. The first and second logic circuits respectively include first and second transistors formed from a gate electrode, the gate electrode extending in a first direction and receiving a first common input signal of the common input signal group.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: January 8, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ju-Hyun Kang, Hyun Lee, Min-Su Kim, Ji-Kyum Kim, Jong-Woo Kim
  • Patent number: 9985016
    Abstract: A charge pump comprises one or more pump stages for providing a negative boosted output voltage. Each of the one or more pump stages comprises a P-channel transistor formed in an isolated P-well and an N-channel transistor coupled in series with the P-channel transistor. Forming the P-channel transistor in the isolated P-well essentially eliminates a raised threshold voltage due to body effect.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: May 29, 2018
    Assignee: NXP USA, INC.
    Inventors: Jon S. Choy, Michael G. Neaves
  • Patent number: 9941394
    Abstract: The tunnel field-effect transistor includes a drain layer, a source layer, a channel layer, a metal gate layer, and a high-k dielectric layer. The drain and source layers are of opposite conductive types. The channel layer is disposed between the drain layer and the source layer. At least one of the drain layer, the channel layer, and the source layer has a substantially constant doping concentration. The metal gate layer is disposed around the channel layer. The high-k dielectric layer is disposed between the metal gate layer and the channel layer.
    Type: Grant
    Filed: August 14, 2014
    Date of Patent: April 10, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Teng-Chun Tsai, Cheng-Tung Lin, Li-Ting Wang, Chih-Tang Peng, De-Fang Chen, Hung-Ta Lin, Chien-Hsun Wang
  • Patent number: 9830417
    Abstract: An electronic circuit design system for generating a programmable set of figures of an electronic circuit layout is provided. The system includes a non-transitory machine-readable layout database storing an electronic circuit layout of an electronic circuit design. The system further includes a circuit designer interface for viewing representations of the electronic circuit layout on a display unit and receiving inputs by one or more electronic circuit designers. The system further includes a processor configured to generate a figure group in the electronic circuit layout of the electronic circuit design; generate one or more templates comprising one or more parameters and a programming language code; and generate a parameterized figure group by associating the one or more templates to the figure group.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: November 28, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventors: Arnold Ginetti, Jean-Noel Pic, Alexander B Wong, Devendra Deshpande
  • Patent number: 9768773
    Abstract: A system, comprising a dual voltage supply configured to receive a logic state input voltage and configured to output an output voltage, wherein the dual voltage supply is configured to output a nominal voltage at a high state of the logic state input voltage and the dual voltage supply is configured to output a high voltage at a low state of the logic state input voltage, a pre-charge capacitor is configured to receive the output voltage of the dual voltage supply and an output buffer has an output buffer power input is coupled to the pre-charge capacitor and configured to receive the output voltage of the dual voltage supply, an output buffer signal input is configured to receive the logic state input voltage and an output buffer output is configured to output a digital output signal.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: September 19, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Robert Mark Englekirk
  • Patent number: 9692415
    Abstract: A semiconductor device includes a first power supply node and a second power supply node having a voltage value higher than the first power supply node. A first switch interrupts a power supplied from the first power supply node to a first circuit node. A second switch interrupts a power supplied from the second power supply node to a second circuit node. A driver drives the second switch by a third switch being driven. The third switch is connected between the second power supply node and the first circuit node. A controller outputs a control signal to drive the first and third switches.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: June 27, 2017
    Assignee: SOCIONEXT INC.
    Inventor: Atsushi Okamoto
  • Patent number: 9590620
    Abstract: An embodiment according to the present invention discloses a gate driving circuit and display panel using the same. The circuit includes a driving unit, a control unit, a first negative voltage input, a driving voltage input and a control signal input. Three inputting ends of the driving unit are connected to the different inputs when the status of the driving unit is changed according to the sequence of first cut-off st atus/first driving status/second driving status/second cutoff status. The benefit of the solution is to prevent circuit invalid due to the drain current generating when the oxide thin film transistor works in the depletion mode.
    Type: Grant
    Filed: February 16, 2015
    Date of Patent: March 7, 2017
    Assignee: EVERDISPLAY OPTRONICS (SHANGHAI) LIMITED
    Inventors: JiaHao Lu, Xin Mou
  • Patent number: 9465088
    Abstract: Non-contact positions sensors are desirable because they have lower failure rates than traditional potentiometers. However, using a Hall Effect sensor as a non-contact position sensor requires a particular input polarity. In an embodiment, a polarity insensitive Hall Effect sensor includes conversion sensors configured to produce outputs responsive to an input. The sensor also includes a semiconductor rectifier arranged to power a first conversion sensor and a second conversion sensor with a given polarity regardless of whether the input has a positive or negative polarity. The sensor also includes a semiconductor multiplexer circuit arranged to direct the first output to a common output port if the input has a positive polarity and direct the second output to the common output port if the input has a negative polarity. The polarity insensitive Hall Effect sensor provides an output representing a position without requiring a input polarity.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: October 11, 2016
    Assignee: Sensata Technologies, Inc.
    Inventor: Rene Putinier
  • Patent number: 9041116
    Abstract: A method for forming an electrical device that includes forming a high-k gate dielectric layer over a semiconductor substrate that is patterned to separate a first portion of the high-k gate dielectric layer that is present on a first conductivity device region from a second portion of the high-k gate dielectric layer that is present on a second conductivity device region. A connecting gate conductor is formed on the first portion and the second portion of the high-k gate dielectric layer. The connecting gate conductor extends from the first conductivity device region over the isolation region to the second conductivity device region. One of the first conductivity device region and the second conductivity device region may then be exposed to an oxygen containing atmosphere. Exposure with the oxygen containing atmosphere modifies a threshold voltage of the semiconductor device that is exposed.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: May 26, 2015
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Kangguo Cheng, Steven J. Holmes, Ali Khakifirooz, Pranita Kulkarni, Shom Ponoth, Raghavasimhan Sreenivasan, Stefan Schmitz
  • Patent number: 9024366
    Abstract: A semiconductor device having a dummy active region for metal ion gathering, which is capable of preventing device failure due to metal ion contamination, and a method of fabricating the same are provided. The semiconductor device includes active regions defined by an isolation layer in a semiconductor substrate and ion-implanted with an impurity, and a dummy active region ion-implanted with an impurity having a concentration higher than that of the impurity in the active region and configured to gather metal ions.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: May 5, 2015
    Assignee: SK Hynix Inc.
    Inventor: Jong Il Kim
  • Patent number: 9023696
    Abstract: Disclosed herein is a method of forming a semiconductor device. In one example, the method includes performing a first process operation to form a first etch stop layer above a first region of a semiconducting substrate where a first type of transistor device will be formed, and forming a first stress inducing layer at least above the first etch stop layer in the first region, wherein the first stress inducing layer is adapted to induce a stress in a channel region of the first type of transistor. The method further includes, after forming the first etch stop layer, performing a second process operation form a second etch stop layer above a second region of the substrate where a second type of transistor device will be formed, and forming a second stress inducing layer at least above the second etch stop layer in the second region, wherein the second stress inducing layer is adapted to induce a stress in a channel region of the second type of transistor.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: May 5, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Peter Baars, Marco Lepper, Thilo Scheiper
  • Patent number: 9018709
    Abstract: A semiconductor device includes: a first field-effect transistor of a first conductivity type formed on a first active region of a semiconductor substrate. The first field-effect transistor includes a first gate insulating film formed on the first active region, and a first gate electrode formed on the first gate insulating film. The first gate electrode includes a first metal electrode formed on the first gate insulating film, a first interface layer formed on the first metal electrode, and a first silicon electrode formed on the first interface layer.
    Type: Grant
    Filed: November 1, 2012
    Date of Patent: April 28, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventor: Shinji Takeoka
  • Patent number: 9018710
    Abstract: A semiconductor device includes a substrate including first and second regions. A first gate stack structure containing a first effective work function adjust species is formed over the first region and a second gate stack structure containing a second effective work function adjust species is formed over the second region. A channel region is formed under the first gate stack structure and contains a threshold voltage adjust species.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: April 28, 2015
    Assignee: SK Hynix Inc.
    Inventors: Seung-Mi Lee, Yun-Hyuck Ji
  • Patent number: 9012277
    Abstract: Generally, the present disclosure is directed to methods for forming dual embedded stressor regions in semiconductor devices such as transistor elements and the like, using in situ doping and substantially diffusionless annealing techniques. One illustrative method disclosed herein includes forming first and second cavities in PMOS and NMOS device regions, respectively, of a semiconductor substrate, and thereafter performing first and second epitaxial deposition processes to form in situ doped first and second embedded material regions in the first and second cavities, respectively. The method further includes, among other things, performing a single heat treating process to activate dopants in the in situ doped first and second embedded material regions.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: April 21, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stefan Flachowsky, Ralf Illgen
  • Patent number: 9013003
    Abstract: A semiconductor structure includes a first gate and a second gate, a first spacer and a second spacer, two first epitaxial structures and two second epitaxial structures. The first gate and the second gate are located on a substrate. The first spacer and the second spacer are respectively located on the substrate beside the first gate and the second gate. The first epitaxial structures and the second epitaxial structures are respectively located in the substrate beside the first spacer and the second spacer, wherein the first spacer and the second spacer have different thicknesses, and the spacing between the first epitaxial structures is different from the spacing between the second epitaxial structures. Moreover, the present invention also provides a semiconductor process forming said semiconductor structure.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: April 21, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Chia-Jui Liang, Po-Chao Tsao
  • Patent number: 9006860
    Abstract: A CMOS semiconductor die comprises a substrate; an insulation layer over a major surface of the substrate; a plurality of P-metal gate areas formed within the insulation layer collectively covering a first area of the major surface; a plurality of N-metal gate areas formed within the insulation layer collectively covering a second area of the major surface, wherein a first ratio of the first area to the second area is equal to or greater than 1; a plurality of dummy P-metal gate areas formed within the insulation layer collectively covering a third area of the major surface; and a plurality of dummy N-metal gate areas formed within the insulation layer collectively covering a fourth area of the major surface, wherein a second ratio of the third area to the fourth area is substantially equal to the first ratio.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: April 14, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry-Hak-Lay Chuang, Ming Zhu
  • Patent number: 8999863
    Abstract: A stress liner having first and second stress type is provided over a first type and a second type transistor to improve reliability and performance without incurring area penalties or layout deficiencies.
    Type: Grant
    Filed: June 5, 2008
    Date of Patent: April 7, 2015
    Assignee: GlobalFoundries Singapore Pte. Ltd.
    Inventors: Jae Gon Lee, Jingze Tian, Shyue Seng Tan, Luona Goh, Wei Lu, Elgin Quek
  • Patent number: 9000529
    Abstract: A circuit includes a complimentary metal-oxide semiconductor (CMOS) storage element implemented within a p-type substrate and an n-well implemented within the p-type substrate that is independent of the storage element. The n-well and the storage element are separated by a minimum distance in which the p-type substrate includes no n-well.
    Type: Grant
    Filed: November 1, 2012
    Date of Patent: April 7, 2015
    Assignee: Xilinx, Inc.
    Inventors: Praful Jain, James Karp, Michael J. Hart, Ramakrishna K. Tanikella
  • Patent number: 8993392
    Abstract: A vertically stacked, planar junction Zener diode is concurrently formed with epitaxially grown FET raised S/D terminals. The structure and process of the Zener diode are compatible with Gate-Last high-k FET structures and processes. Lateral separation of diode and transistor structures is provided by modified STI masking. No additional photolithography steps are required. In some embodiments, the non-junction face of the uppermost diode terminal is silicided with nickel to additionally perform as a copper diffusion barrier.
    Type: Grant
    Filed: June 21, 2013
    Date of Patent: March 31, 2015
    Assignee: Broadcom Corporation
    Inventors: Wei Xia, Xiangdong Chen
  • Patent number: 8987144
    Abstract: In sophisticated semiconductor devices, high-k metal gate electrode structures may be formed in an early manufacturing stage with superior integrity of sensitive gate materials by providing an additional liner material after the selective deposition of a strain-inducing semiconductor material in selected active regions. Moreover, the dielectric cap materials of the gate electrode structures may be removed on the basis of a process flow that significantly reduces the degree of material erosion in isolation regions and active regions by avoiding the patterning and removal of any sacrificial oxide spacers.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: March 24, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan Kronholz, Markus Lenski, Hans-Juergen Thees
  • Patent number: 8981489
    Abstract: Semiconductor devices including a resistor structure is provided. The semiconductor device may include a gate structure on an active region, a resistor structure on a field region and a first interlayer insulating layer on the gate structure and the resistor structure. The semiconductor devices may also include a resistor trench plug vertically penetrating through the first interlayer insulating layer and contacting the resistor structure and a second interlayer insulating layer on the first interlayer insulating layer and the resistor trench plug. Further, the semiconductor devices may include a resistor contact plug vertically penetrating through the first and second interlayer insulating layers and contacting the resistor structure.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: March 17, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Junjie Xiong, Yoon-Hae Kim, Hong-Seong Kang, Yoon-Seok Lee, You-Shin Choi
  • Patent number: 8975707
    Abstract: A region for substrate potential is formed of an n-type well at a position in the direction of a channel length relative to the gate electrode and the position is between drain regions in the direction of a channel width. An n-type of a contact region with a higher concentration of n-type impurity than that of the region is provided in the region. The contact region is arranged away from the drain regions with a distance to obtain a desired breakdown voltage of PN-junction between the region and the drain region.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: March 10, 2015
    Assignee: Ricoh Company, Ltd.
    Inventor: Masaya Ohtsuka
  • Patent number: 8975712
    Abstract: One method disclosed herein includes forming first and second transistor devices in and above adjacent active regions that are separated by an isolation region, wherein the transistors comprise a source/drain region and a shared gate structure, forming a continuous conductive line that spans across the isolation region and contacts the source/drain regions of the transistors and etching the continuous conductive line to form separated first and second unitary conductive source/drain contact structures that contact the source/drain regions of the first and second transistors, respectively. A device disclosed herein includes a gate structure, source/drain regions, first and second unitary conductive source/drain contact structures, each of which contacts one of the source/drain regions, and first and second conductive vias that contact the first and second unitary conductive source/drain contact structures, respectively.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: March 10, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Mahbub Rashed, Juhan Kim, Yunfei Deng, Suresh Venkatesan
  • Patent number: 8969916
    Abstract: A semiconductor device includes a gate electrode structure of a transistor, the gate electrode structure being positioned above a semiconductor region and having a gate insulation layer that includes a high-k dielectric material, a metal-containing cap material positioned above the gate insulation layer, and a gate electrode material positioned above the metal-containing cap material. A bottom portion of the gate electrode structure has a first length and an upper portion of the gate electrode structure has a second length that is different than the first length, wherein the first length is approximately 50 nm or less. A strain-inducing semiconductor alloy is embedded in the semiconductor region laterally adjacent to the bottom portion of the gate electrode structure, and drain and source regions are at least partially positioned in the strain-inducing semiconductor alloy.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: March 3, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan Kronholz, Markus Lenski, Vassilios Papageorgiou
  • Patent number: 8969970
    Abstract: A semiconductor device includes a first MIS transistor and a second MIS transistor. The first MIS transistor includes a first gate insulating film which is formed on a first active region of a semiconductor substrate and has a first high dielectric constant film, and a first gate electrode formed on the first gate insulating film. The second MIS transistor includes a second gate insulating film which is formed on a second active region of the semiconductor substrate and has a second high dielectric constant film, and a second gate electrode formed on the second gate insulating film. The second high dielectric constant film contains first adjusting metal. The first high dielectric constant film has a higher nitrogen concentration than the second high dielectric constant film, and does not contain the first adjusting metal.
    Type: Grant
    Filed: August 6, 2014
    Date of Patent: March 3, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Yoshihiro Sato, Takayuki Yamada
  • Patent number: 8969969
    Abstract: Transistors exhibiting different electrical characteristics such as different switching threshold voltage or different leakage characteristics are formed on the same chip or wafer by selectively removing a film or layer which can serve as an out-diffusion sink for an impurity region such as a halo implant and out-diffusing an impurity such as boron into the out-diffusion sink, leaving the impurity region substantially intact where the out-diffusion sink has been removed. In forming CMOS integrated circuits, such a process allows substantially optimal design for both low-leakage and low threshold transistors and allows a mask and additional associated processes to be eliminated, particularly where a tensile film is employed to increase electron mobility since the tensile film can be removed from selected NMOS transistors concurrently with removal of the tensile film from PMOS transistors.
    Type: Grant
    Filed: March 19, 2010
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Victor W. C. Chan, Narasimhulu Kanike, Huiling Shang, Varadarajan Vidya, Jun Yuan, Roger Allen Booth, Jr.
  • Patent number: 8963250
    Abstract: A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which second region is different from the first region. An impurity concentration of a gate electrode of the n channel FET has an impurity concentration greater than an impurity concentration of the gate electrode of the p channel FET to thereby create a tensile stress in the direction of flow of a drain current in the channel forming region of the n channel FET. The tensile stress in the flow direction of the drain current in the channel forming region of the n channel FET is greater than a tensile stress in the direction of flow of a drain current in the channel forming region of the p channel FET.
    Type: Grant
    Filed: October 15, 2008
    Date of Patent: February 24, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Akihiro Shimizu, Nagatoshi Ooki, Yusuke Nonaka, Katsuhiko Ichinose
  • Patent number: 8946721
    Abstract: A method is provided that includes forming a high-k dielectric etch stop layer over at least a first conductivity type semiconductor device on a first portion of a substrate and at least a second conductivity type semiconductor device on a second portion of the semiconductor device. A first stress-inducing layer is deposited over the first conductivity type semiconductor device and the second conductivity type semiconductor device. The portion of the first stress-inducing layer that is formed over the second conductivity type semiconductor device is then removed with an etch that is selective to the high-k dielectric etch stop layer to provide an exposed surface of second portion of the substrates that includes at least the second conductivity type semiconductor device. A second stress-inducing layer is then formed over the second conductivity type semiconductor device.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventor: William K. Henson
  • Patent number: 8946084
    Abstract: A device includes a p-type metal-oxide-semiconductor (PMOS) device and an n-type metal-oxide-semiconductor (NMOS) device at a front surface of a semiconductor substrate. A first dielectric layer is disposed on a backside of the semiconductor substrate. The first dielectric layer applies a first stress of a first stress type to the semiconductor substrate, wherein the first dielectric layer is overlying the semiconductor substrate and overlapping a first one of the PMOS device and the NMOS device, and is not overlapping a second one of the PMOS device and the NMOS device. A second dielectric layer is disposed on the backside of the semiconductor substrate. The second dielectric layer applies a second stress to the semiconductor substrate, wherein the second stress is of a second stress type opposite to the first stress type. The second dielectric layer overlaps a second one of the PMOS device and the NMOS device.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: February 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, I-Ching Lin
  • Patent number: 8940626
    Abstract: A method for fabricating an integrated circuit includes forming a first layer of a workfunction material in a first trench of a plurality of trench structures formed over a silicon substrate, the first trench having a first length and forming a second layer of a workfunction material in a second trench, the second trench having a second length that is longer than the first length. The method further includes depositing a low-resistance fill material onto the integrated circuit to fill any unfilled trenches with the low-resistance fill material and etching the low resistance fill material, the first layer, and the second layer to re-expose a portion of each trench of the plurality of trenches, while leaving a portion of each of the first layer, the second layer, and the low-resistance fill material in place. Still further, the method includes depositing a gate fill material into each re-exposed trench portion.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: January 27, 2015
    Assignees: GLOBALFOUNDRIES Inc., International Business Machines Corporation
    Inventors: Ruilong Xie, Pranatharthi Haran Balasubramanian
  • Patent number: 8941153
    Abstract: An integrated circuit structure includes a semiconductor substrate including a first portion in a first device region, and a second portion in a second device region. A first semiconductor fin is over the semiconductor substrate and has a first fin height. A second semiconductor fin is over the semiconductor substrate and has a second fin height. The first fin height is greater than the second fin height.
    Type: Grant
    Filed: August 30, 2010
    Date of Patent: January 27, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Lin Lee, Chih Chieh Yeh, Chang-Yun Chang, Feng Yuan
  • Patent number: 8928111
    Abstract: Transistors are formed using pitch multiplication. Each transistor includes a source region and a drain region connected by strips of active area material separated by shallow trench isolation (STI) structures, which are formed by dielectric material filling trenches formed by pitch multiplication. During pitch multiplication, rows of spaced-apart mandrels are formed and spacer material is deposited over the mandrels. The spacer material is etched to define spacers on sidewalls of the mandrels. The mandrels are removed, leaving free-standing spacers. The spacers constitute a mask, through which an underlying substrate is etched to form the trenches and strips of active area material. The trenches are filled to form the STI structures. The substrate is doped, forming source, drain and channel regions. A gate is formed over the channel region. In some embodiments, the STI structures and the strips of material facilitate the formation of transistors having a high breakdown voltage.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: January 6, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Mike Smith
  • Patent number: 8927361
    Abstract: Transistors exhibiting different electrical characteristics such as different switching threshold voltage or different leakage characteristics are formed on the same chip or wafer by selectively removing a film or layer which can serve as an out-diffusion sink for an impurity region such as a halo implant and out-diffusing an impurity such as boron into the out-diffusion sink, leaving the impurity region substantially intact where the out-diffusion sink has been removed. In forming CMOS integrated circuits, such a process allows substantially optimal design for both low-leakage and low threshold transistors and allows a mask and additional associated processes to be eliminated, particularly where a tensile film is employed to increase electron mobility since the tensile film can be removed from selected NMOS transistors concurrently with removal of the tensile film from PMOS transistors.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Roger Allen Booth, Jr., Victor W. C. Chan, Narasimhulu Kanike, Huiling Shang, Varadarajan Vidya, Jun Yuan
  • Patent number: 8916936
    Abstract: A semiconductor device including: a first gate pattern disposed in a peripheral region of a substrate; a second gate pattern disposed in a cell region of the substrate; a first insulator formed on sidewalls of the first gate pattern; and a second insulator formed on sidewalls of the second gate pattern, wherein a dielectric constant of the first insulator is different from a dielectric constant of the second insulator, and wherein a height of the second insulator is greater than a height of the second gate pattern.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: December 23, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Chan Lee, Seung-Jae Lee, Sang-Bom Kang, Dae-Young Kwak, Myeong-Cheol Kim, Yong-Ho Jeon
  • Patent number: 8916933
    Abstract: A semiconductor device having a tensile and/or compressive strain applied thereto and methods of manufacturing the semiconductor devices and design structure to enhance channel strain. The gate structures for an NFET and a PFET have identically formed sidewalls, and stress materials are provided in recesses in source and drain regions of the NFET and the PFET.
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: December 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Carl J. Radens
  • Patent number: 8912057
    Abstract: A semiconductor device with an n-type transistor and a p-type transistor having an active region is provided. The active region further includes two adjacent gate structures. A portion of a dielectric layer between the two adjacent gate structures is selectively removed to form a contact opening having a bottom and sidewalls over the active region. A bilayer liner is selectively provided within the contact opening in the n-type transistor and a monolayer liner is provided within the contact opening in the p-type transistor. The contact opening in the n-type transistor and p-type transistor is filled with contact material. The monolayer liner is treated to form a silicide lacking nickel in the p-type transistor.
    Type: Grant
    Filed: June 5, 2013
    Date of Patent: December 16, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Derya Deniz
  • Patent number: 8907427
    Abstract: A semiconductor device may include a substrate, source and drain regions in the substrate, a recessed epitaxial channel layer in the substrate between the source and drain regions, and a high-K gate dielectric layer overlying the recessed epitaxial channel layer. The semiconductor device may further include a gate electrode overlying the high-K gate dielectric layer, a dielectric cap layer in contact with top and sidewall portions of the gate electrode, the dielectric cap layer having a lower dielectric constant than the high-K gate dielectric layer, and source and drain contacts coupled to the source and drain regions.
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: December 9, 2014
    Assignee: STMicroelectronics, Inc.
    Inventor: John H Zhang
  • Patent number: 8901665
    Abstract: The present disclosure provides a method of semiconductor fabrication including forming an inter-layer dielectric (ILD) layer on a semiconductor substrate. The ILD layer has an opening defined by sidewalls of the ILD layer. A spacer element is formed on the sidewalls of the ILD layer. A gate structure is formed in the opening adjacent the spacer element. In an embodiment, the sidewall spacer also for a decrease in the dimensions (e.g., length) of the gate structure formed in the opening.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: December 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Andrew Joseph Kelly, Pei-Shan Chien, Yung-Ta Li, Chan Syun Yang
  • Patent number: 8901666
    Abstract: A semiconducting graphene structure may include a graphene material and a graphene-lattice matching material over at least a portion of the graphene material, wherein the graphene-lattice matching material has a lattice constant within about ±5% of a multiple of the lattice constant or bond length of the graphene material. The semiconducting graphene structure may have an energy band gap of at least about 0.5 eV. A method of modifying an energy band gap of a graphene material may include forming a graphene-lattice matching material over at least a portion of a graphene material, the graphene-lattice matching material having a lattice constant within about ±5% of a multiple of the lattice constant or bond length of the graphene material.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: December 2, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Roy E. Meade, Sumeet C. Pandey
  • Patent number: 8901668
    Abstract: An n-channel MISFETQn is formed in an nMIS first formation region of a semiconductor substrate and a p-channel MISFETQp is formed in an adjacent pMIS second formation region of the semiconductor substrate. A silicon nitride film having a tensile stress is formed to cover the n-channel MISFETQn and the p-channel MISFETQp. In one embodiment, the silicon nitride film in the nMIS formation region and the pMIS formation region is irradiated with ultraviolet rays. Thereafter, a mask layer is formed to cover the silicon nitride film in the nMIS formation region and to expose the silicon nitride film in the pMIS formation region. The silicon nitride film in the pMIS formation region is then subjected to plasma processing, which relieves the tensile stress of the silicon nitride film in the pMIS formation region.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: December 2, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Tatsunori Murata
  • Patent number: 8901664
    Abstract: A device and method for fabrication of fin devices for an integrated circuit includes forming fin structures in a semiconductor material of a semiconductor device wherein the semiconductor material is exposed on sidewalls of the fin structures. A donor material is epitaxially deposited on the exposed sidewalls of the fin structures. A condensation process is applied to move the donor material through the sidewalls into the semiconductor material such that accommodation of the donor material causes a strain in the semiconductor material of the fin structures. The donor material is removed, and a field effect transistor is formed from the fin structure.
    Type: Grant
    Filed: June 2, 2011
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Bruce B. Doris, Johnathan E. Faltermeier, Ali Khakifirooz
  • Patent number: 8890257
    Abstract: Disclosed is a damascene method for forming a semiconductor structure and the resulting semiconductor structure having multiple fin-shaped channel regions with different widths. In the method, fin-shaped channel regions are etched using differently configured isolating caps as masks to define the different widths. For example, a wide width isolating cap can comprise a dielectric body positioned laterally between dielectric spacers and can be used as a mask to define a relatively wide width channel region; a medium width isolating cap can comprise a dielectric body alone and can be used as a mask to define a medium width channel region and/or a narrow width isolating cap can comprise a dielectric spacer alone and can be used as a mask to define a relatively narrow width channel region. These multiple fin-shaped channel regions with different widths can be incorporated into either multiple multi-gate field effect transistors (MUGFETs) or a single MUGFET.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: November 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak, Jed H. Rankin
  • Patent number: 8884372
    Abstract: At least one analog signal compatible complementary metal oxide semiconductor (CMOS) switch circuit is incorporated with digital logic circuits in an integrated circuit. The integrated circuit may further comprise a digital processor and memory, e.g., microcontroller, microprocessor, digital signal processor (DSP), programmable logic array (PLA), application specific integrated circuit (ASIC), etc., for controlling operation of the at least one analog signal compatible CMOS switch for switching analog signals, e.g., audio, video, serial communications, etc. The at least one analog signal compatible CMOS switch may have first and second states, e.g., single throw “on” or “off”, or double throw common to a or b, controlled by a single digital control signal of either a logic “0” or a logic “1”.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: November 11, 2014
    Assignee: Microchip Technology Incorporated
    Inventor: James K. Russell
  • Patent number: 8878301
    Abstract: A semiconductor device includes core transistors for forming a logic circuit, and I/O transistors for forming an input/output circuit. A distance from the main surface to a lowermost part of an n-type impurity region NR of the I/O n-type transistor is longer than that from the main surface to a lowermost part of an n-type impurity region NR of the core n-type transistor. A distance from the main surface to a lowermost part of a p-type impurity region PR of the I/O p-type transistor is longer than that from the main surface to a lowermost part of a p-type impurity region of the core p-type transistor. A distance from the main surface to the lowermost part of the n-type impurity region of the I/O n-type transistor is longer than that from the main surface to the lowermost part of the p-type impurity region of the I/O p-type transistor.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: November 4, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Yuichi Hirano