MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
A semiconductor manufacturing method includes forming a word line crossing with an active region on a semiconductor substrate; forming a diffusion layer region; forming a first insulating film as high as a bit line to be formed; etching the first insulating film, while using, as a mask, a pattern having a linear aperture extending to the active region on the first insulating film so as to form a groove pattern for exposing the surface of the semiconductor substrate; embedding a conductive film in the groove pattern; forming a mask pattern passing over a portion, in which a bit contact is formed, on the first insulating film; and removing the first insulating film and the conductive layer until the upper layer insulating film of the word line is exposed, while using the mask pattern as a mask so as to isolate a bit contact from another contact.
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1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, in particular, to a method of forming a bit contact in a memory cell, etc., of a DRAM (Dynamic Random Access Memory).
2. Description of the Related Art
In a semiconductor integrated circuit device, wiring is being micro-miniaturized in order to improve characteristics and yields. In a process of manufacturing a micro-miniaturized semiconductor integrated circuit device, there is a problem since if design margin for a contact hole is determined in consideration of deviation of alignment with lower layer wiring, the deign dimension (=hole diameter+design margin) of the contact hole would be oversized. Alignment deviation is caused by deficiency of alignment performance of a reduced projection stepper used in photolithography. Moreover, alignment deviation makes scaling down, which is one of various dimension requirements (scaling factor) for a semiconductor process, difficult. As such, it is said that alignment deviation is a factor, which affects limits of the lithography technology more than the resolution limit.
Recently, a self-alignment contact (SAC) process, whereby design margin for alignment is unnecessary on a photo mask, has been mostly used.
In general, a DRAM memory cell has the structure, in which two neighboring transistors share a bit contact diffusion layer, and both sides thereof have a capacitor contact diffusion layer so as to form one cell. FIGS. 1 to 9 show processes until formation of a bit line of a cell transistor having the so-called COB (Capacitor Over Bitline) structure, in which a capacitor structure is formed on a conventional bit line. In each of the drawings, (a) is a top view, (b) is an XX cross-sectional view, (c) is an YY cross-sectional view, and (d) is a perspective projected view. The drawings were prepared by the inventor to explain the background art of the present invention and do not describe conventional technology itself.
Firstly, as illustrated in
Subsequently, as illustrated in
Subsequently, as illustrated in
As illustrated in
As illustrated in
In the subsequent process of
As illustrated in
In the process illustrated in
Finally, as illustrated in
In the conventional cell contact (11) and bit contact (15), a hole is formed by forming a pattern on a resist through lithography and processing it through dry etching. As such, the dimension of a completed resist pattern and the precision of dry etching significantly affect the shape of a completed contact. This influence will be described with reference to
After optimum dry etching, the interlayer insulating film aperture (13a) is formed in a predetermined position as illustrated in
Although the pattern irregulars illustrated in
Japanese Patent Laid-Open No. 2001-223155 discloses a photolithography process, in which a contact aperture is set small. This document discloses a process of exposing mutually crossing line patterns on a negative resist twice and developing a non-exposed portion between the line patterns to be used as a contact aperture mask. In this case, by adjusting the spacing of the line patterns, a desired size of an aperture mask is formed. In this process, shortage of isolation margin upon exposing a resist pattern is resolved. However, like a hole pattern, partial deviation of dry etching cannot be resolved.
Japanese Patent Laid-Open No. 2000-36573 discloses a process of reducing the spacing of contact holes and forming relatively large contact holes in the case where a bit cell contact and a capacitor cell contact are close to each other due to disposition of diffusion layers. According to this process, shortage of isolation margin upon exposing a resist pattern is resolved by forming a thin hard mask layer consisting of polysilicon on an interlayer insulating film forming a contact hole, and forming every other hard mask patterns for apertures of neighboring contact holes through two times of hard mask etching. However, since the hard mask etching is performed twice, the process is complicated. Further, the problem in local deviation of dry etching still exists.
There is an over etching method to resolve local deviation of dry etching. However, since a word line to be a gate electrode is disposed below a bit contact, and an insulating film insulating between the gate electrode and the contact is etched in the portion, in which etching is performed fast due to the over etching, short circuit or other problems may occur. In particular, if a micro-miniaturized cell contact is formed by the SAC method, a contact hole aperture formed thereon is larger than the diameter of the top surface of the cell contact, so that etching of the insulating film covering a word line cannot be avoided. Thus, the over etching has a limit in resolving local deviation.
Meanwhile, Japanese Patent Laid-Open No. 2005-94044 discloses a technique of forming a cell contact by using a line pattern (slit pattern) extending in a longitudinal direction of an active region. This technique pursues additional reduction of a cell contact by additionally forming a side wall after forming a slit pattern. However, since a bit contact formed on the cell contact is manufactured by a conventional method, the problem in forming a bit contact described above is not considered.
As described above, even though conventional technology might have resolved shortage of isolation margin upon exposing a resist pattern, it has complicated processes. In addition, as long as a hole pattern is formed, local deviation of dry etching cannot be resolved. In particular, no technical solution with respect to forming a bit contact has been developed.
SUMMARYIn order to resolve shortage of isolation margin upon exposing a resist pattern and local deviation of dry etching, the inventor of the present invention reviewed a method of forming a cell contact and a bit contact by using a line pattern. In the method using a line pattern (groove pattern), etchants can be moved along with a groove, and thereby resulting in the effect of inhibiting local deviation of dry etching. Further, in case of a line pattern, compared to a hole pattern, isolation margin upon exposing a resist pattern can be easily acquired. However, using a line pattern would be meaningless if it causes manufacturing processes to be complicated. The present invention provides a method of forming a cell contact and a bit contact by effectively using a line pattern without causing complicated processes.
One embodiment of the present invention provides a method of manufacturing a semiconductor device comprising:
forming, on a semiconductor substrate comprising active regions which are element-isolated each other, a word line combining with a gate electrode so as to cross with the active regions;
forming diffusion regions on each active region between the word lines;
forming, on the whole surface, a first insulating film as high as a bit line to be formed;
forming a linear mask pattern having a linear aperture on the extending direction of the active regions on the first insulating film;
etching the first insulating film, while using the linear mask pattern as a mask, so as to form a groove pattern for exposing the surface of the semiconductor substrate comprising the active regions;
embedding a conductive film in the groove pattern;
forming an etching mask pattern passing over a portion, in which a bit contact is formed, on the first insulating film, in which the conductive layer is embedded; and
removing the first insulating film and the conductive layer until an upper layer insulating film of the word line is exposed, while using the linear mask pattern as a mask, so as to isolate a bit contact from another contact.
According to the present invention, by using a linear pattern, shortage of isolation margin upon exposing a resist pattern can be resolved. Simultaneously, local deviation of dry etching can be resolved. In addition, by using a linear pattern, a bit contact and a cell contact are integratedly formed. Further, a cell contact, to which a capacitor contact is connected, can be manufactured by reducing the height of the embedded conductive film to the height of the bit contact. As a result, complexity in process and an increase in the number of processes can be inhibited.
The features and advantages of the present invention that have been described will be more apparent from the following descriptions of certain preferred embodiments taken in conjunction of with the accompanying drawings.
The invention will be now described herein with reference to illustrative embodiments. Those skilled in the art will recognize that many alternative embodiments can be accomplished using the teachings of the present invention and that the invention is not limited to the embodiments illustrated for explanatory purpose.
Firstly, as illustrated in
Subsequently, as illustrated in
Subsequently, as illustrated in
The interlayer insulating film (8) exposed from the resist aperture is etched through dry etching until the diffusion region (3) is exposed, so that an interlayer insulating film aperture (8a) is formed. Thereafter, the resist is removed from the top surface of the interlayer insulating film (8), so that an aperture of a line pattern (groove pattern) is formed.
As illustrated in
In the subsequent process of
As illustrated in
Dry Etching Condition (Simultaneous Etching)
(1) Method: reactive ion etching (RIE)
(2) Source power: 400 W
(3) Bias power: 50 W
(4) Pressure: about 0.53 Pa (4 mTorr)
(5) Wafer temperature: 15° C.
(6) Process gases and flow rate: CF4/Cl2/O2/N2=55/20/10/100 sccm
(7) Selectivity Ratio: SiN/W/SiO=1.3/1.0/1.0
The conductive film (9) and the interlayer insulating film (8) do not need to be simultaneously etched and may be individually etched. In this case, the dry etching condition is as described below. Under the etching condition for the conductive film (9), etching of the interlayer insulating film (8) is impossible. Likewise, under the etching condition for the interlayer insulating film (8), etching of the conductive film (9) is impossible. Thus, by adjusting the finish point of etchings, processing can be performed without causing an etching step difference. However, if the interlayer insulating film (8) is first etched and removed, the remaining conductive film (9) may fall down and be damaged. Thus, first performing etching of the conductive film (9) is preferable.
Dry Etching Condition (Etching of Conductive Film (9))
(1) Method: RIE
(2) Source power: 1000 W
(3) Pressure: about 0.67 Pa (5 mTorr)
(4) Wafer temperature: 20° C.
(5) Process gas and flow rate: SF6/Ar=150/10 sccm
Dry Etching Condition (Etching of Interlayer Insulating Film (8))
(1) Method: RIE
(2) Source power: 2000 W
(3) Pressure: about 10.7 Pa (80 mTorr)
(4) Wafer temperature: 60° C.
(5) Process gas and flow rate: Perfluorocyclobutane (C4F8)/Ar/O2=15/750/15 sccm
During dry etching, the resist (31) and the nitrogen-containing silicon oxide and the silicon oxide in the laminated film (10) are removed. The amorphous carbon remaining after etching can be removed by ashing through oxygen plasma. In the process illustrated in
As illustrated in
The conductive film (14) is etched through dry etching until the interlayer insulating film (13) is exposed, while using the linear resist pattern (32) as an etching mask, so that a bit line (16) is completed. Thereafter, the resist (32) is removed, so that the structure illustrated in
Subsequently, the bit line (16) is embedded by an interlayer insulating film, and planarization is preformed. Thereafter, a process of forming a capacitor starts. The structure of a capacitor is not limited, and includes a known capacitor structure such as a stack type, a crown type, and a cylindrical type.
As described above, the contact of the present invention is formed by forming a linear pattern and then removing a conductive layer through CMP or dry etching to reach to a portion defined as a base film. Thus, a hole pattern of a resist is unnecessary so that contacting of neighboring patterns does not occur. Further, since local deviation of etching resulting from a hole pattern can be reduced, the technical problem of conventional technology can be resolved.
The structure, in which two neighboring transistors share a bit contact diffusion layer, and both sides thereof have a capacitor contact layer to form one cell, has been described as an example. However, the present invention is also applicable to the case where one transistor forms one cell.
As to the gate structure of a transistor, a planar structure of a polymetal structure, in which tungsten is laminated on polysilicon, has been described. However, a polycide structure, in which silicide is formed, or a recess gate structure, in which a gate is embedded in a substrate, is applicable. The other materials that have been described are not limited to the exemplified materials.
Moreover, as disclosed in Japanese Patent Laid-open No. 2005-94044, a side wall may be formed after a line pattern is formed in order to achieve micro-miniaturization of a line pattern in a side direction.
The present invention has been described with reference to embodiments. However, the present invention is not limited to the embodiments and may be modified within the scope of the essence of the present invention.
Claims
1. A method of manufacturing a semiconductor device comprising:
- forming, on a semiconductor substrate comprising active regions which are element-isolated each other, a word line combining with a gate electrode so as to cross with the active regions;
- forming diffusion regions on each active region between the word lines;
- forming, on the whole surface, a first insulating film as high as a bit line to be formed;
- forming a linear mask pattern having a linear aperture on the extending direction of the active regions on the first insulating film;
- etching the first insulating film, while using the linear mask pattern as a mask, so as to form a groove pattern for exposing the surface of the semiconductor substrate comprising the active regions;
- embedding a conductive film in the groove pattern;
- forming an etching mask pattern passing over a portion, in which a bit contact is formed, on the first insulating film, in which the conductive layer is embedded; and
- removing the first insulating film and the conductive layer until an upper layer insulating film of the word line is exposed, while using the linear mask pattern as a mask, so as to isolate a bit contact from another contact.
2. The method of manufacturing a semiconductor device according to claim 1, further comprising a process of forming side walls on the word line.
3. The method of manufacturing a semiconductor device according to claim 1, wherein the first insulating film and the conductive film are simultaneously removed under the condition that no etching selectivity ratio for both of them exists.
4. The method of manufacturing a semiconductor device according to claim 1, wherein after the conductive film is removed, the first insulating film is removed.
5. The method of manufacturing a semiconductor device according to claim 1, further comprising a process of forming a second insulating film after isolating a bit contact and another contact, performing planarization to expose the surface of the bit contact, and then forming a bit line connected to the bit contact.
Type: Application
Filed: Jun 28, 2010
Publication Date: Dec 30, 2010
Applicant: ELPIDA MEMORY, INC. (Tokyo)
Inventor: Hiromitu OSHIMA (Tokyo)
Application Number: 12/824,381
International Classification: H01L 21/768 (20060101); H01L 21/8242 (20060101);