PILLAR BUMP WITH BARRIER LAYER
A copper pillar bump has a surface covered with by a barrier layer formed of a copper-containing material layer including a group III element, a group IV element, a group V element or combinations thereof. The barrier layer depresses the copper diffusion and reaction with solder to reduce the thickness of intermetallic compound between the pillar pump and solder.
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The present application claims priority of U.S. Provisional Patent Application Ser. No. 61/258,393, filed on Nov. 5, 2009, which is incorporated herein by reference in its entirety.
TECHNICAL FIELDThis disclosure relates to the fabrication of integrated circuit devices, and more particularly, to the fabrication of bump structures in integrated circuit devices.
BACKGROUNDModern integrated circuits are made up of literally millions of active devices such as transistors and capacitors. These devices are initially isolated from each other, but are later interconnected together to form functional circuits. Typical interconnect structures include lateral interconnections, such as metal lines (wirings), and vertical interconnections, such as vias and contacts. Interconnections are increasingly determining the limits of performance and the density of modern integrated circuits. On top of the interconnect structures, bond pads are formed and exposed on the surface of the respective chip. Electrical connections are made through bond pads to connect the chip to a package substrate or another die. Bond pads can be used for wire bonding or flip-chip bonding.
Flip-chip packaging utilizes bumps to establish electrical contact between a chip's I/O pads and the substrate or lead frame of the package. Structurally, a bump actually contains the bump itself and a so-called under bump metallurgy (UBM) located between the bump and an I/O pad. An UBM generally contains an adhesion layer, a barrier layer and a wetting layer, arranged in this order on the I/O pad. The bumps themselves, based on the material used, are classified as solder bumps, gold bumps, copper pillar bumps and bumps with mixed metals. Recently, copper pillar bump technology is proposed. Instead of using solder bump, the electronic component is connected to a substrate by means of copper pillar bump, which achieves finer pitch with minimum probability of bump bridging, reduces the capacitance load for the circuits and allows the electronic component to perform at higher frequencies.
The Cu pillar bump flip-chip assembly has the following advantages: (1) better thermal/electric performance, (2) higher current carrying capacity, (3) better resistance to electromigration, thus longer bump life, (4) minimizing molding voids—more consistence gaps between Cu pillar bumps. Also, a lower cost substrate is possible by using Cu-pillar controlled solder spreading, eliminating lead-free teardrop design. However, there are concerns regarding the Intermetallic Compound (IMC) generated between the Cu pillar bump and the solder during annealing. When used with Sn solder material, sufficient Cu diffusion from Cu pillar bump into the solder forms thick IMC such as Cu6Sn5 and Cu3Sn through the reaction between the diffused Cu and Sn in the solder. Thick IMC layers reduce mechanical strength of the Cu pillar bump because the IMC layers are brittle. The IMC becomes scallops and spalls off the interface. With thicker Sn solder, longer annealing process and abundant Cu source make Cu3Sn thicker, and also the size of Cu6Sn5 becomes large. Total transfer of the ductile solder to harder IMC lowers the shear strength of the structure. The IMC formation will cause bump crack or unwanted stress, the thicker IMC also results in poor adhesion.
The objects, features and advantages of this disclosure will become apparent by referring to the following detailed description of exemplary embodiments with reference to the accompanying drawings, wherein:
In the following description, numerous specific details are set forth to provide a thorough understanding of the disclosure. However, one having an ordinary skill in the art will recognize that the disclosure can be practiced without these specific details. In some instances, well-known structures and processes have not been described in detail to avoid unnecessarily obscuring the disclosure.
Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be appreciated that the following figures are not drawn to scale; rather, these figures are merely intended for illustration.
Herein, cross-sectional diagrams of
In
The substrate 10 further includes inter-layer dielectric layers and a metallization structure overlying the integrated circuits. The inter-layer dielectric layers in the metallization structure include low-k dielectric materials, un-doped silicate glass (USG), silicon nitride, silicon oxynitride, or other commonly used materials. The dielectric constants (k value) of the low-k dielectric materials may be less than about 3.9, or less than about 2.8. Metal lines in the metallization structure may be formed of copper or copper alloys. One skilled in the art will realize the formation details of the metallization layers. A contact region 12 is a top metallization layer formed in a top-level inter-layer dielectric layer, which is a portion of conductive routs and has an exposed surface treated by a planarization process, such as chemical mechanical polishing (CMP), if necessary. Suitable materials for the conductive region 12 may include, but are not limited to, for example copper (Cu), aluminum (Al), AlCu, copper alloy, or other mobile conductive materials. In one embodiment, the contact region 12 is a metal pad region 12, which may be used in the bonding process to connect the integrated circuits in the respective chip to external features.
A post passivation interconnect (PPI) process is then performed on the passivation layer 14. Referring to
Also, a post passivation interconnect (PPI) line 18 is formed on the layers 16 to fill the opening 15. Using a mask and a photolithography process, a conductive material fills the opening 15 of the passivation layer 14 and the opening of the mask followed by removing the mask and the exposed layers 16. The conductive material formed on the layers 16 and filling the opening 15 serves as the PPI line 18. The PPI line 18 may include, but is not limited to, for example copper, aluminum, copper alloy, or other mobile conductive materials. The PPI line 18 may further include a nickel-containing layer (not shown) on the top a copper-containing layer. The PPI formation methods include plating, electroless plating, sputtering, chemical vapor deposition methods, and the like. The PPI line 18 connects the contact region 12 to bump features. The PPI line 18 may also function as power lines, re-distribution lines (RDL), inductors, capacitors or any passive components. The PPI line 18 may have a thickness less than about 30 μm, for example between about 2 μm and about 25 μm. Then the exposed portions of the layers 16 including the adhesion layer and the seed layer are removed. The removal step may include a wet etching process or a dry etching process. In one embodiment, the removal step includes an isotropic wet etching using an ammonia-based acid, which may be a flash etching with a short duration.
Next, a dielectric layer 20, also referred to as an isolation layer or a passivation layer, is formed on the exposed passivation layer 14 and the PPI line 18. The dielectric layer 20 may be formed of dielectric materials such as silicon nitride, silicon carbide, silicon oxynitride or other applicable materials. The formation methods include plasma enhance chemical vapor deposition (PECVD) or other commonly used CVD methods. A polymer layer 22 is formed on the dielectric layer 16 through the steps of coating, curing, descum and the like. Lithography technology and etching processes such as a dry etch and/or a wet etch process are then performed to pattern the polymer layer 22, thus an opening 23 is formed to pass through the polymer layer 22 and expose a portion of the PPI line 18 for allowing subsequent bump process. The polymer layer 22, as the name suggests, is formed of a polymer, such as an epoxy, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), and the like, although other relatively soft, often organic, dielectric materials can also be used. In one embodiment, the polymer layer 22 is a polyimide layer. In another embodiment, the polymer layer 22 is a polybenzoxazole (PBO) layer. The polymer layer 22 is soft, and hence has the function of reducing inherent stresses on respective substrate. In addition, the polymer layer 22 is easily formed to a thickness of tens of microns.
Referring to
Next, a mask layer 26 is provided on the UBM layer 24 and patterned with an opening 27 exposing a portion of the UBM layer 24 for Cu pillar bump formation. In one embodiment, the opening 27 is over the opening 23. In another embodiment, the diameter of the opening 27 is greater or equal to the diameter of the opening 23. The mask layer 26 may be a dry film or a photoresist film. The opening 27 is then partially or fully filled with a conductive material with solder wettability. In an embodiment, a copper (Cu) layer 28 is formed in the opening 27 to contact the underlying UBM layer 24. As used throughout this disclosure, the term “copper (Cu) layer” is intended to include substantially a layer including pure elemental copper, copper containing unavoidable impurities, and copper alloys containing minor amounts of elements such as tantalum, indium, tin, zinc, manganese, chromium, titanium, germanium, strontium, platinum, magnesium, aluminum or zirconium. The formation methods may include sputtering, printing, electro plating, electroless plating, and commonly used chemical vapor deposition (CVD) methods. For example, electro-chemical plating (ECP) is carried out to form the Cu layer 28. In an exemplary embodiment, the thickness of the Cu layer 28 is greater than 30 μm. In another exemplary embodiment, the thickness of the Cu layer 28 is greater than 40 μm. For example, the Cu layer 28 is of about 40-50 μm thickness, or about 40-70 μm thickness, although the thickness may be greater or smaller.
Next, as shown in
Next, as depicted in
The connection structure 32 may further include a solder layer. Referring to
The substrate 10 is then sawed and packaged onto a package substrate, or another die, with solder balls or Cu bumps mounted on a pad on the package substrate or the other die.
The structure shown in
In the preceding detailed description, the disclosure is described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications, structures, processes, and changes may be made thereto without departing from the broader spirit and scope of the disclosure. The specification and drawings are, accordingly, to be regarded as illustrative and not restrictive. It is understood that the disclosure is capable of using various other combinations and environments and is capable of changes or modifications within the scope of inventive concepts as expressed herein.
Claims
1. An integrated circuit device, comprising:
- a semiconductor substrate;
- a bond pad region on the semiconductor substrate;
- a copper pillar bump overlying and electrically connected to the bond pad region; and
- a barrier layer on a surface of the copper pillar bump, wherein the barrier layer is a copper-containing material layer comprising at least one of a group III element, a group IV element and a group V element.
2. The integrated circuit device of claim 1, wherein the barrier layer is a CuGeN layer.
3. The integrated circuit device of claim 1, wherein the barrier layer is a copper-containing material layer comprising at least one of germanium (Ge), silicon (Si) and carbon (C).
4. The integrated circuit device of claim 1, wherein the barrier layer is a copper-containing material layer comprising at least one of nitrogen (N) or phosphorus (P).
5. The integrated circuit device of claim 1, wherein the barrier layer is a copper-containing material layer comprising boron (B).
6. The integrated circuit device of claim 1, further comprising a solder layer on the barrier layer.
7. The integrated circuit device of claim 1, further comprising:
- a passivation layer overlying the semiconductor substrate and exposing a portion of the bond pad region;
- an interconnect line formed on the passivation layer and electrically connected to the bond pad region; and
- a polymer layer overlying the passivation layer and exposing a portion of the interconnect line;
- wherein the copper pillar bump is formed overlying the polymer layer and electrically connected to the exposed portion of the interconnect line.
8. The integrated circuit device of claim 7, wherein the interconnect line comprises copper.
9. The integrated circuit device of claim 7, wherein the passivation layer comprises polybenzoxazole (PBO).
10. The integrated circuit device of claim 7, wherein the polymer layer comprises polybenzoxazole (PBO).
11. A flip-chip assembly comprising:
- a first substrate;
- a second substrate;
- a joint structure disposed between the first substrate and the second substrate;
- wherein the joint structure comprises a connection structure between the first substrate and the second substrate and a joint solder layer between the connection structure and the second substrate; and
- an intermetallic compound (IMC) layer between the connection structure and the joint solder layer, wherein the IMC layer has a thickness less than 2 μm.
12. The flip-chip assembly of claim 11, wherein the connection structure comprises a copper pillar bump.
13. The flip-chip assembly of claim 12, wherein the connection structure comprises a barrier layer on a surface of the copper pillar bump.
14. The flip-chip assembly of claim 13, wherein the barrier layer is a copper-containing material layer comprising at least one of a group III element, a group IV element and a group V element.
15. The flip-chip assembly of claim 13, wherein the barrier layer is a CuGeN layer.
16. The flip-chip assembly of claim 13, wherein the copper-containing material layer comprises at least one of germanium (Ge), silicon (Si) or carbon (C).
17. The flip-chip assembly of claim 13, wherein the copper-containing material layer comprises at least one of nitrogen (N) or phosphorus (P).
18. The flip-chip assembly of claim 13, wherein the copper-containing material layer comprises boron (B).
19. The flip-chip assembly of claim 11, wherein the first substrate comprises:
- a passivation layer overlying the first substrate;
- an interconnect line formed on the passivation layer; and
- a polymer layer overlying the passivation layer and exposing a portion of the interconnect line;
- wherein the connection structure is overlying and electrically connected to the exposed portion of the interconnect line.
20. The flip-chip assembly of claim 19, wherein the interconnect line comprises copper, and the polymer layer comprises polybenzoxazole (PBO).
Type: Application
Filed: Nov 5, 2010
Publication Date: May 5, 2011
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (Hsinchu)
Inventors: Chien Ling HWANG (Hsinchu), Yi-Wen WU (Xizhi City), Chung-Shi LIU (Shinchu)
Application Number: 12/940,196
International Classification: H01L 23/52 (20060101);