Nonvolatile Memory Device and Manufacturing Method Thereof
A nonvolatile memory device comprises a gate insulating layer, a floating gate and a dielectric layer sequentially formed over a semiconductor substrate, a capping layer formed over the dielectric layer, and a control gate formed over the capping layer, wherein the control gate includes nitrogen or carbon as an additive.
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Priority to Korean patent application number 10-2009-0134122 filed Dec. 30, 2009, the entire disclosure of which is incorporated by reference herein, is claimed.
BACKGROUNDExemplary embodiments relate generally to a method of manufacturing nonvolatile memory devices and, more particularly, to a method of manufacturing nonvolatile memory devices that is capable of preventing the generation of voids when forming a control gate.
A nonvolatile memory device includes a floating gate for storing data and a control gate for transferring driving voltages.
A method of forming the nonvolatile memory device is described below.
A gate insulating layer and a conductive layer for floating gates are formed over a semiconductor substrate. The conductive layer and the gate insulating layer are patterned to expose the semiconductor substrate, and some of the exposed semiconductor substrate is etched to form trenches for isolation. The trenches are filled with an insulating material to form isolation layers, and an etch process for lowering the height of the isolation layers is performed. A dielectric layer is formed on the entire surface, and a conductive layer for control gates is formed over the dielectric layer.
Meanwhile, with increases in the degree of integration of nonvolatile memory devices, not only the width of the floating gate, but also a gap between neighboring floating gates is narrowed.
Accordingly, after forming the dielectric layer, when forming the conductive layer for control gates, voids can be generated between the conductive layers for floating gates. Thus, voids can be generated on a surface of the dielectric layer and in the control gates.
If voids are generated as described above, resistance of the control gate can be increased when the memory device is operated, and there may be a difference in the electrical characteristics between a region in which voids have occurred and a region in which voids have not occurred. Accordingly, reliability of the nonvolatile memory device may be degraded.
BRIEF SUMMARYExemplary embodiments relate to a method of manufacturing nonvolatile memory devices that is capable of preventing the generation of voids in a process of forming a control gate.
A nonvolatile memory device according to an aspect of the disclosure comprises a gate insulating layer, a floating gate and a dielectric layer sequentially formed over a semiconductor substrate, a capping layer formed over the dielectric layer, and a control gate formed over the capping layer, wherein the control gate includes polysilicon in which nitrogen or carbon as an additive is contained.
A nonvolatile memory device according to an aspect of the disclosure comprises a gate insulating layer, floating gate and dielectric layer sequentially formed over a semiconductor substrate, a capping layer formed over the dielectric layer, and a control gate formed over the capping layer, wherein the control gate contains additive for having a nano sized grain.
A nonvolatile memory device according to an aspect of the disclosure comprises a gate insulating layer and a floating gate and dielectric layer sequentially formed over a semiconductor substrate of an active region defined by isolation layers, a dielectric layer formed along a surface of the isolation layers and the floating gate, a capping layer formed along a surface of the dielectric layer, and a control gate formed over the capping layer, wherein the control gate contains nitrogen or carbon as an additive for a nano sized grain.
A method of manufacturing nonvolatile memory devices according to an aspect of the disclosure comprises forming a sequentially stacked gate insulating layer and a floating gate over a semiconductor substrate, forming a dielectric layer along a surface of a whole structure including the floating gate, forming a capping layer along a surface of the dielectric layer, forming a conductive layer of an amorphous layer over the capping layer, wherein the conductive layer contains additives, performing an annealing process to crystallize the capping layer and the conductive layer, and removing voids or seams which may occur during formation of the conductive layer.
Hereinafter exemplary embodiments of the disclosure are described in detail with reference to the accompanying drawings. The drawing figures are provided to allow those having ordinary skill in the art to understand the scope of the embodiments of this disclosure.
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More particularly, the capping layer 112 preferably comprises a polysilicon layer and preferably is relatively thin (for example 5 Å to 50 Å) by taking the aspect ratio between the floating gates 104a into consideration.
After forming the capping layer 112, impurities are added to the capping layer 112 for the purpose of prohibiting the generation of voids in a subsequent process of forming a third conductive layer (114 of
The process of adding the impurities in the capping layer 112 preferably is performed in-situ in the same chamber after forming the capping layer 112.
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Furthermore, since the capping layer 112 containing the impurities is formed, voids can be prevented from occurring on the surface of the dielectric layer 110 or within the third conductive layer 114 in the process of forming the third conductive layer 114. Since the generation of voids is prevented, an increase of resistance of the control gate can be prevented, thereby improving reliability of the nonvolatile memory devices.
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Next, the insulating materials are isolated from each other by performing a polishing process (for example, chemical mechanical polishing (CMP)) until the isolation mask patterns (206 of
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After forming the capping layer 216, impurities are added to the capping layer 216 to prevent voids from occurring on the surface of the dielectric layer 214 or within the control gate in a subsequent process of forming a third conductive layer (218 of
The process of containing the impurities in the capping layer 216 preferably is performed in-situ in the same chamber after forming the capping layer 216.
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Furthermore, the process of forming the third conductive layer 218 preferably is performed in-situ by using the same chamber after the process of adding the impurities to the capping layer 216 is performed.
Since the process of forming the capping layer 216, the process of containing the impurities, and the process of forming the third conductive layer 218 preferably are performed in-situ in the same chamber as described above, the turnaround time may be reduced.
In the process of forming the third conductive layer 218 as described above, voids can be prevented from occurring in the region between the protruded second conductive patterns 210a for floating gates. Since the generation of voids can be prevented, an increase of resistance of the control gate can be prevented, thereby improving reliability of the nonvolatile memory devices.
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Next, the annealing process is performed to crystallize the third conductive layer 314 and the capping layer 312. Voids or seams may be removed during the annealing process. The annealing process is performed to a temperature of 800° C. to 1000° C. and N2 gas atmosphere within 2 hours. The capping layer 312 and the third conductive layer 314 become a polysilicon by crystallizing during the annealing process. More particularly, the third conductive layer 314 which was an amorphous layer is changed to a crystallized polysilicon layer by the additive contained in the third conductive layer 314. Here, the voids or seams are dispersed and then changed to micro voids so that the defect by the voids or seams can be prevented from occurring in the region between the protruded floating gate. Furthermore, a turnaround time (TAT) may be improved by using single type equipment instead of a furnace for the annealing process.
Next, a metal layer 316 is further formed over the third conductive layer 314 to lower resistance so that a control gate comprises the capping layer 312, the third conductive layer 314 and the metal layer 316.
According to the disclosure, the capping layer is formed on a surface of the dielectric layer, and impurities for accelerating the formation of a conductive material for a control gate are added to the capping layer. Accordingly, the generation of voids can be prevented in the process of forming the control gate. Consequently, reliability of nonvolatile memory devices can be improved because deterioration of an electrical characteristic can be prevented.
Claims
1. A nonvolatile memory device, comprising:
- a gate insulating layer, a floating gate and a dielectric layer sequentially formed over a semiconductor substrate;
- a capping layer formed over the dielectric layer; and
- a control gate formed over the capping layer, wherein the control gate includes polysilicon in which nitrogen or carbon is contained as an additive.
2. The nonvolatile memory device of claim 1, wherein the floating gate comprises an undoped polysilicon layer and a doped polysilicon layer formed over the undoped polysilicon layer.
3. The nonvolatile memory device of claim 1, further comprising additives which are contained in the floating gate.
4. The nonvolatile memory device of claim 1, wherein impurity is injected into the control gate.
5. The nonvolatile memory device of claim 4, wherein the impurity comprises boron (B) or phosphorous (P).
6. A nonvolatile memory device, comprising:
- a gate insulating layer, a floating gate and a dielectric layer sequentially formed over a semiconductor substrate;
- a capping layer formed over the dielectric layer; and
- a control gate formed over the capping layer, wherein the control gate comprises a nano sized grain by containing an additive.
7. The nonvolatile memory device of claim 6, wherein the floating gate comprises an undoped polysilicon layer and a doped polysilicon layer formed over the undoped polysilicon layer.
8. The nonvolatile memory device of claim 6, further comprising additive which is contained in the floating gate.
9. The nonvolatile memory device of claim 8, wherein the additive comprises nitride (N) or carbon (C).
10. The nonvolatile memory device of claim 6, wherein the control gate includes impurity to have a conductive characteristic.
11. The nonvolatile memory device of claim 10, wherein the impurity comprises boron (B) or phosphorous (P).
12. A method of manufacturing nonvolatile memory devices, comprising:
- forming a sequentially stacked gate insulating layer and a floating gate over a semiconductor substrate;
- forming a dielectric layer along a surface of a whole structure including the floating gate;
- forming a capping layer along a surface of the dielectric layer;
- forming a conductive layer of an amorphous layer over the capping layer, wherein the conductive layer contains additives;
- performing an annealing process to crystallize the capping layer and the conductive layer.
13. The method of claim 12, wherein the capping layer comprises an amorphous silicon layer.
14. The method of claim 12, comprising forming the capping layer using a disilane (Si2H6) gas as a source gas.
15. The method of claim 12, wherein the conductive layer comprises an amorphous doped silicon layer.
16. The method of claim 12, wherein the conductive layer is formed by using a source gas and an additive gas and injecting impurity.
17. The method of claim 16, wherein the source gas comprises monosilane (SiH4) gas.
18. The method of claim 16, wherein the additive gas comprises NH3 gas or C2H4 gas.
19. The method of claim 18, wherein the conductive layer contains nitrogen as an additive when NH3 gas is used, and contains carbon as the additive when C2H4 gas is used.
20. The method of claim 12, wherein boron or phosphorous are injected into the control gate.
Type: Application
Filed: Dec 6, 2011
Publication Date: Mar 29, 2012
Applicant: HYNIX SEMICONDUCTOR INC. (Icheon-si)
Inventors: Chul Young Ham (Guri-si), Min Sik Jang (Icheon-si), Sang Soo Lee (Songpa-gu)
Application Number: 13/312,569
International Classification: H01L 29/788 (20060101); H01L 21/336 (20060101);