To Produce Devices Each Consisting Of Plurality Of Components, E.g., Integrated Circuits (epo) Patents (Class 257/E21.602)

  • Patent number: 10879212
    Abstract: Representative implementations of techniques and methods include processing singulated dies in preparation for bonding. A plurality of semiconductor die components may be singulated from a wafer component, the semiconductor die components each having a substantially planar surface. Particles and shards of material may be removed from edges of the plurality of semiconductor die component. Additionally, one or more of the plurality of semiconductor die components may be bonded to a prepared bonding surface, via the substantially planar surface.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: December 29, 2020
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Cyprian Emeka Uzoh, Guilian Gao, Laura Wills Mirkarimi, Gaius Gillman Fountain, Jr.
  • Patent number: 10820407
    Abstract: An electronic structure includes a plurality of electronic devices arranged in the form of a matrix array including a first number of rows, the electronic devices of each row being connected in series, the matrix array further including a plurality of switches, the rows of the matrix array being distributed in a second number of groups intended to be connected in series by the switches, the groups connected in series being supplied with an electrical supply current, at least one of the groups including at least two rows connected in parallel so as to distribute the supply current between the at least two rows.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: October 27, 2020
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Bertrand Chambion
  • Patent number: 10702946
    Abstract: A substrate has a first surface with at least one division line formed thereon and a second surface opposite the first surface. The substrate is processed by applying a pulsed laser beam from the side of the first surface. The substrate is transparent to the pulsed laser beam. The pulsed laser beam is applied at least in a plurality of positions along the at least one division line, a focal point of the pulsed laser beam located at a distance from the first surface in the direction from the first surface towards the second surface, so as to form a plurality of modified regions inside the substrate. Each modified region is entirely within the bulk of the substrate, without any openings open to the first surface or the second surface. Substrate material is removed along the at least one division line where the modified regions are present.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: July 7, 2020
    Assignee: DISCO CORPORATION
    Inventors: Hiroshi Morikazu, Karl Heinz Priewasser, Nao Hattori
  • Patent number: 10461043
    Abstract: The present disclosure provides electromagnetic shielding for integrated circuit (IC) modules. First, a precursor package with a number of IC modules is provided. The precursor package is then placed onto a chemical resistant tape. After a sweller process and a desmear process are performed, the chemical resistant tape is removed. Next, the precursor package is singulated to form a number of individual IC modules. The individual IC modules are placed onto a carrier tape, such that a bottom surface of each individual IC module is covered by the carrier tape, and a top surface and side surfaces of each individual IC module are exposed. A shielding structure is applied completely over the top surface and the side surfaces of each individual IC module. Herein, the shielding structure is electrically coupled to a ground plane within each individual IC module.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: October 29, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Stephen Craig Parker, James Edwin Culler, Jr., Donald Joseph Leahy
  • Patent number: 10388670
    Abstract: Provided is a semiconductor device which has low power consumption and can operate at high speed. The semiconductor device includes a memory element including a first transistor including crystalline silicon in a channel formation region, a capacitor for storing data of the memory element, and a second transistor which is a switching element for controlling supply, storage, and release of charge in the capacitor. The second transistor is provided over an insulating film covering the first transistor. The first and second transistors have a source electrode or a drain electrode in common.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: August 20, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshinori Ieda, Atsuo Isobe, Yutaka Shionoiri, Tomoaki Atsumi
  • Patent number: 9941167
    Abstract: The method includes a laser scribing step of forming an opening including an exposing portion, where the first layer is exposed, by irradiating the dividing region of the substrate with laser light from the first main surface side, forming a remaining region on which the second layer in the dividing region remains around the opening other than the exposing portion, and forming a first damaged region of a surface layer portion of the first layer including the exposing portion and a second damaged region of a surface layer portion of the first layer to be covered by the remaining region on the first layer of the dividing region.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: April 10, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Bunzi Mizuno, Shogo Okita, Mitsuru Hiroshima, Tutomu Sakurai, Noriyuki Matsubara
  • Patent number: 9805679
    Abstract: The disclosure is related to a scan driving circuit for an oxide semiconductor thin film transistor and the NOR gate logic operation circuit thereof. The NOR gate logic operation circuit includes a first invertor and a second invertor applied in the pull down holding circuit of the GOA circuit, and a plurality of transistors. The combination of the NTFT and the invertor displaces the original function of the PMOS element to realize a characteristic similar to an original COMS NOR operation circuit, thereby solving a design problem of the logic operation circuit using a IGZO TFT single element, such that a larger scale digital integrated circuit is further suitably integrated into the liquid crystal display.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: October 31, 2017
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Chao Dai
  • Patent number: 9793222
    Abstract: Packages and packaging techniques for providing EMI shielding are described. In an embodiment, a package includes an electrically conductive ground structure on a ground pad at a periphery of a package substrate. The electrically conductive ground structure is encapsulated in a molding compound, and a surface of the electrically conductive ground structure is exposed at a side surface of the molding compound. An electrically conductive shield layer is on top and side surfaces of the molding compound, and in physical contact with the surface of the exposed electrically conductive ground structure.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: October 17, 2017
    Assignee: Apple Inc.
    Inventor: MyungHo Lee
  • Patent number: 9773810
    Abstract: Provided is a semiconductor device which has low power consumption and can operate at high speed. The semiconductor device includes a memory element including a first transistor including crystalline silicon in a channel formation region, a capacitor for storing data of the memory element, and a second transistor which is a switching element for controlling supply, storage, and release of charge in the capacitor. The second transistor is provided over an insulating film covering the first transistor. The first and second transistors have a source electrode or a drain electrode in common.
    Type: Grant
    Filed: August 3, 2015
    Date of Patent: September 26, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshinori Ieda, Atsuo Isobe, Yutaka Shionoiri, Tomoaki Atsumi
  • Patent number: 9601437
    Abstract: Consistent with an example embodiment, a method for preparing integrated circuit (IC) device die from a wafer substrate having a front-side with active devices and a back-side, comprises mounting the front-side of the wafer onto protective foil. A laser is applied to saw lane areas on the backside of the wafer, at a first focus depth to define a modification zone; the modification zone defined at a pre-determined depth within active device boundaries and the active device boundaries defined by the saw lane areas. The protective foil is stretched to separate IC device die from one another and expose active device side-walls. With dry-etching of the active device side-walls, the modification zone is substantially removed.
    Type: Grant
    Filed: September 9, 2014
    Date of Patent: March 21, 2017
    Assignee: NXP B.V.
    Inventors: Guido Albermann, Sascha Moeller, Thomas Rohleder, Martin Lapke, Hartmut Buenning
  • Patent number: 9589905
    Abstract: A semiconductor package includes a substrate, a chip disposed over a top surface of the substrate, an electromagnetic interference (EMI) shielding layer disposed over the substrate such that the EMI shielding layer surrounds the chip, a ground pad disposed in the substrate to contact a bottom surface of the substrate, and a test pad disposed in the substrate to contact the bottom surface of the substrate and spaced apart from the ground pad. A method of testing the semiconductor package is performed using a loop circuit to which a current is applied, the loop circuit being formed by electrically coupling the ground pad, the EMI shielding layer, and the test pad.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: March 7, 2017
    Assignee: SK HYNIX INC.
    Inventors: Hyung Ju Choi, Jong Hyun Kim
  • Patent number: 9401333
    Abstract: According to one embodiment, a semiconductor device includes a circuit substrate, a semiconductor element, a sealing resin layer, and a conductive shielding layer. The circuit substrate includes an insulating layer, a plurality of interconnections forming first interconnection layers provided on an upper surface side of the insulating layer, a plurality of interconnections forming second interconnection layers provided on a lower surface side of the insulating layer, and a plurality of vias penetrating from the upper surface to the lower surface of the insulating layer. The semiconductor element is mounted on the upper surface side of the circuit substrate. The conductive shielding layer covers the sealing resin layer and part of an end portion of the circuit substrate. Any of the plurality of vias and the conductive shielding layer are electrically connected.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: July 26, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Keiju Yamada, Masaaki Ishida
  • Patent number: 9385090
    Abstract: A semiconductor device includes a conductive shield layer that has a first portion covering a surface of a sealing resin layer and a second portion covering side surfaces of the sealing resin layer and side surfaces of the substrate. Portions of wiring layers, including a grounding wire, on or in the substrate have cut planes which are exposed to the side surfaces of the substrate and spread out in a thickness direction of the substrate. A cut plane of the grounding wire is electrically connected to the shield layer. An area of the cut plane of the grounding wire is larger than an area of a cross section of the grounding wire parallel to, and inward of the substrate from, the cut plane of the grounding wire.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: July 5, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Katsunori Shibuya, Takashi Imoto, Soichi Homma, Takeshi Watanabe, Yuusuke Takano
  • Patent number: 9023688
    Abstract: A method for processing a semiconductor device, the method including; providing a first semiconductor layer including first transistors; forming interconnection layers overlying the transistors, where the interconnection layers include copper or aluminum; forming a shielding heat conducting layer overlaying the interconnection layers; forming an isolation layer overlaying the shielding heat conducting layer; forming a second semiconductor layer overlying the isolation layer, and processing the second semiconductor layer at a temperature greater than about 400° C., where the interconnection layers are kept at a temperature below about 400° C.
    Type: Grant
    Filed: June 7, 2014
    Date of Patent: May 5, 2015
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Albert Karl Henning
  • Patent number: 9012305
    Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask is patterned with a laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. Subsequent to patterning the mask, the exposed regions of the semiconductor wafer are cleaned with an anisotropic plasma process non-reactive to the exposed regions of the semiconductor wafer. Subsequent to cleaning the exposed regions of the semiconductor wafer, the semiconductor wafer is plasma etched through the gaps in the patterned mask to singulate the integrated circuits.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: April 21, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Wei-Sheng Lei, Jungrae Park, James S. Papanu, Brad Eaton, Ajay Kumar
  • Patent number: 9006756
    Abstract: An aggregation of semiconductor devices, comprising: a first layer comprising a first surface and a second surface; a second layer comprising a first region and a second region; and a plurality of semiconductor devices disposed between the first layer and the second region wherein a shape of the second region comprises a curve and a mark.
    Type: Grant
    Filed: June 5, 2013
    Date of Patent: April 14, 2015
    Assignee: Epistar Corporation
    Inventors: Hsu-Cheng Lin, Ching-Yi Chiu, Pei-Shan Fang, Chun-Chang Chen
  • Patent number: 8999813
    Abstract: A method of forming a focal plane array by: forming a first wafer having sensing material provided on a surface, which is covered by a sacrificial layer, the sensing material being a thermistor material defining at least one pixel; providing supporting legs for the pixel within the sacrificial layer, covering them with a further sacrificial layer and forming first conductive portions in the surface of the sacrificial layer that are in contact with the supporting legs; forming a second wafer having read-out integrated circuit (ROIC), the second wafer being covered by another sacrificial layer, into which is formed second conductive portions in contact with the ROIC; bringing the sacrificial oxide layers of the first wafer and second wafer together such that the first and second conductive portions are aligned and bonding them together such that the sensing material is transferred from the first wafer to the second wafer when a sacrificial bulk layer of the first wafer is removed; and removing the sacrificial l
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: April 7, 2015
    Assignee: SensoNor AS
    Inventors: Adriana Lapadatu, Gjermund Kittilsland
  • Patent number: 8980727
    Abstract: Approaches for patterning semiconductor or other wafers and dies are described. For example, a method of patterning features within a substrate involves forming a mask layer above a surface of a semiconductor or glass substrate. The method also involves laser ablating the mask layer to provide a pattern of openings through the mask layer. The method also involves plasma etching portions of the semiconductor or glass substrate through the pattern of openings to provide a plurality of trenches in the semiconductor or glass substrate. The plurality of trenches has a pattern corresponding to the pattern of openings and comprising a pattern of through-substrate-via openings or redistribution layer (RDL) openings. The method also involves, subsequent to the plasma etching, removing the mask layer.
    Type: Grant
    Filed: May 7, 2014
    Date of Patent: March 17, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Wei-Sheng Lei, Brad Eaton, Ajay Kumar
  • Patent number: 8975163
    Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer comprising a plurality of integrated circuits involves forming a mask above the semiconductor wafer. The mask includes a layer covering and protecting the integrated circuits. The semiconductor wafer has a thickness. The method also involves laser scribing the mask and a majority of the thickness of the semiconductor wafer to provide scribe lines in the mask and the semiconductor wafer. The scribe lines are formed between the integrated circuits. The method also involves plasma etching the semiconductor wafer through the scribe lines to singulate the integrated circuits.
    Type: Grant
    Filed: April 10, 2014
    Date of Patent: March 10, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Wei-Sheng Lei, James S. Papanu, Brad Eaton, Ajay Kumar
  • Patent number: 8975748
    Abstract: An electronic device includes: a base layer; a first layer located at least partially over the base layer; a second layer located at least partially over the first layer; a first metal layer located at least partially over the second layer, wherein one or more signal outputs of the electronic device are formed in the first metal layer; and a second metal layer located at least partially over the first metal layer, wherein one or more gate connection is formed in the second metal layer, wherein removing a portion of the second metal layer disrupts at least one gate connection and deactivates the device.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: March 10, 2015
    Assignee: Secure Silicon Layer, Inc.
    Inventor: William Eli Thacker, III
  • Patent number: 8952497
    Abstract: A wafer includes a plurality of chips arranged as rows and columns. A first plurality of scribe lines is between the rows of the plurality of chips. Each of the first plurality of scribe lines includes a metal-feature containing scribe line comprising metal features therein, and a metal-feature free scribe line parallel to, and adjoining, the metal-feature containing scribe line. A second plurality of scribe lines is between the columns of the plurality of chips.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: February 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: U-Ting Chen, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Jeng-Shyan Lin, Shuang-Ji Tsai
  • Patent number: 8927393
    Abstract: Methods and systems for dicing a semiconductor wafer including a plurality of integrated circuits (ICs) are described. In one embodiment, a method involves adhering an adhesive tape to a thin water soluble dry film. The method involves applying the thin water soluble dry film adhered to the adhesive tape over a surface of the semiconductor wafer. The method involves removing the adhesive tape from the thin water soluble dry film. The thin water soluble dry film is patterned with a laser scribing process, exposing regions of the semiconductor wafer between the ICs. The method involves etching the semiconductor wafer through gaps in the patterned thin water soluble dry film, and removing the thin water soluble dry film.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: January 6, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Wei-Sheng Lei, James S. Papanu, Prabhat Kumar, Brad Eaton, Ajay Kumar
  • Patent number: 8912077
    Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The semiconductor wafer is supported by a substrate carrier. The mask is then patterned with a laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to singulate the integrated circuits while supported by the substrate carrier.
    Type: Grant
    Filed: June 15, 2011
    Date of Patent: December 16, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Saravjeet Singh, Brad Eaton, Ajay Kumar, Wei-Sheng Lei, James M. Holden, Madhava Rao Yalamanchili, Todd J. Egan
  • Patent number: 8884403
    Abstract: According to the invention, die shift is reduced or substantially eliminated, by cutting the wafer in two stages. In some embodiments a first wafer cutting procedure is carried out prior to thinning the wafer to the prescribed die thickness; and in other embodiments the wafer is thinned to the prescribed die thickness prior to carrying out a first wafer cutting procedure. The first wafer cutting procedure includes cutting along a first set of streets to a depth greater than the prescribed die thickness and optionally along a second set of streets to a depth less than the die thickness. The result of the first cutting procedure is an array of strips or blocks of die, each including a plurality of connected die, that are less subject to shift than are individual singulated die. In a second wafer cutting procedure the die are singulated by cutting through along the second set of streets.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: November 11, 2014
    Assignee: Iinvensas Corporation
    Inventors: Reynaldo Co, DeAnn Eileen Melcher, Weiping Pan, Grant Villavicencio
  • Patent number: 8865564
    Abstract: A process is provided for producing at least one interconnecting well to achieve a conductive pathway between at least two connection layers of a component comprising a stack of at least one first substrate and one second substrate which are electrically insulated from one another, the process including defining a surface contact region of a surface connection layer over a surface of the stack and of at least one first contact region embedded in the stack starting from a first embedded connection layer of the first substrate. A region devoid of material is positioned between the first substrate and second substrates and which comprises a stage of producing a interconnecting well which passes through the second substrate and extends between the surface contact region and the first embedded contact region and passes through the region devoid of material, and also a first layer which covers the first embedded connection layer.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: October 21, 2014
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Audrey Berthelot, Jean-Philippe Polizzi
  • Patent number: 8835893
    Abstract: A phase change memory cell and methods of fabricating the same are presented. The memory cell includes a variable resistance region and a top and bottom electrode. The shapes of the variable resistance region and the top electrode are configured to evenly distribute a current with a generally hemispherical current density distribution around the first electrode.
    Type: Grant
    Filed: May 9, 2012
    Date of Patent: September 16, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Jun Liu, Mike Violette
  • Patent number: 8822268
    Abstract: Embodiments of a method for fabricating Redistributed Chip Packages are provided, as are embodiments of Redistributed Chip Packages. In one embodiment, the method includes the steps/processes of embedding a first semiconductor die and a microelectronic component in a molded panel having a frontside, the first semiconductor die comprising a plurality of bond pads over which a plurality of raised contacts has been formed. The frontside of the molded panel is polished to impart the molded panel with a substantially planar surface through which the terminals of the microelectronic component and the plurality of raised contacts are exposed. Finally, at least one redistribution layer is build or produced over the substantially planar surface to electrically interconnect the first semiconductor die and the microelectronic component.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: September 2, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Alan J. Magnus
  • Patent number: 8815652
    Abstract: The present invention is a manufacturing method for a semiconductor device having steps of; aligning a program head 80 having a program dot array corresponding to each OTP-ROM cell array 21 provided in areas 12 to be a plurality of semiconductor chips arranged in a semiconductor wafer to the OTP-ROM cell array 21 in one of the areas to be the plurality of semiconductor chips 12; and programming the OTP-ROM cell array 21 with a different pattern for each of the areas to be the plurality of semiconductor chips 12 by using the program head 80.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: August 26, 2014
    Assignee: Spansion LLC
    Inventors: Fumihiko Inoue, Kentaro Sera
  • Patent number: 8800475
    Abstract: Semiconductor die break strength and yield are improved with a combination of laser dicing and etching, which are followed by dicing an underlying layer of material, such as die attach film (DAF) or metal. A second laser process or a second etch process may be used for dicing of the underlying layer of material. Performing sidewall etching before cutting the underlying layer of material reduces or prevents debris on the kerf sidewalls during the sidewall etching process. A thin wafer dicing laser system may include either a single laser process head solution or a dual laser process head solution to meet throughput requirements.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: August 12, 2014
    Assignee: Electro Scientific Industries, Inc.
    Inventor: Daragh S. Finn
  • Patent number: 8796794
    Abstract: The present disclosure relates to the fabrication of spin transfer torque memory elements for non-volatile microelectronic memory devices. The spin transfer torque memory element may include a magnetic tunneling junction connected with specifically sized and/or shaped fixed magnetic layer that can be positioned in a specific location adjacent a free magnetic layer. The shaped fixed magnetic layer may concentrate current in the free magnetic layer, which may result in a reduction in the critical current needed to switch a bit cell in the spin transfer torque memory element.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: August 5, 2014
    Assignee: Intel Corporation
    Inventors: Brian S. Doyle, David L. Kencke, Charles C. Kuo, Dmitri E. Nikonov, Robert S. Chau
  • Patent number: 8754515
    Abstract: Provided is a method of forming a package-on-package. An encapsulation is formed to cover a wafer using a wafer level molding process. The wafer includes a plurality of semiconductor chips and a plurality of through silicon vias (TSVs) passing through the semiconductor chips. The encapsulant may have openings aligned with the TSVs. The encapsulant and the semiconductor chips are divided to form a plurality of semiconductor packages. Another semiconductor package is stacked on one selected from the semiconductor packages. The other semiconductor package is electrically connected to the TSVs.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: June 17, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Hun Kim, Jin-Woo Park, Dae-Young Choi, Mi-Yeon Kim, Sun-Hye Lee
  • Patent number: 8754514
    Abstract: A multi-chip wafer level package comprises three stacked semiconductor dies. A first semiconductor die is embedded in a first photo-sensitive material layer. A second semiconductor die is stacked on top of the first semiconductor die wherein the second semiconductor die is face-to-face coupled to the first semiconductor die. A third semiconductor die is back-to-back attached to the second semiconductor die. Both the second semiconductor die and the third semiconductor die are embedded in a second photo-sensitive material layer. The multi-chip wafer level package further comprises a plurality of through assembly vias formed in the first photo-sensitive material layer and the second photo-sensitive material layer.
    Type: Grant
    Filed: August 10, 2011
    Date of Patent: June 17, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hui Yu, Chih-Hang Tung, Tung-Liang Shao, Chen-Hua Yu, Da-Yuan Shih
  • Patent number: 8723314
    Abstract: Various semiconductor workpieces and methods of dicing the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a channel in a metallization structure on a backside of a semiconductor workpiece. The semiconductor workpiece includes a substrate. The channel is in substantial alignment with a dicing street on a front side of the semiconductor chip.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: May 13, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Michael Su, Lei Fu, Edward S. Alcid
  • Publication number: 20140117469
    Abstract: A through-substrate via (TSV)-MEMS combination includes a TSV die including a substrate and a plurality of TSVs which extend of a full thickness of the substrate. The TSV die includes a top side surface including circuitry and top side bonding pads thereon, a bottom side surface including bottom side bonding features thereon, and a through-hole through the full thickness of the substrate. A microelectromechanical systems (MEMS) die having a floating sensing structure including solder balls thereon is bound to the top side bonding pads or bottom side bonding features of the TSV die. A layer of adhesive material is surrounding the solder balls, which can provide a sealant ring for the TSV-MEMS bonds.
    Type: Application
    Filed: October 26, 2012
    Publication date: May 1, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: YOSHIMI TAKAHASHI, KOHICHI KUBOTA
  • Patent number: 8710481
    Abstract: A non-volatile memory device includes a plurality of non-volatile memory cells. Each of the non-volatile memory cells includes a first electrode, a diode steering element, a storage element located in series with the diode steering element, a second electrode, and a nano-rail electrode having a width of 15 nm or less.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: April 29, 2014
    Assignee: SanDisk 3D LLC
    Inventors: James K. Kai, Henry Chien, George Matamis, Vinod R. Purayath
  • Publication number: 20140103489
    Abstract: An electronic device comprising a semiconductor structure having an integrated circuit back end capacitor and an integrated circuit back end thin film resistor and a method of manufacturing the same is provided. The semiconductor structure comprises a first dielectric layer, a bottom plate of the capacitor and a thin film resistor body. Furthermore, there is a second dielectric layer which is disposed on the bottom plate of the capacitor and on top of the thin film resistor body. A top plate of the capacitor is disposed on the second dielectric layer in a region of the second dielectric layer which is defined by the lateral dimensions of the bottom plate of the capacitor. The bottom plate and the resistor body are laterally spaced apart layers which are both disposed on the first dielectric layer and which are composed of a same thin film material.
    Type: Application
    Filed: October 17, 2012
    Publication date: April 17, 2014
    Applicant: TEXAS INSTRUMENTS DEUTSCHLAND GMBH
    Inventors: Christoph DIRNECKER, Berthold STAUFER
  • Publication number: 20140080259
    Abstract: In a manufacturing method for layered chip packages, a layered substructure with at least one additional package joined thereto is used to produce a plurality of layered chip packages. The layered substructure includes a plurality of main bodies to be separated from each other later. Each main body includes: a main part having top and bottom surfaces and including a plurality of layer portions stacked on each other; and a plurality of main terminals disposed on at least one of the top and bottom surfaces of the main part. The additional package includes an additional semiconductor chip and at least one additional terminal that is electrically connected to the additional semiconductor chip and in contact with at least one of the plurality of main terminals.
    Type: Application
    Filed: September 17, 2012
    Publication date: March 20, 2014
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Atsushi Iijima, Ryuji Fujii
  • Patent number: 8673741
    Abstract: Semiconductor die break strength and yield are improved with a combination of laser dicing and etching, which are followed by dicing an underlying layer of material, such as die attach film (DAF) or metal. A second laser process or a second etch process may be used for dicing of the underlying layer of material. Performing sidewall etching before cutting the underlying layer of material reduces or prevents debris on the kerf sidewalls during the sidewall etching process. A thin wafer dicing laser system may include either a single laser process head solution or a dual laser process head solution to meet throughput requirements.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: March 18, 2014
    Assignee: Electro Scientific Industries, Inc
    Inventor: Daragh S. Finn
  • Patent number: 8674333
    Abstract: Variable-resistance memory material cells are contacted by vertical bottom spacer electrodes. Variable-resistance material memory spacer cells are contacted along the edge by electrodes. Processes include the formation of the bottom spacer electrodes as well as the variable-resistance material memory spacer cells. Devices include the variable-resistance memory cells.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: March 18, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Jun Liu
  • Publication number: 20140061849
    Abstract: Various embodiments comprise apparatuses and methods including a memory array having alternating levels of semiconductor materials and dielectric material with strings of memory cells formed on the alternating levels. One such apparatus includes a memory array formed substantially within a cavity of a substrate. Peripheral circuitry can be formed adjacent to a surface of the substrate and adjacent to the memory array. Additional apparatuses and methods are described.
    Type: Application
    Filed: August 30, 2012
    Publication date: March 6, 2014
    Inventor: Toru Tanzawa
  • Publication number: 20140015008
    Abstract: The present invention discloses a transient voltage suppressor (TVS) circuit, and a diode device therefor and a manufacturing method thereof. The TVS circuit is for coupling to a protected circuit to limit amplitude of a transient voltage which is inputted to the protected circuit. The TVS circuit includes a suppressor device and at least a diode device. The diode device is formed in a substrate, which includes: a well formed in the substrate; a separation region formed beneath the upper surface; a anode region and a cathode region, which are formed at two sides of the separation region beneath the upper surface respectively, wherein the anode region and the cathode region are separated by the separation region; and a buried layer, which is formed in the substrate below the well with a higher impurity density and a same conductive type as the well.
    Type: Application
    Filed: July 15, 2012
    Publication date: January 16, 2014
    Inventors: Tsung-Yi Huang, Jin-Lian Su
  • Patent number: 8624300
    Abstract: Briefly, in accordance with one or more embodiments, multilayer memory device, comprising a lower deck and an upper deck disposed on the lower deck, the decks comprising one or more memory cells coupled via one or more contacts. An isolation layer is disposed between the upper deck, and one or more contacts are formed between the upper deck and the lower deck to couple one or more of the contact lines of the upper deck with one or more contact lines of the lower deck.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: January 7, 2014
    Assignee: Intel Corporation
    Inventors: Sanh D. Tang, John Zahurak, Shane Trapp, Krishna K. Parat
  • Patent number: 8617963
    Abstract: An integrated circuit wafer dicing method is provided. The method includes forming a plurality of integrated circuits and a plurality of test-keys on a wafer substrate, wherein the plurality of test-keys are disposed between the adjacent integrated circuits; forming a patterned protective film on the wafer to cover the plurality of integrated circuits and expose the plurality of test-keys; etching the plurality of test-keys by using the patterned protective film as a mask; and dicing an area between the plurality of integrated circuits to form a plurality of discrete integrated circuit dies.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: December 31, 2013
    Assignee: Raydium Semiconductor Corporation
    Inventors: Ching-San Lin, Kun-Tai Wu, Chih-Chao Wang
  • Patent number: 8618607
    Abstract: One illustrative device disclosed herein includes a continuous active region defined in a semiconducting substrate, first and second transistors formed in and above the continuous active region, each of the first and second transistors comprising a plurality of doped regions formed in the continuous active region, a conductive isolating electrode positioned above the continuous active region between the first and second transistors and a power rail conductively coupled to the conductive isolating electrode.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: December 31, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Mahbub Rashed, David Doman, Marc Tarabbia, Irene Lin, Jeff Kim, Chinh Nguyen, Steve Soss, Scott Johnson, Subramani Kengeri, Suresh Venkatesan
  • Patent number: 8609526
    Abstract: A method of forming an integrated circuit structure includes forming a copper-containing seed layer on a wafer, and performing a descum step on an exposed surface of the copper-containing seed layer. The descum step is performed using a process gas including fluorine and oxygen. A reduction/purge step is then performed on the exposed surface of the copper-containing seed layer using a nitrogen-containing gas. A copper-containing layer is plated on the copper-containing seed layer.
    Type: Grant
    Filed: July 23, 2010
    Date of Patent: December 17, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Shi Liu, Cheng-Chung Lin, Ming-Che Ho, Kuo Cheng Lin, Meng-Wei Chou
  • Patent number: 8604615
    Abstract: A stack of semiconductor chips, a semiconductor device, and a method of manufacturing are disclosed. The stack of semiconductor chips may comprise a first chip of the stack, a second chip of the stack over the first chip, conductive bumps, a homogeneous integral underfill material, and a molding material. The conductive bumps may extend between an upper surface of the first chip and a lower surface of the second chip. The homogeneous integral underfill material may be interposed between the first chip and the second chip, encapsulate the conductive bumps, and extend along sidewalls of the second chip. The homogeneous integral underfill material may have an upper surface extending in a direction parallel to an upper surface of the second chip and located adjacent the upper surface of the second chip.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: December 10, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chung-Sun Lee, Jung-Hwan Kim, Tae-Hong Min, Hyun-Jung Song, Sun-Pil Youn
  • Patent number: 8598016
    Abstract: Methods of dicing substrates by both laser scribing and plasma etching. A method includes forming an in-situ mask with a plasma etch chamber by accumulating a thickness of plasma deposited polymer to protect IC bump surfaces from a subsequent plasma etch. Second mask materials, such as a water soluble mask material may be utilized along with the plasma deposited polymer. At least some portion of the mask is patterned with a femtosecond laser scribing process to provide a patterned mask with trenches. The patterning exposing regions of the substrate between the ICs in which the substrate is plasma etched to singulate the IC and the water soluble material layer washed off.
    Type: Grant
    Filed: June 15, 2011
    Date of Patent: December 3, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Madhava Rao Yalamanchili, Wei-Sheng Lei, Brad Eaton, Saravjeet Singh, Ajay Kumar, Banqiu Wu
  • Publication number: 20130314146
    Abstract: The present description relates to a semiconductor device including an array of two or more switching elements and a controller electrically connected to the array of switching elements. At least one switching element of the array of switching elements has a different electrical resistance than at least another switching element of the array of switching elements. The controller is configured to generate and transmit at least one coarse tuning signal and at least one fine tuning signal. The array of switching elements is configured to alter an electrical resistance of the array of switching elements in response to the at least one coarse tuning signal and the at least one fine tuning signal. The present description also includes a method of making a semiconductor device and a method of using a semiconductor device.
    Type: Application
    Filed: May 22, 2012
    Publication date: November 28, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Mu-Shan Lin
  • Patent number: 8587985
    Abstract: A memory array with graded resistance lines includes a first set of lines intersecting a second set of lines. A line from one of the sets of lines includes a graded resistance along a length of the line.
    Type: Grant
    Filed: October 1, 2010
    Date of Patent: November 19, 2013
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jianhua Yang, John Paul Strachan, Wei Wu, Janice H. Nickel
  • Patent number: 8586392
    Abstract: A manufacturing method of a display device including a gate electrode film, a first electrode film, a second electrode film, and a conductive film connected to the first electrode film and formed of a conductive layer including a first conductive layer and a second conductive layer formed overlapping the first conductive layer. The method includes the steps of forming the first electrode film and the second electrode film, forming the conductive layer such that the conductive layer is connected to the first electrode film and the second electrode film, and forming the conductive film by removing regions other than predetermined regions of the conductive layer, wherein the conductive layer forming step includes the steps of forming the first conductive layer on the respective upper surfaces of the first electrode film and the second electrode film and forming the second conductive layer on the upper surface of the first conductive layer.
    Type: Grant
    Filed: January 11, 2011
    Date of Patent: November 19, 2013
    Assignees: Hitachi Displays, Ltd., Panasonic Liquid Crystal Display Co., Ltd.
    Inventors: Jun Gotoh, Eisuke Hatakeyama, Kenji Anjo, Yoshitomo Ogishima