INTERCONNECT STRUCTURES AND METHODS OF MANUFACTURING OF INTERCONNECT STRUCTURES
Interconnect structures and methods of manufacturing the same are disclosed herein. The method includes forming a barrier layer within a structure and forming an alloy metal on the barrier layer. The method further includes forming a pure metal on the alloy metal, and reflowing the pure metal such that the pure metal migrates to a bottom of the structure, while the alloy metal prevents exposure of the barrier layer. The method further includes completely filling in the structure with additional metal.
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The invention relates to semiconductor structures and methods of manufacture and, more particularly, to interconnect structures and methods of manufacturing the same.BACKGROUND
As device dimensions shrink, it becomes difficult to fill trenches and vias with copper in a damascene copper interconnect process. For example, copper can be used to fill a high aspect ratio trench/via through a migration process. That is, it is known that copper migrates at a much lower temperature than its melting point when the copper film has a thickness less than a few nanometers. This copper migration tends to accumulate at the bottom of the trench and/or via due to the so-called capillary phenomenon. More specifically, by utilizing this phenomenon, small trenches and/or vias are filled by: (1) deposition of ultra thin copper films (e.g., as thin as less than a few nanometers), and (2) heating the wafers at temperatures as low as 200° C. to 400° C. At these temperatures, the ultra thin copper films migrate to the bottom of the trenches and/or vias to partially fill the features from the bottom side. Since the actual aspect ratio which needs to be filled with a subsequent plating of copper becomes low, it becomes easier to fill such high aspect ratio features with copper plating.
However, due to the migration of the copper atoms at the interface of the underlying materials, e.g., diffusion barrier metals such as TaN and Ta, formed on sidewalls, the underlying materials become exposed, which makes subsequent electroplating of copper difficult. This is because it is difficult for the copper to adhere to the underlying exposed materials, e.g., TaN and Ta. Also, it is known that the migration of copper causes agglomeration of copper at the sidewalls of the trench/via which, in turn, forms isolated islands. These isolated islands, though, do not migrate to the bottom of the trench/via features because of the lost capillary phenomenon. It is also known that these agglomerated copper islands make it difficult for filling of the trenches and/or vias with electroplated copper. In other words, the low temperature migration of copper atoms which takes place when the copper film is ultra thin causes both agglomeration and migration of copper at the same time, which results in processing concerns.
More specifically, in conventional processes, after trench/via pattern definition, a liner of copper seed is formed along the sidewall of the trench/via before electroplating of copper. In the conventional process, when copper is heated for reflow, copper islands are formed due to the dewetting of the liner surface (i.e., disconnected flow of copper down to the bottom of the trench/via features). A resultant void is thus formed after the copper electroplating. Also, from the dewetted liner surface, no electroplating takes place, or early pinch off of the trench entrance occurs due to the copper island formation. In this latter situation, voids will remain in the trench/via features.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.SUMMARY
In a first aspect of the invention, a method comprises forming a barrier layer within a structure and forming an alloy metal on the barrier layer. The method further comprises forming a pure metal on the alloy metal, and reflowing the pure metal such that the pure metal migrates to a bottom of the structure, while the alloy metal prevents exposure of the barrier layer. The method further comprises completely filling in the structure with additional metal.
In another aspect of the invention, a method of forming an interconnect structure comprises forming a structure through an interlevel dielectric. The method further comprises forming a barrier layer on sidewalls of the structure and forming a copper alloy seed layer on the barrier layer. The method further comprises forming a pure copper film layer on the barrier layer. The method further comprises reflowing the pure copper film layer such that the pure copper film layer migrates into a bottom of the structure, while the copper alloy layer wets the barrier layer due to adhesion. The method further comprises filling the structure with an electroplated copper, directly on the reflowed pure copper, and capping the structure with a dielectric material.
In another aspect of the invention, a structure comprises a barrier layer on sidewalls of a via and trench structure. A copper alloy seed layer is on the barrier layer. A pure copper film layer is on the barrier layer and migrates to a bottom of the via and trench structure. An electroplated copper fills in remaining portions of the via and trench structure, directly on the reflowed pure copper. A dielectric material capping is provided over the filled via and trench structure.
In another aspect of the invention, a design structure tangibly embodied in a machine readable storage medium for designing, manufacturing, or testing an integrated circuit is provided. The design structure comprises the structures of the present invention. In further embodiments, a hardware description language (HDL) design structure encoded on a machine-readable data storage medium comprises elements that when processed in a computer-aided design system generates a machine-executable representation of the interconnect structures, which comprises the structures of the present invention. In still further embodiments, a method in a computer-aided design system is provided for generating a functional design model of the interconnect structures. The method comprises generating a functional representation of the structural elements of the tunable filter structures.
The present invention is described in the detailed description which follows, in reference to the noted plurality of drawings by way of non-limiting examples of exemplary embodiments of the present invention. Unless otherwise specified herein, the drawings are not to scale.
The invention relates to semiconductor structures and methods of manufacture and, more particularly, to interconnect structures and methods of manufacturing the same. In embodiments, the interconnect structures of the present invention include an improved liner surface, which prevents exposure of underlying barrier metals during a reheating or reflow process. The methods of the present invention thus prevent formation of voids, formation of agglomerated copper islands and pinch-off of the high aspect trenches and/or vias. Advantageously, copper (Cu) interconnect reliability, especially electromigration performance, is drastically improved by implementations of the present invention.
More specifically, in embodiments of the present invention, high aspect ratio trenches and/or vias are filled with a seed layer of copper comprising a copper alloy layer and a pure copper layer. The high aspect ratio trenches and/or vias can then be filled with reflowed copper and electroplated copper, without void formation or agglomeration. In embodiments, an optional additional copper alloy layer can also be provided over the pure copper layer, prior to electroplating copper processes. In implementation, the copper alloy layer ensures that a wet liner surface remains during the reflowing process, and is maintained during subsequent deposition processes. In this way, the interfacial barrier layer is not exposed during heating processes, thereby avoiding the formation of voids and other processing issues.
An interlevel dielectric material 14 is deposited on the wiring 12 and exposed portions of the substrate 10. In embodiments, the interlevel dielectric material 14 can be an oxide, formed using conventional CVD processes. A high aspect ratio via and trench structure 16 is formed in the interlevel dielectric material 14, using any conventional photolithographic and etching processes. For example, the high aspect ratio via and trench structure 16 can be formed using a conventional dual damascene process. In embodiments, the high aspect ratio via and trench structure 16 exposes an underlying wiring 12.
In embodiments, the via portion of the structure 16 can have a cross dimensional size “X” of about 20 nm to about 50 nm, with a preference of about 30 nm; although other dimensions are also contemplated by the present invention. In further embodiments, the trench portion of the structure 16 can have a cross dimensional size “Y” of about 3 microns; although other dimensions are also contemplated by the present invention.
Still referring to
The pure copper film layer 22 is then deposited on the copper alloy seed layer 20. The pure copper film layer 22 can have a thickness of about 10 nm; although other dimensions are also contemplated by the present invention. Preferably, the pure copper film layer 22 can be formed without breaking the vacuum, from the previous deposition process.
As shown in
After dielectric cap deposition and, in some case, after annealing of the copper lines after CMP, impurities in the copper alloy layer (e.g., M, Ti, etc.) redistribute to segregate at the top surface of the copper (e.g., layer 26), which improves the electromigration reliability of the copper interconnects, e.g., by preventing void formation. Thus, the resultant copper interconnect exhibits high reliability without having voids and with segregated alloy impurity atoms 26 at the copper surface, i.e., between the copper 22 and the dielectric layer 24.
As shown in
Also, it should be understood by those of skill in the art, that the steps of the depositing of the pure copper deposition and the heating can be repeated for multiple times without exposure of the underlying materials (e.g., TaN, Ta Ru, Co), in any of the aspects of the present invention. This is because of the presence of the copper alloy layer interfacing to the underlying materials. This repetition of the sequence gradually decreases the actual aspect ratio of the features for easier filling of the features (e.g., structure 16) with copper by electroplating. Also, the processes of the present invention can be provided in an in-situ vacuum thermal cycle or ex-situ reducing-ambient thermal cycle, which will render low-thermal-budget full-fill Cu damascene with appropriate alloy concentration.
Design flow 900 may vary depending on the type of representation being designed. For example, a design flow 900 for building an application specific IC (ASIC) may differ from a design flow 900 for designing a standard component or from a design flow 900 for instantiating the design into a programmable array, for example a programmable gate array (PGA) or a field programmable gate array (FPGA) offered by Altera® Inc. or Xilinx® Inc.
Design process 910 preferably employs and incorporates hardware and/or software modules for synthesizing, translating, or otherwise processing a design/simulation functional equivalent of the components, circuits, devices, or logic structures shown in
Design process 910 may include hardware and software modules for processing a variety of input data structure types including netlist 980. Such data structure types may reside, for example, within library elements 930 and include a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing technology (e.g., different technology nodes, 32 nm, 45 nm, 90 nm, etc.). The data structure types may further include design specifications 940, characterization data 950, verification data 960, design rules 970, and test data files 985 which may include input test patterns, output test results, and other testing information. Design process 910 may further include, for example, standard mechanical design processes such as stress analysis, thermal analysis, mechanical event simulation, process simulation for operations such as casting, molding, and die press forming, etc. One of ordinary skill in the art of mechanical design can appreciate the extent of possible mechanical design tools and applications used in design process 910 without deviating from the scope and spirit of the invention. Design process 910 may also include modules for performing standard circuit design processes such as timing analysis, verification, design rule checking, place and route operations, etc.
Design process 910 employs and incorporates logic and physical design tools such as HDL compilers and simulation model build tools to process design structure 920 together with some or all of the depicted supporting data structures along with any additional mechanical design or data (if applicable), to generate a second design structure 990.
Design structure 990 resides on a storage medium or programmable gate array in a data format used for the exchange of data of mechanical devices and structures (e.g., information stored in a IGES, DXF, Parasolid XT, JT, DRG, or any other suitable format for storing or rendering such mechanical design structures). Similar to design structure 920, design structure 990 preferably comprises one or more files, data structures, or other computer-encoded data or instructions that reside on transmission or data storage media and that when processed by an ECAD system generate a logically or otherwise functionally equivalent form of one or more of the embodiments of the invention shown in
Design structure 990 may also employ a data format used for the exchange of layout data of integrated circuits and/or symbolic data format (e.g., information stored in a GDSII (GDS2), GL1, OASIS, map files, or any other suitable format for storing such design data structures). Design structure 990 may comprise information such as, for example, symbolic data, map files, test data files, design content files, manufacturing data, layout parameters, wires, levels of metal, vias, shapes, data for routing through the manufacturing line, and any other data required by a manufacturer or other designer/developer to produce a device or structure as described above and shown in
The method as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
1. A method comprising:
- forming a barrier layer within a structure;
- forming an alloy metal on the barrier layer;
- forming a pure metal on the alloy metal;
- reflowing the pure metal such that the pure metal migrates to a bottom of the structure, while the alloy metal prevents exposure of the barrier layer;
- completely filling in the structure with additional metal; and
- comprising forming a layer of metal alloy on the pure metal, after the reflowing and prior to the filling in the structure.
2. The method of claim 1, wherein the alloy metal is a copper alloy.
3. The method of claim 2, wherein the pure metal is pure copper.
4. The method of claim 3, wherein the completely filling in the structure comprises electroplating copper within structure, over the pure copper.
5. The method of claim 2, wherein the metal alloy is one of CuAl, CuMn, CuTi and CuSn.
6. The method of claim 2, wherein the copper alloy wets the barrier layer during reflowing.
7. The method of claim 6, wherein the reflowing causes copper migration to the bottom of the structure without forming voids or agglomeration of copper islands.
9. The method of claim 1, wherein the structure is a trench and via structure formed in an interlevel dielectric material using a dual damascene process.
10. The method of claim 1, wherein the barrier layer is a Ta based material using a combination of TaN and Ta, Ru, Co or alloys thereof.
11. The method of claim 1, further comprising forming a dielectric cap over the filled structure, which forms a film of segregated alloy impurity atoms on a surface of the additional metal which is electroplated copper.
12. A method of forming an interconnect structure, comprising:
- forming a structure through an interlevel dielectric;
- forming a barrier layer on sidewalls of the structure;
- forming a copper alloy seed layer on the barrier layer;
- forming a pure copper film layer on the barrier layer;
- reflowing the pure copper film layer such that the pure copper film layer migrates into a bottom of the structure, while the copper alloy layer wets the barrier layer due to adhesion;
- filling the structure with an electroplated copper, directly on the reflowed pure copper;
- capping the structure with a dielectric material; and
- forming a layer of copper alloy on the pure copper, after the reflowing and prior to the filling in the structure.
13. The method of claim 12, wherein the copper alloy is CuAl, CuMn, CuTi or CuSn, which forms a film of impurities on a surface of the electroplated copper.
14. The method of claim 13, wherein the impurities are Al, Mn, Ti or Sn.
15. The method of claim 13, wherein the film prevents void formation.
16. The method of claim 12, wherein the barrier layer is Ta based material using any combination of TaN and Ta, Ru, Co or alloys thereof.
18. The method of claim 12, wherein the copper alloy is thicker than the layer of copper alloy.
International Classification: H01L 23/532 (20060101); H01L 21/768 (20060101);