At Least One Layer Forms A Diffusion Barrier Patents (Class 257/751)
  • Patent number: 11417819
    Abstract: An integrated circuit is provided that comprises a first substrate having a plurality of conductive contact pads spaced apart from one another on a surface of the first substrate, a dielectric layer overlying the first substrate and the plurality of conductive contact pads, and a second substrate overlying the dielectric layer. A plurality of superconducting contacts extend through the second substrate and the dielectric layer to the first substrate, wherein each superconducting contact of the plurality of superconducting contacts is aligned with and in contact with a respective conductive contact pad of the plurality of conductive contact pads.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: August 16, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Christopher A. Cantaloube
  • Patent number: 11410885
    Abstract: Methods of forming fully aligned vias connecting two metal lines extending in two directions are described. The fully aligned via is aligned with the first metal line and the second metal line along both directions. A third metal layer is patterned on a top of a second metal layer in electrical contact with a first metal layer. The patterned third metal layer is misaligned from the top of the second metal layer. The second metal layer is recessed to expose sides of the second metal layer and remove portions not aligned sides of the third metal layer.
    Type: Grant
    Filed: May 1, 2020
    Date of Patent: August 9, 2022
    Assignee: APPLIED MATERIALS, INC.
    Inventors: He Ren, Hao Jiang, Mehul Naik
  • Patent number: 11404373
    Abstract: Disclosed are standard cells and methods for fabricating standard cells used in semiconductor device design and fabrication. Aspects disclosed include a standard cell having a plurality of wide metal lines. The wide metal lines being formed from copper. The standard cell also includes a plurality of narrow metal lines. The narrow metal lines are formed from a material that has a lower resistance than copper for line widths on the order of twelve nanometers or less.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: August 2, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Junjing Bao, John Jianhong Zhu, Giridhar Nallapati
  • Patent number: 11398409
    Abstract: A method of forming a BEOL interconnect structure having improved resistance-capacitance is provided in which a via metal layer is created by a first metallization process and thereafter shrunk by a subtractive etch; these steps relax the critical dimension, ensure a via straight profile, avoid via chamfering and bowing, and maximize metal volume. Top trench metallization is then performed above the via metal layer; this step eliminates reactive ion etch lag and ensures no metallization void issues.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: July 26, 2022
    Assignee: International Business Machines Corporation
    Inventors: Yann Mignot, Yongan Xu, Hsueh-Chung Chen
  • Patent number: 11387143
    Abstract: A method includes forming a metal seed layer over a first conductive feature of a wafer, forming a patterned photo resist on the metal seed layer, forming a second conductive feature in an opening in the patterned photo resist, and heating the wafer to generate a gap between the second conductive feature and the patterned photo resist. A protection layer is plated on the second conductive feature. The method further includes removing the patterned photo resist, and etching the metal seed layer.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: July 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Da Cheng, Wen-Hsiung Lu, Chin Wei Kang, Yung-Han Chuang, Lung-Kai Mao, Yung-Sheng Lin
  • Patent number: 11380638
    Abstract: In one embodiment, a semiconductor device includes a substrate, a first interconnection provided above the substrate, and a first pad provided on the first interconnection. The device further includes a second pad provided on the first pad, and a second interconnection provided on the second pad. Furthermore, the first pad includes a first layer provided in a first insulator above the substrate, and a second layer that is provided in the first insulator via the first layer and is in contact with the first interconnection, or the second pad includes a third layer provided in a second insulator above the substrate, and a fourth layer that is provided in the second insulator via the third layer and is in contact with the second interconnection.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: July 5, 2022
    Assignee: Kioxia Corporation
    Inventor: Masayoshi Tagami
  • Patent number: 11373879
    Abstract: A planarization method and a CMP method are provided. The planarization method includes providing a substrate with a first region and a second region having different degrees of hydrophobicity or hydrophilicity and performing a surface treatment to the first region to render the degrees of hydrophobicity or hydrophilicity in proximity to that of the second region. The CMP method includes providing a substrate with a first region and a second region; providing a polishing slurry on the substrate, wherein the polishing slurry and the surface of the first region have a first contact angle, and the polishing slurry and the surface of the first region have a second contact angle; modifying the surface of the first region to make a contact angle difference between the first contact angle and the second contact angle equal to or less than 30 degrees.
    Type: Grant
    Filed: September 12, 2020
    Date of Patent: June 28, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tung-Kai Chen, Ching-Hsiang Tsai, Kao-Feng Liao, Chih-Chieh Chang, Chun-Hao Kung, Fang-I Chih, Hsin-Ying Ho, Chia-Jung Hsu, Hui-Chi Huang, Kei-Wei Chen
  • Patent number: 11362079
    Abstract: A method of forming a bonded assembly includes providing a first semiconductor die containing a first substrate, first semiconductor devices, first dielectric material layers overlying the first semiconductor devices, and first metal interconnect structures, providing a second semiconductor die containing a second substrate, second semiconductor devices, second dielectric material layers overlying the second semiconductor devices, and second metal interconnect structures, depositing a manganese layer on a top surface of the first dielectric material layers, disposing the second semiconductor die on the manganese layer such that a surface of the second dielectric material layers contacts the manganese layer, and performing a bonding anneal to bond the first semiconductor die to the second semiconductor die and to convert the manganese layer into a manganese-containing oxide layer, such that the manganese-containing oxide layer is bonded to the first dielectric material layers and the second dielectric material
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: June 14, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Chen Wu, Peter Rabkin, Masaaki Higashitani
  • Patent number: 11355512
    Abstract: A semiconductor device includes a substrate, a logic circuit provided on the substrate, a wiring layer including a plurality of wirings that are provided above the logic circuit, a first insulating film below the wiring layer, a plug, and a second insulating film. Each of the wirings contains copper and extends along a surface plane of the substrate in a first direction. The wirings are arranged along the surface plane of the substrate in a second direction different from the first direction. The plug extends through the first insulating film in a third direction crossing the first and second directions and is electrically connected to one of the wirings. The plug contains tungsten. The second insulating film is provided between the first insulating film and the plug.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: June 7, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Jun Iijima, Masayoshi Tagami, Masayuki Kitamura, Satoshi Wakatsuki
  • Patent number: 11355390
    Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip may comprise a first metal line disposed over a substrate. A via may be disposed directly over a top of the first metal line and the via may comprise a first lower surface and a second lower surface above the first lower surface. A first dielectric structure may be disposed laterally adjacent to the first metal line and may be disposed along a sidewall of the first metal line. A first protective etch-stop structure may be disposed directly over a top of the first dielectric structure and the first protective etch-stop structure may vertically separate the second lower surface of the via from the top of the first dielectric structure.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: June 7, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shao-Kuan Lee, Hai-Ching Chen, Hsin-Yen Huang, Shau-Lin Shue, Cheng-Chin Lee
  • Patent number: 11348864
    Abstract: Disclosed are redistribution substrates and semiconductor packages including the same. For example, a redistribution substrate including a dielectric pattern, and a first redistribution pattern in the dielectric pattern is provided. The first redistribution pattern may include: a first via part having a first via seed pattern and a first via conductive pattern on the first via seed pattern, and a first wiring part having a first wiring seed pattern and a first wiring conductive pattern, the first wiring part being disposed on the first via part and having a horizontal width that is different from a horizontal width of the first via part. Additionally, the first wiring seed pattern may cover a bottom surface and a sidewall surface of the first wiring conductive pattern, and the first via conductive pattern is directly connected to the first wiring conductive pattern.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: May 31, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seokhyun Lee, Gwangjae Jeon
  • Patent number: 11328993
    Abstract: An embodiment includes a metal interconnect structure, comprising: a dielectric layer disposed on a substrate; an opening in the dielectric layer, wherein the opening has sidewalls and exposes a conductive region of at least one of the substrate and an interconnect line; an adhesive layer, comprising manganese, disposed over the conductive region and on the sidewalls; and a fill material, comprising cobalt, within the opening and on a surface of the adhesion layer. Other embodiments are described herein.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: May 10, 2022
    Assignee: Intel Corporation
    Inventors: Christopher J. Jezewski, Tejaswi K. Indukuri, Ramanan V. Chebiam, Colin T. Carver
  • Patent number: 11322359
    Abstract: After forming a contact opening in a dielectric material layer located over a substrate, a metal liner layer comprising a nitride of an alloy and a metal contact layer comprising the alloy that provides the metal liner layer are deposited in-situ in the contact opening by sputter deposition in a single process and without an air break. Compositions of the metal liner layer and the metal contact layer can be changed by varying gas compositions employed in the sputtering process.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: May 3, 2022
    Assignee: ELPIS TECHNOLOGIES INC.
    Inventors: Praneet Adusumilli, Alexander Reznicek, Oscar van der Straten, Chih-Chao Yang
  • Patent number: 11315892
    Abstract: A power semiconductor device, a power semiconductor module and a power semiconductor device processing method are provided. The power semiconductor device includes a first load terminal structure, a second load terminal structure, and a semiconductor structure electrically coupled to each load terminal structure and configured to carry a load current. The first load terminal structure includes a conductive layer in contact with the semiconductor structure, a bonding block configured to be contacted by at least one bond wire and to receive at least a part of the load current from the at least one bond wire and/or the conductive layer, a support block having a hardness greater than the hardness of the conductive layer and the bonding block. The bonding block is mounted on the conductive layer via the support block, and a zone is arranged within the conductive layer and/or the bonding block, the zone exhibiting nitrogen atoms.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: April 26, 2022
    Inventors: Roman Roth, Frank Hille, Hans-Joachim Schulze
  • Patent number: 11296026
    Abstract: A semiconductor device includes a first interlayer dielectric (ILD) layer disposed over a substrate, and a first metal wiring pattern formed in the first interlayer dielectric layer and extending in a first direction parallel with the substrate. In a cross section along a second direction which crosses the first direction and is in parallel with the substrate, a top of the first metal wiring pattern is covered by a first two-dimensional material layer.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: April 5, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Han Lee, Shau-Lin Shue
  • Patent number: 11289157
    Abstract: A memory device includes: a resistive switching layer, a conductive pillar, a barrier layer, a word line, a plurality of resistive layers, and a plurality of bit lines. The resistive switching layer is shaped as a cup and has an inner surface to define an opening. The conductive pillar is disposed in the opening. The barrier layer is disposed between the resistive switching layer and the conductive pillar. The word line is electrically connected to the conductive pillar. The resistive layers are respectively distributed on an outer surface of the resistive switching layer. The bit lines are electrically connected to the resistive layers, respectively.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: March 29, 2022
    Assignee: Winbond Electronics Corp.
    Inventors: Frederick Chen, Ping-Kun Wang, Kuang-Chih Hsieh, Chien-Min Wu, Meng-Hung Lin
  • Patent number: 11276727
    Abstract: In a general aspect, a superconducting via for routing electrical signals through a substrate includes the substrate and a layer formed of superconducting material. The substrate has a first orifice disposed on a first surface and a second orifice disposed on a second surface. A cavity extends through the substrate from the first orifice to the second orifice. The layer of superconducting material includes a first portion occluding the first orifice and having an exterior surface facing outward from the substrate. The layer also includes a second portion in contact with a side wall of the cavity and extending to the second orifice. A quantum circuit element may optionally be disposed on the first surface and electrically coupled to the exterior surface of the first portion of the layer.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: March 15, 2022
    Assignee: Rigetti & Co, LLC
    Inventors: James Russell Renzas, Jayss Daniel Marshall, Cat-Vu Huu Bui, Mehrnoosh Vahidpour, William Austin O'Brien, IV, Andrew Joseph Bestwick, Chad Tyler Rigetti, Keith Matthew Jackson
  • Patent number: 11276611
    Abstract: A method for fabricating a semiconductor device including a self-aligned top via includes subtractively etching a conductive layer to form at least a first conductive line on a substrate. After the subtractive etching, the method further includes forming a barrier layer along the substate and along the first conductive line, planarizing at least portions of the barrier layer to obtain at least an exposed first conductive line, recessing at least the exposed first conductive line to form a first recessed conductive line, and forming conductive material in a via opening on the first recessed conductive line.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: March 15, 2022
    Assignee: International Business Machines Corporation
    Inventors: Brent Anderson, Lawrence A. Clevenger, Kisik Choi, Nicholas Anthony Lanzillo, Christopher J. Penny, Robert Robison
  • Patent number: 11270948
    Abstract: In an embodiment, a semiconductor wafer is provided that includes a plurality of component positions with scribe line regions located at least one of adjacent to and between the component positions. The component positions include an active device structure. An auxiliary structure is positioned in one or more of the scribe line regions. The auxiliary structure is electrically coupled to an auxiliary contact pad which includes tungsten.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: March 8, 2022
    Assignee: Infineon Technologies Austria AG
    Inventor: Oliver Blank
  • Patent number: 11270963
    Abstract: A semiconductor die includes a first pad-level dielectric layer embedding first bonding pads and located over a first substrate. Each of the first bonding pads is located within a respective pad cavity in the first pad-level dielectric layer. Each of the first bonding pads includes a first metallic liner containing a first metallic liner material and contacting a sidewall of the respective pad cavity, a first metallic fill material portion embedded in the first metallic liner, and a metallic electromigration barrier layer contacting the first metallic fill material portion and adjoined to the first metallic liner.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: March 8, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Chen Wu, Peter Rabkin, Masaaki Higashitani
  • Patent number: 11257782
    Abstract: A method of manufacturing a semiconductor device comprising embedding electrodes in insulating layers exposed to the joint surfaces of a first substrate and a second substrate, subjecting the joint surfaces of the first substrate and the second substrate to chemical mechanical polishing, to form the electrodes into recesses recessed as compared to the insulating layers, laminating insulating films of a uniform thickness over the entire joint surfaces, forming an opening by etching in at least part of the insulating films covering the electrodes of the first substrate and the second substrate, causing the corresponding electrodes to face each other and joining the joint surfaces of the first substrate and the second substrate to each other, heating the first substrate and the second substrate joined to each other, causing the electrode material to expand and project through the openings, and joining the corresponding electrodes to each other.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: February 22, 2022
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Eiichiro Kanda
  • Patent number: 11251261
    Abstract: Methods, apparatuses, and systems related to forming a barrier material on an electrode are described. An example method includes forming a top electrode of a storage node on a dielectric material in a semiconductor fabrication sequence and forming, in-situ in a semiconductor fabrication apparatus, a barrier material on the top electrode to reduce damage to the dielectric material when ex-situ of the semiconductor fabrication apparatus.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: February 15, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Sanket S Kelkar, An-Jen B. Cheng, Dojun Kim, Christopher W. Petz, Matthew N. Rocklein, Brenda D. Kraus
  • Patent number: 11251129
    Abstract: An integrated circuit structure, comprises a dielectric material having an opening therein, the opening defined by sides and a bottom. A graphene barrier material is conformal to the sides and the bottom of the opening, and a conductive metal over the graphene barrier material that fills at least a portion of a remainder of the opening in the dielectric material. The graphene barrier is formed by applying a non-hydrogen based plasma pretreatment to the dielectric surface, including the sides and the bottom of the opening, to substantially remove any passivation and provide an activated dielectric surface. A carbon-based precursor is exposed to the activated dielectric surface at less than approximately 400° C. to form the graphene barrier.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: February 15, 2022
    Assignee: Intel Corporation
    Inventors: Nita Chandrasekhar, AKM Shaestagir Chowdhury
  • Patent number: 11251126
    Abstract: Various methods and structures for fabricating BEOL metallization layer including at least one bulk cobalt contact, the at least one bulk cobalt contact including a replacement non-cobalt metal cap integral to the at least one bulk cobalt contact. The method includes performing selective deposition, by a chemical exchange reaction of metal between a non-cobalt metal and Cobalt in the at least one bulk cobalt contact, of the replacement non-cobalt metal cap integrally formed in a top surface region of the bulk cobalt contact.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: February 15, 2022
    Assignee: International Business Machines Corporation
    Inventors: James J. Kelly, Cornelius Brown Peethala
  • Patent number: 11239112
    Abstract: Passivating silicide-based approaches for conductive via fabrication is described. In an example, an integrated circuit structure includes a plurality of conductive lines in an inter-layer dielectric (ILD) layer above a substrate. Each of the plurality of conductive lines is recessed relative to an uppermost surface of the ILD layer. A metal silicide layer is on the plurality of conductive lines, in recess regions above each of the plurality of conductive lines. A hardmask layer is on the metal silicide layer and on the uppermost surface of the ILD layer. A conductive via is in an opening in the hardmask layer and on a portion of the metal silicide layer on one of the plurality of conductive lines.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: February 1, 2022
    Assignee: Intel Corporation
    Inventors: Manish Chandhok, Sudipto Naskar, Richard E. Schenker
  • Patent number: 11233020
    Abstract: A semiconductor package device includes: (1) a die having an active surface, a back surface opposite to the active surface and a lateral surface extending between the active surface and the back surface; (2) a first conductive pillar disposed on the active surface of the die and electrically connected to the die, the first conductive pillar having a top surface facing away from the die and a lateral surface substantially perpendicular to the top surface of the first conductive pillar; (3) a dielectric layer disposed on the active surface of the die and fully covering the lateral surface of the first conductive pillar; and (4) a package body encapsulating the back surface and the lateral surface of the die.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: January 25, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Chung-Hsuan Tsai
  • Patent number: 11222815
    Abstract: A semiconductor interconnect structure having a first electrically conductive structure having a plurality of bottom portions; a dielectric capping layer, at least a portion of the dielectric capping layer being in contact with a first bottom portion of the plurality of bottom portions; and a second electrically conductive structure in electrical contact with a second bottom portion of the plurality of bottom portions. A method of forming the interconnect structure is also provided.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: January 11, 2022
    Assignee: Tessera, Inc.
    Inventors: Conal E. Murray, Chih-Chao Yang
  • Patent number: 11211289
    Abstract: The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: December 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Chieh Wu, Tang-Kuei Chang, Kuo-Hsiu Wei, Kei-Wei Chen, Ying-Lang Wang, Su-Hao Liu, Kuo-Ju Chen, Liang-Yin Chen, Huicheng Chang, Ting-Kui Chang, Chia Hsuan Lee
  • Patent number: 11205592
    Abstract: A back end of line interconnect structure and methods for forming the interconnect structure including a self-aligned via generally includes a subtractive etch process to define the vias. The vias include a via core and a liner to provide a critical dimension equal to a critical dimension of an underlying metal line. The metal lines are free of the liner. The method provides some via metal liner material on top of metal lines that do not includes a via in direct contact therewith.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: December 21, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruilong Xie, Cheng Chi, Chih-Chao Yang, Kangguo Cheng
  • Patent number: 11205652
    Abstract: A semicondcutor memory device may include a substrate, a bit line structure extending in one direction on the substrate, the bit line structure including a sidewall, a storage node contact on the sidewall of the bit line structure, first and second spacers between the sidewall of the bit line structure and the storage node contact, the first spacer separated from the second spacer by a space between the first spacer and the second spacer, an interlayer dielectric layer on the bit line structure, the interlayer dielectric layer including a bottom surface, a spacer capping pattern extending downward from the bottom surface of the interlayer dielectric layer toward the space between the first and second spacers, and a landing pad structure penetrating the interlayer dielectric layer, the landing pad structure coupled to the storage node contact.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: December 21, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dongjun Lee, Sang Chul Shin, Bong-Soo Kim, Jiyoung Kim
  • Patent number: 11201242
    Abstract: A semiconductor structure is provided that includes non-metal semiconductor alloy containing contact structures for field effect transistors (FETs), particularly p-type FETs. Notably, each non-metal semiconductor alloy containing contact structure includes a highly doped epitaxial semiconductor material directly contacting a topmost surface of a source/drain region of the FET, a titanium liner located on the highly doped epitaxial semiconductor material, a diffusion barrier liner located on the titanium liner, and a contact metal portion located on the diffusion barrier liner.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: December 14, 2021
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Keith E. Fogel, Nicole S. Munro, Alexander Reznicek
  • Patent number: 11195815
    Abstract: A method of manufacturing a semiconductor device which includes a plurality of members including a semiconductor element is provided. The method may include disposing one surface of a first member which is one of the plurality of members and one surface of a second member which is another one of the plurality of members opposite to each other with a tin-based (Sn-based) solder material interposed therebetween, and bonding the first member and the second member by melting and solidifying the Sn-based solder material. At least the one surface of the first member may be constituted of a nickel-based (Ni-based) metal, and at least the one surface of the second member may be constituted of copper (Cu).
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: December 7, 2021
    Assignee: DENSO CORPORATION
    Inventor: Takuya Kadoguchi
  • Patent number: 11189524
    Abstract: A semiconductor arrangement is provided. The semiconductor arrangement includes a first dielectric layer over a substrate, a metal layer over the first dielectric layer, a first conductive structure passing through the metal layer and the first dielectric layer, a second conductive structure passing through the metal layer and the first dielectric layer, and a third conductive structure coupling the first conductive structure to the second conductive structure, and overlying a first portion of the metal layer between the first conductive structure and the second conductive structure, wherein an interface exists between the metal layer and at least one of the first conductive structure or the second conductive structure.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: November 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Hsi-Wen Tien, Wei-Hao Liao, Pin-Ren Dai, Chih Wei Lu, Chung-Ju Lee
  • Patent number: 11177231
    Abstract: Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first and second semiconductor structures. The first semiconductor structure includes a substrate, a first device layer disposed on the substrate, and a first bonding layer disposed above the first device layer and including a first bonding contact. The second semiconductor structure includes a second device layer, and a second bonding layer disposed below the second device layer and including a second bonding contact. The first bonding contact is in contact with the second bonding contact at the bonding interface. At least one of the first bonding contact and the second bonding contact includes a capping layer at the bonding interface and having a conductive material different from a remainder of the respective first or second bonding contact.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: November 16, 2021
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Jie Pan, Shu Liang Lv, Liang Ma, Yuan Li, Si Ping Hu, Xianjin Wan
  • Patent number: 11177232
    Abstract: Techniques and mechanisms for bonding structures of a circuit device with a monolayer. In an embodiment, a patterned metallization layer or a first dielectric layer includes a first surface portion. The first surface portion is exposed to first molecules which each include a first head group and a first end group which is substantially non-reactive with the first head group. The first head groups attach to the first portion to form a first self-assembled monolayer, which is subsequently reacted with second molecules to form a second monolayer comprising moieties of the first molecules. In another embodiment, the first head group comprises a first moiety comprising a sulfur atom or a nitrogen atom, where the first end group comprises one of an acid moiety, an acid anhydride moiety, an aliphatic alcohol moiety, an aromatic alcohol moiety, or an unsaturated hydrocarbon moiety.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: November 16, 2021
    Assignee: Intel Corporation
    Inventors: Suddhasattwa Nad, Rahul N. Manepalli, Marcel A. Wall
  • Patent number: 11171097
    Abstract: A bonded assembly includes a first semiconductor die containing a first substrate, first semiconductor devices, and first bonding pads that are electrically connected to a respective node of the first semiconductor devices, a second semiconductor die containing a second substrate, second semiconductor devices, and second bonding pads that are electrically connected to a respective node of the second semiconductor devices and bonded to a respective one of the first bonding pads, and at least one metal-organic framework (MOF) dielectric layer that laterally surrounds at least one of the first bonding pads and the second bonding pads.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: November 9, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Ramy Nashed Bassely Said, Raghuveer S. Makala, Senaka Kanakamedala, Fei Zhou, Yao-Sheng Lee
  • Patent number: 11158511
    Abstract: A semiconductor device that includes a semiconductor layer disposed on a semiconductor substrate, a first semiconductor region provided in an upper layer portion of the semiconductor layer, a second semiconductor region provided in an upper layer portion of the first semiconductor region, a gate insulation film, a gate electrode, a first main electrode that is provided on an interlayer insulation film that covers the gate electrode and that is electrically connected to the second semiconductor region via a contact hole, and a second main electrode disposed on a second main surface of the semiconductor substrate. The first main electrode includes an underlying electrode film connected to the second semiconductor region via the contact hole, and a copper film provided on the underlying electrode film. The copper film includes at least a portion that serves as a stress relaxation layer having a smaller grain size than the other portion of the copper film.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: October 26, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Kazuyuki Sugahara, Hiroaki Okabe, Motoru Yoshida
  • Patent number: 11158659
    Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes an interconnect structure formed over a substrate and a passivation layer formed over the interconnect structure. The semiconductor device structure also includes an anti-acid layer formed in the passivation layer and a bonding layer formed on the anti-acid layer and the passivation layer. The anti-acid layer has a thickness that is greater than about 140 nm.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: October 26, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yin-Shuo Chu, Chi-Chung Yu, Li-Yen Fang, Tain-Shang Chang, Yao-Hsiang Liang, Min-Chih Tsai
  • Patent number: 11133609
    Abstract: A semiconductor device includes: an insulation circuit substrate including a metal layer and an insulation substrate, the metal layer being formed on one surface of the insulation substrate, a connecting member having a cylindrical shape joined to the metal layer via a bonding material, a terminal pin inserted in the connecting member, and a reinforcement member having a cylindrical shape disposed on an outer periphery of the connecting member. The reinforcement member is made of a material having a hardness greater than that of the connecting member.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: September 28, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yuichiro Hinata, Tatsuo Nishizawa
  • Patent number: 11133461
    Abstract: Devices and systems having a diffusion barrier for limiting diffusion of a phase change material including an electrode, a phase change material electrically coupled to the electrode, and a carbon and TiN (C:TiN) diffusion barrier disposed between the electrode and the phase change material to limit diffusion of the phase change material are disclosed and described.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: September 28, 2021
    Assignee: Intel Corporation
    Inventors: Christopher Petz, Dale Collins, Tsz-Wah Chan, Swapnil Lengade, Yongjun Hu, Allen McTeer
  • Patent number: 11127826
    Abstract: A semiconductor device may include a semiconductor substrate, an upper electrode provided on an upper surface of the semiconductor substrate, a lower electrode provided on a lower surface of the semiconductor substrate, and a terminal connected to the upper electrode. The semiconductor substrate may include an active region in which switching elements are provided. The switching elements may be configured to pass a current between the upper electrode and the lower electrode. The active region may include a main region located under the terminal and an external region located outside the main region. The external region may include a low current region. A current density in the low current region may be lower than a current density in the main region in a case where the switching elements in the low current region and the main region are turned on.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: September 21, 2021
    Assignee: DENSO CORPORATION
    Inventors: Masayuki Kamiya, Takanori Kawashima
  • Patent number: 11114433
    Abstract: Provided is a three dimensional integrated circuit (3DIC) structure including a first die, a second die, and a hybrid bonding structure bonding the first die and the second die. The hybrid bonding structure includes a first bonding structure and a second bonding structure. The first bonding structure includes a first bonding dielectric layer and a first bonding metal layer. The first bonding metal layer is disposed in the first bonding dielectric layer. The first bonding metal layer includes a first via plug and a first metal feature disposed over the first via plug, wherein a height of the first metal feature is greater than or equal to a height of the first via plug. A method of fabricating the 3DIC structure is also provided.
    Type: Grant
    Filed: July 15, 2018
    Date of Patent: September 7, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Ming-Fa Chen
  • Patent number: 11114462
    Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and a memory stack structure extending through the alternating stack. The memory stack structure includes a composite charge storage structure, a tunneling dielectric layer, and a vertical semiconductor channel. The composite charge storage structure may include a vertical stack of tubular charge storage material portions including a first charge trapping material located at levels of the electrically conductive layers, and a charge storage layer including a second charge trapping material extending through a plurality of electrically conductive layers of the electrically conductive layers. The first charge trapping material has a higher charge trap density than the second charge trapping material. Alternatively, the composite charge storage material portions may include discrete charge storage elements each containing a silicon nitride portion and a silicon carbide nitride liner.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: September 7, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Zhixin Cui, Ippei Yasuda
  • Patent number: 11101130
    Abstract: A method of forming a pattern of metallic material on a substrate includes providing a plurality of void regions on a surface of the substrate. At a first temperature, a first layer of a first metallic material of a eutectic-forming pair of metallic materials is deposited on the substrate to form a conformal metallic film over the substrate and over the surfaces of the plurality of void regions. The substrate and conformal metallic film are warmed to a second temperature greater than a eutectic-liquid-formation temperature of the eutectic pair of metallic materials. At the second temperature, the second metallic material of the eutectic-forming pair of metallic materials is deposited on the conformal metallic film to initiate a eutectic-liquid-forming reaction, such that the plurality of void regions are filled with a mixture of the first and second metallic materials of the eutectic-forming pair of metallic materials.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: August 24, 2021
    Assignee: RAYTHEON COMPANY
    Inventors: Andrew Clarke, Robert M. Emerson, George Grama, June-Marie Boll
  • Patent number: 11094626
    Abstract: A method of fabricating a semiconductor interconnect structure includes forming a via in a dielectric layer, depositing a ruthenium-containing conductive layer over a top surface of the via and a top surface of the dielectric layer, and patterning the ruthenium-containing conductive layer to form a conductive line over the top surface of the via, where a thickness of the conductive line is less than a thickness of the via.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: August 17, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Han Lee, Shau-Lin Shue
  • Patent number: 11081352
    Abstract: In some embodiments, a method for forming an integrated circuit is provided. The method includes forming a first layer over a semiconductor wafer, the first layer having a first portion and a second portion. The first portion is patterned by projecting a first image field over the first portion of the first layer, where the first portion of the first layer corresponds to the first image field. The second portion is patterned by projecting a second image field over the second portion of the first layer, where the second portion of the first layer corresponds to the second image field. A second layer is formed over the first layer. The second layer is patterned by projecting a third image field over the second layer, where the third image field covers a majority of the first portion and a majority of the second portion of the first layer.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: August 3, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Chen Lu, Ming-Chang Hsieh, Yi-Min Chen
  • Patent number: 11075501
    Abstract: A process for producing a component includes a structure made of III-V material(s) on the surface of a substrate, the structure comprising at least one upper contact level defined on the surface of a first III-V material and a lower contact level defined on the surface of a second III-V material, comprising: successive operations of encapsulation of the structure with at least one dielectric; making primary apertures in a dielectric for the two contacts; making secondary apertures in a dielectric for the two contacts; at least partial filling of the apertures with at least one metallic material so as to produce upper contact bottom metallization and at least one upper contact pad in contact with the metallization for each of said contacts. A component produced by the process is also provided. The component may be a laser diode.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: July 27, 2021
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Elodie Ghegin, Christophe Jany, Fabrice Nemouchi, Philippe Rodriguez, Bertrand Szelag
  • Patent number: 11069619
    Abstract: An interconnect structure and an electronic device including the interconnect structure are disclosed. The interconnect structure may include a metal interconnect having a bottom surface and two opposite side surfaces surrounded by a dielectric layer, a graphene layer on the metal interconnect, and a metal bonding layer providing interface adhesion between the metal interconnect and the graphene layer. The metal bonding layer includes a metal material.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: July 20, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seunggeol Nam, Hyeonjin Shin, Keunwook Shin, Changhyun Kim, Kyung-Eun Byun, Hyunjae Song, Eunkyu Lee, Changseok Lee, Alum Jung, Yeonchoo Cho
  • Patent number: 11062943
    Abstract: A method includes patterning an interconnect trench in a dielectric layer. The interconnect trench has sidewalk and a bottom surface. A liner layer is deposited on the sidewalls and the bottom surface of the interconnect trench. The interconnect trench is filled with a first conductive metal material. The conducting metal material is recessed to below a top surface of the dielectric layer. A cap layer is deposited on a top surface of the first conductive metal material. The cap layer and the liner layer are of the same material. The method further includes forming a via on a portion of the interconnect trench.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: July 13, 2021
    Assignee: International Business Machines Corporation
    Inventors: Koichi Motoyama, Nicholas Anthony Lanzillo, Christopher J. Penny, Somnath Ghosh, Robert Robison, Lawrence A. Clevenger
  • Patent number: 11063005
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first conductive interconnect wire extending in a first direction over a substrate. A second conductive interconnect wire is arranged over the first conductive interconnect wire. A via rail is configured to electrically couple the first conductive interconnect wire and the second conductive interconnect wire. The first conductive interconnect wire and the second conductive interconnect wire extend as continuous structures past one or more sides of the via rail.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: July 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kam-Tou Sio, Chih-Ming Lai, Chun-Kuang Chen, Chih-Liang Chen, Charles Chew-Yuen Young, Chi-Yeh Yu, Jiann-Tyng Tzeng, Ru-Gun Liu, Wen-Hao Chen