At Least One Layer Forms A Diffusion Barrier Patents (Class 257/751)
  • Patent number: 10283448
    Abstract: A method of fabricating a semiconductor device includes providing a first substrate comprising a first conductive element exposed at a surface of the first substrate; forming a patterned photoresist layer atop the first conductive element, whereby the patterned photoresist layer provides openings exposing the first conductive element; forming a first metal layer in the openings and directly atop the first conductive element; forming a first insulator layer over the first metal layer and the first substrate; and polishing the first metal layer and the first insulator layer, resulting in a first interface surface over the first substrate wherein the first interface surface includes part of the first metal layer and the first insulator layer.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: May 7, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ping-Yin Liu, Kai-Wen Cheng, Xin-Hua Huang, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
  • Patent number: 10276634
    Abstract: A semiconductor memory structure is provided. The semiconductor memory structure includes a bottom electrode formed over a substrate and a magnetic tunneling junction (MTJ) cell formed over the bottom electrode. The semiconductor memory structure includes a top electrode formed over the MTJ cell and a passivation layer surrounding the top electrode. The passivation layer has a recessed portion that is lower than a top surface of the top electrode. The semiconductor memory structure further includes a cap layer formed on the top electrode and the passivation layer, wherein the cap layer is formed in the recessed portion.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Wei Lin, Yuan-Tai Tseng, Shih-Chang Liu
  • Patent number: 10276397
    Abstract: The present disclosure relates to an improved method of forming interconnection layers to reduce voids and improve reliability, and an associated device. In some embodiments, a dielectric layer is formed over a semiconductor substrate having an opening arranged within the dielectric layer. A metal seed layer is formed on the surfaces of the opening using a chemical vapor deposition (CVD) process. Then a metal layer is plated onto the metal seed layer to fill the opening. Forming the metal seed layer using a CVD process provides the seed layer with a good uniformity, which allows for high aspect ratio openings in the dielectric layer to be filled without voids or pinch off.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ya-Ling Lee, Lin-Jung Wu, Victor Y. Lu
  • Patent number: 10276530
    Abstract: A semiconductor device includes: a conductive structure, a conductive bump extending into the conductive structure and contacting the conductive structure along a first surface, the conductive bump configured to interface with an external semiconductor device at a second surface opposite the first surface, the conductive bump being wider along the first surface than the second surface.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hsiang Tsai, Hsin-Hung Chen, Chia-Ping Lai
  • Patent number: 10276432
    Abstract: An embodiment contact plug includes a bilayer structure and a diffusion barrier layer on a sidewall and a bottom surface of the bilayer structure. The bilayer structure includes a conductive core and a conductive liner on a sidewall and a bottom surface of the conductive core. In the embodiment contact plug, the conductive liner comprises cobalt or ruthenium.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Lin, Sheng-Hsuan Lin, Chih-Wei Chang, You-Hua Chou, Chia-Lin Hsu
  • Patent number: 10269629
    Abstract: A semiconductor device and a method of manufacturing the same, the semiconductor device including a substrate; an insulating layer on the substrate, the insulating layer including a first trench and a second trench therein, the second trench having an aspect ratio that is smaller than an aspect ratio of the first trench; a barrier layer in the first trench and the second trench; a seed layer on the barrier layer in the first trench and the second trench; a first bulk layer on the seed layer and filled in the first trench; and a second bulk layer on the seed layer and filled in the second trench, wherein an average grain size of the second bulk layer is larger than an average grain size of the first bulk layer.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: April 23, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Junghun Choi, Jeong Ik Kim, Myung Yang, Chul Sung Kim, Sang Jin Hyun
  • Patent number: 10269683
    Abstract: A semiconductor device according to an embodiment includes a semiconductor layer having a first plane and a second plane, an insulating layer provided in the first plane side of the semiconductor layer, a metal layer provided on or above the insulating layer, and a through electrode penetrating through the semiconductor layer and in contact with the metal layer. When a width of the through electrode in the first plane is a first width, a width of the through electrode in an intermediate plane between the first plane and the second plane is a second width, and a width of the metal layer is a third width, a first difference between the second width and the first width is larger than a second difference between the third width and the first width.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: April 23, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Masayuki Akou
  • Patent number: 10269697
    Abstract: A semiconductor device includes a plurality of lower conductive lines overlying a substrate and extending in a first direction, an insulating layer overlying the plurality of lower conductive lines, a plurality of upper conductive lines overlying the insulating layer and the first conductive lines and extending in a second direction crossing the first direction, and a plurality of vias filled with a conductive material formed in the insulating layer. The plurality of upper conductive lines are arranged in the first direction with a first pitch. The plurality of vias includes first vias and second vias. At least one via of the first vias connects at least two lines of the plurality of lower conductive lines and one line of the plurality of upper conductive lines. An average width in the first direction of the first vias is different from an average width in the first direction of the second vias.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Yen Liu, Boo Yeh, Min-Chang Liang, Jui-Yao Lai, Sai-Hooi Yeong, Ying-Yan Chen, Yen-Ming Chen
  • Patent number: 10262896
    Abstract: A use of an amine-containing silane for forming a transition metal nitride is provided. In this use, the amine of the amine-containing silane is the source of at least some, preferably most and most preferably all of the nitrogen present in the transition metal nitride.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: April 16, 2019
    Assignee: IMEC VZW
    Inventor: Silvia Armini
  • Patent number: 10256191
    Abstract: A semiconductor device is provided and includes first and second dielectrics, first and second conductive elements, a self-formed-barrier (SFB) and a liner. The first and second dielectrics are disposed with one of first-over-second dielectric layering and second-over-first dielectric layering. The first and second conductive elements are respectively suspended at least partially within a lower one of the first and second dielectrics and at least partially within the other one of the first and second dielectrics. The self-formed-barrier (SFB) is formed about a portion of one of the first and second conductive elements which is suspended in the second dielectric. The liner is deposited about a portion of the other one of the first and second conductive elements which is partially suspended in the first dielectric.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: April 9, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Nicholas A. Lanzillo, Takeshi Nogami, Christopher J. Penny, Michael Rizzolo
  • Patent number: 10256185
    Abstract: A method for fabricating a semiconductor structure includes the following steps. A substrate including a dielectric material is formed. A surface of the substrate is molecularly modified to convert the surface of the substrate to a nitrogen-enriched surface. A metal layer is deposited on the molecularly modified surface of the substrate interacting with the molecularly modified surface to form a nitridized metal layer.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: April 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Lawrence A. Clevenger, Roger A. Quon, Hosadurga K. Shobha, Terry A. Spooner, Wei Wang, Chih-Chao Yang
  • Patent number: 10249534
    Abstract: The present disclosure provides a contact element of a semiconductor device structure, wherein an opening is formed in an insulating material layer, the insulating material layer being provided over a semiconductor substrate. Within a lower portion of the opening, a contact liner portion is formed, the contact liner portion covering a bottom of the opening and partially covering a lower sidewall portion of the lower portion of the opening such that an upper sidewall portion at an upper portion of the opening is exposed to further processing. An insulating liner portion is formed within the opening, the insulating liner portion covering the exposed upper sidewall portion. Furthermore, a contact liner is formed within the opening, the contact liner covering the contact liner portion in the insulating liner portion, and the opening is filled with a conductive material.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: April 2, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Jim Shih-Chun Liang
  • Patent number: 10236206
    Abstract: Structures for interconnects and methods for forming interconnects. A dual-damascene opening is formed in a dielectric layer and a first liner is formed on the dielectric layer at one or more sidewalls of the dual-damascene opening. A first conductor layer is formed in a portion of the dual-damascene opening. The first liner is removed from the one or more sidewalls of the dual-damascene opening vertically between the first conductor layer and a top surface of the dielectric layer. After the first liner is removed, a second liner is formed on the dielectric layer at the one or more sidewalls of the dual-damascene opening between the first conductor layer and the top surface of the dielectric layer. A second conductor layer is formed in the dual-damascene opening between the first conductor layer and the top surface of the dielectric layer. The first and second liner materials differ in composition.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: March 19, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Robert J. Fox, III
  • Patent number: 10229851
    Abstract: An etch back air gap (EBAG) process is provided. The EBAG process includes forming an initial structure that includes a dielectric layer disposed on a substrate and a liner disposed to line a trench defined in the dielectric layer. The process further includes impregnating a metallic interconnect material with dopant materials, filling a remainder of the trench with the impregnated metallic interconnect materials to form an intermediate structure and drive-out annealing of the intermediate structure. The drive-out annealing of the intermediate structure serves to drive the dopant materials out of the impregnated metallic interconnect materials and thereby forms a chemical- and plasma-attack immune material.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: March 12, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin D. Briggs, Elbert Huang, Takeshi Nogami, Christopher J. Penny
  • Patent number: 10229875
    Abstract: A back end of the line (BEOL) fuse structure having a stack of vias. The stacking of vias leads to high aspect ratios making liner and seed coverage inside the vias poorer. The weakness of the liner and seed layers leads to a higher probability of electromigration (EM) failure. The fuse structure addresses failures due to poor liner and seed coverage. Design features permit determining where failures occur, determining the extent of the damaged region after fuse programming and preventing further propagation of the damaged dielectric region.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: March 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Griselda Bonilla, Kaushik Chanda, Ronald G. Filippi, Stephan Grunow, Naftali E. Lustig, Andrew H. Simon, Ping-Chuan Wang
  • Patent number: 10229968
    Abstract: A method for fabricating an advanced metal insulator metal capacitor structure includes providing a pattern in a dielectric layer. The pattern includes a set of features in the dielectric layer. A first metal layer is deposited in the set of features in the dielectric layer. A phase change material layer is deposited over the metal layer in the set of features in the dielectric layer. The phase change material is an insulator in a deposited state. A surface treatment process is performed on the phase change layer to produce a top surface layer having electrically conductive properties. A second metal layer is deposited on the top surface layer of the phase change layer.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: March 12, 2019
    Assignee: International Business Machines Corporation
    Inventor: Chih-Chao Yang
  • Patent number: 10224259
    Abstract: The resin composition for sealing semiconductor according to the present invention is characterized by containing a maleimide-based compound represented by the following general formula (1), at least one of the benzoxazine-based compounds represented by the following general formula (2-1) and the following general formula (2-2), a curing catalyst, and an inorganic filler. In the general formulae (1), (2-1) and (2-2), each of X2, X3 and X4 independently represents an alkylene group having 1 to 10 carbon atoms, a group represented by the following general formula (3), a group represented by the formula “—SO2—” or “—CO—”, an oxygen atom or a single bond.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: March 5, 2019
    Assignee: SUMITOMO BAKELITE CO., LTD.
    Inventors: Yui Ozaki, Katsushi Yamashita, Tomomasa Kashino
  • Patent number: 10224204
    Abstract: An integrated circuit device is manufactured by a method including forming a stacked mask structure including a carbon-containing film and a silicon-containing organic anti-reflective film is on a substrate, forming a silicon-containing organic anti-reflective pattern by etching the silicon-containing organic anti-reflective film, and forming a composite mask pattern including a carbon-containing mask pattern and a profile control liner lining interior surfaces of the carbon-containing mask pattern by etching the carbon-containing film while using the silicon-containing organic anti-reflective pattern as an etch mask. Ions are implanted into the substrate through a plurality of spaces defined by the composite mask pattern.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: March 5, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Hoon Khang, Dong-Woo Kang, Moon-Han Park, Ji-Ho Yoo, Chong-Kwang Chang
  • Patent number: 10224241
    Abstract: Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: March 5, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Daniel C. Edelstein, Son V. Nguyen, Takeshi Nogami, Deepika Priyadarshini, Hosadurga K. Shobha
  • Patent number: 10217663
    Abstract: A system includes a deposition chamber comprising first, second, and third stations, a delivery system providing a substrate to the deposition chamber, a processing system processing the substrate, a controller controlling the delivery system and the processing system, and an etch chamber. The delivery system provides the substrate to the first station, where the processing system performs a nucleation process on the substrate to form a metal nucleation layer, the substrate is then provided by the delivery system to the second station, where the processing system performs a first deposition process at a first temperature to form a first metal layer, the delivery system provides the substrate including the first metal layer metal to the etch chamber, where the first metal layer is etched back using a first gas. The substrate is provided back to the first station, wherein it undergoes a cleaning process using a second gas.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: February 26, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Jian Hua Xu
  • Patent number: 10211148
    Abstract: A structure comprising a first dielectric layer embedded with a first interconnect structure; an insulator layer disposed on the first dielectric layer; a second dielectric layer disposed on the insulator layer; a via residing within the second dielectric layer; and a second interconnect structure isolated from the first dielectric layer. Further, a diffusion barrier layer is configured to isolate the first interconnect structure from the first dielectric layer and the insulator layer. Further, a first portion of a bottom surface of the via resides on a top surface of the insulator layer, a second portion of the bottom surface of the via resides on a first portion of a top surface of the first interconnect structure. Moreover, a capping layer residing on a second portion of the top surface of the first interconnect structure and a first portion of a bottom surface of the second dielectric layer.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: February 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Daniel C. Edelstein, Chih-Chao Yang
  • Patent number: 10211098
    Abstract: Techniques are disclosed for providing a decoupled via fill. Given a via trench, a first barrier layer is conformally deposited onto the bottom and sidewalls of the trench. A first metal fill is blanket deposited into the trench. The non-selective deposition is subsequently recessed so that only a portion of the trench is filled with the first metal. The previously deposited first barrier layer is removed along with the first metal, thereby re-exposing the upper sidewalls of the trench. A second barrier layer is conformally deposited onto the top of the first metal and the now re-exposed trench sidewalls. A second metal fill is blanket deposited into the remaining trench. Planarization and/or etching can be carried out as needed for subsequent processing. Thus, a methodology for filling high aspect ratio vias using a dual metal process is provided. Note, however, the first and second fill metals may be the same.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: February 19, 2019
    Assignee: Intel Corporation
    Inventors: Yuriy V. Shusterman, Flavio Griggio, Tejaswi K. Indukuri, Ruth A. Brain
  • Patent number: 10204828
    Abstract: A method for forming a semiconductor structure using first and second conductive materials, and having first and second trenches with first and second critical dimensions. The second conductive material exhibits a lower resistivity than the first conductive material at a film thickness corresponding to the second critical dimension and the second conductive material exhibits a higher resistivity than the first conductive material at a film thickness corresponding to the first critical dimension. An initial semiconductor structure has the first trench having the first critical dimension and the second trench having the second critical dimension. The second critical dimension is larger than the first critical dimension. A first conductive structure made from one of the first and second conductive materials is formed in the first trench. A second conductive structure made from another of the first and second conductive materials is formed in the second trench.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: February 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Ruqiang Bao, Benjamin D. Briggs, Lawrence A. Clevenger, Koichi Motoyama, Cornelius Brown Peethala, Michael Rizzolo, Gen Tsutsui
  • Patent number: 10199451
    Abstract: A lower electrode is made of a TiN-based material and provided at a base of a dielectric film in a DRAM capacitor. The lower electrode includes first TiON films provided at opposite outer sides, the first TiON films having a relatively low oxygen concentration, and a second TiON film provided between the first TiON films, the second TiON film having a relatively high oxygen concentration.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: February 5, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Tadahiro Ishizaka, Masaki Koizumi, Masaki Sano, Seokhyoung Hong
  • Patent number: 10199234
    Abstract: A method of forming a metal silicide can include depositing an interface layer on exposed silicon regions of a substrate, where the interface layer includes a silicide forming metal and a non-silicide forming element. The method can include depositing a metal oxide layer over the interface layer, where the metal oxide layer includes a second silicide forming metal. The substrate can be subsequently heated to form the metal silicide beneath the interface layer, using silicon from the exposed silicon regions, the first silicide forming metal of the interface layer and the second silicide forming metal of the metal oxide layer.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: February 5, 2019
    Assignee: ASM IP Holding B.V.
    Inventor: Jacob Huffman Woodruff
  • Patent number: 10192829
    Abstract: Low-temperature techniques for doping of Cu interconnects based on interfacially-assisted thermal diffusion are provided. In one aspect, a method of forming doped copper interconnects includes the steps of: patterning at least one trench in a dielectric material; forming a barrier layer lining the trench; forming a metal liner on the barrier layer; depositing a seed layer on the metal liner; plating a Cu fill into the trench to form Cu interconnects; removing a portion of a Cu overburden to access an interface between the metal liner and the Cu fill; depositing a dopant layer; and diffusing a dopant(s) from the dopant layer along the interface to form a Cu interconnect doping layer between the metal liner and the Cu fill. Alternatively, the overburden and the barrier layer/metal liner can be completely removed, and the dopant layer deposited selectively on the Cu fill. An interconnect structure is also provided.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: January 29, 2019
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Chao-Kun Hu, Takeshi Nogami, Deepika Priyadarshini, Michael Rizzolo
  • Patent number: 10192755
    Abstract: The present invention makes it possible to improve the reliability of a semiconductor device. The semiconductor device has, over a semiconductor substrate, a pad electrode formed at the uppermost layer of a plurality of wiring layers, a surface protective film having an opening over the pad electrode, a redistribution line being formed over the surface protective film and having an upper surface and a side surface, a sidewall barrier film comprising an insulating film covering the side surface and exposing the upper surface of the redistribution line, and a cap metallic film covering the upper surface of the redistribution line. Then the upper surface and side surface of the redistribution line are covered with the cap metallic film or the sidewall barrier film and the cap metallic film and the sidewall barrier film have an overlapping section.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: January 29, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Masahiro Matsumoto, Kazuyoshi Maekawa, Yuichi Kawano
  • Patent number: 10192775
    Abstract: Methods for seam-less gapfill comprising sequentially depositing a film with a seam, reducing the height of the film to remove the seam and repeating until a seam-less film is formed. Some embodiments include optional film doping and film treatment (e.g., ion implantation and annealing).
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: January 29, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Pramit Manna, Ludovic Godet, Rui Cheng, Erica Chen, Ziqing Duan, Abhijit Basu Mallick, Srinivas Gandikota
  • Patent number: 10181441
    Abstract: A through via structure includes a conductive wiring, at least one dielectric layer over the conductive wiring, a via hole in the at least one dielectric layer and exposing the conductive wiring, and a conductive via in the via hole. The conductive via includes a conductive barrier layer in a bottom portion of the via hole, and a conductive layer in a top portion of the via hole.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: January 15, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Cheng-Tai Hsiao, Hsun-Chung Kuang
  • Patent number: 10170424
    Abstract: A method for fabricating an advanced metal conductor structure is described. A pattern in a dielectric layer is provided. The pattern includes a set of features in the dielectric for a set of metal conductor structures. An adhesion promoting layer is created over the patterned dielectric. A ruthenium layer is deposited over the adhesion promoting layer. Using a physical vapor deposition process, a cobalt layer is deposited over the ruthenium layer. A thermal anneal is performed which reflows the cobalt layer to fill the set of features to form a set of metal conductor structures.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Daniel C Edelstein, Chih-Chao Yang
  • Patent number: 10170419
    Abstract: At least one opening having a biconvex shape is formed into a dielectric material layer. A void-free metallization region (interconnect metallic region and/or metallic contact region) is provided to each of the openings. The void-free metallization region has the biconvex shape and exhibits a low wire resistance.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Alexander Reznicek, Oscar van der Straten
  • Patent number: 10163644
    Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a conductive plug over a substrate; a conductive feature over the conductive plug, wherein the conductive feature has a first sidewall, a second sidewall facing the first sidewall, and a bottom surface; and a carbon-containing barrier layer having a first portion along the first sidewall of the conductive feature, a second portion along the second sidewall of the conductive feature, and a third portion along the bottom surface of the conductive feature.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Rueijer Lin, Ya-Lien Lee, Chun-Chieh Lin, Hung-Wen Su
  • Patent number: 10163793
    Abstract: An integrated circuit device has a substrate including a dielectric layer patterned with a pattern which includes a set of features in the dielectric for a set of metal conductor structures. An adhesion promoting layer is disposed on the set of features in the patterned dielectric. A ruthenium layer is disposed on the adhesion promoting layer. A cobalt layer is disposed on the ruthenium layer filling a first portion of the set of features. The cobalt layer has a u-shaped cross section having a thicker bottom layer than side layers. The cobalt layer is formed using a physical vapor deposition process. A metal layer is disposed on the cobalt layer filling a second, remainder portion of the set of features.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: December 25, 2018
    Assignee: International Business Machines Corporation
    Inventors: Daniel C Edelstein, Chih-Chao Yang
  • Patent number: 10163695
    Abstract: A method is provided, including the following operations: performing a deposition process on a substrate, the deposition process configured to deposit a copper layer in a feature on the substrate, the copper layer being doped with zinc at an atomic percentage less than approximately 30 percent; after depositing the copper layer, annealing the substrate, wherein the annealing is configured to cause migration of the zinc to an interface of the copper layer and an oxide layer of the substrate, the migration of the zinc producing an adhesive barrier at the interface that inhibits electromigration of the copper layer.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: December 25, 2018
    Assignee: Lam Research Corporation
    Inventors: Aniruddha Joi, Yezdi Dordi
  • Patent number: 10163697
    Abstract: Disclosed is a method of forming back end of the line (BEOL) metal levels with improved dielectric capping layer to metal wire adhesion. The method includes process step(s) designed to address dielectric capping layer to metal wire adhesion, when the metal wire(s) in a given metal level are relatively thick. These process step(s) can include, for example: (1) selective adjustment of the deposition tool used to deposit the dielectric capping layer onto metal wires based on the pattern density of the metal wires in order to ensure that those metal wires actually achieve a temperature between 360° C.-400° C.; and/or (2) deposition of a relatively thin dielectric layer on the dielectric capping layer prior to formation of the next metal level in order to reduce the tensile stress of the metal wire(s) below without causing delamination. Also disclosed is an IC chip formed using the above-described method.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: December 25, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Felix P. Anderson, Edward C. Cooney, III, Michael S. Dusablon, David C. Mosher
  • Patent number: 10157826
    Abstract: A semiconductor device includes a plurality of lower conductive lines overlying a substrate and extending in a first direction, an insulating layer overlying the plurality of lower conductive lines, a plurality of upper conductive lines overlying the insulating layer and the first conductive lines and extending in a second direction crossing the first direction, and a plurality of vias filled with a conductive material formed in the insulating layer. The plurality of upper conductive lines are arranged in the first direction with a first pitch. The plurality of vias includes first vias and second vias. At least one via of the first vias connects at least two lines of the plurality of lower conductive lines and one line of the plurality of upper conductive lines. An average width in the first direction of the first vias is different from an average width in the first direction of the second vias.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Yen Liu, Boo Yeh, Min-Chang Liang, Jui-Yao Lai, Sai-Hooi Yeong, Ying-Yan Chen, Yen-Ming Chen
  • Patent number: 10153231
    Abstract: An interconnect structure includes a dielectric layer and a conductor embedded in the dielectric layer. A top surface of the conductor is flush with a top surface of the dielectric layer. A cobalt cap layer is deposited on the top surface of the conductor. A nitrogen-doped cobalt layer is disposed on the cobalt cap layer.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: December 11, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ko-Wei Lin, Hung-Miao Lin, Chun-Ling Lin, Ying-Lien Chen, Huei-Ru Tsai, Sheng-Yi Su
  • Patent number: 10134673
    Abstract: According to some embodiments, a semiconductor device includes a substrate and an insulating film that is provided on the substrate. The device further includes a contact plug which includes a barrier metal layer provided in the insulating film, and a plug material layer provided in the insulating film, the barrier metal layer disposed between the plug material layer and the insulating film. The barrier metal layer includes at least a first layer including a first metal element and nitrogen, and a second layer including a second metal element different from the first metal element, and nitrogen.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: November 20, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Masayuki Kitamura, Atsuko Sakata
  • Patent number: 10128150
    Abstract: Implementations of the present disclosure generally relate to methods for forming thin films in high aspect ratio feature definitions. In one implementation, a method of processing a substrate in a process chamber is provided. The method comprises flowing a boron-containing precursor comprising a ligand into an interior processing volume of a process chamber, flowing a nitrogen-containing precursor comprising the ligand into the interior processing volume and thermally decomposing the boron-containing precursor and the nitrogen-containing precursor in the interior processing volume to deposit a boron nitride layer over at least one or more sidewalls and a bottom surface of a high aspect ratio feature definition formed in and below a surface of a dielectric layer on the substrate.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: November 13, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Pramit Manna, Rui Cheng, Kelvin Chan, Abhijit Basu Mallick
  • Patent number: 10121876
    Abstract: In case of performing annealing at a temperature of 1300° C. or higher, it is not possible to sufficiently suppress escape of nitrogen from a GaN layer even if a cap layer is provided thereon. Thereby, the front surface of the GaN layer is roughened. A semiconductor device manufacturing method of manufacturing a semiconductor device having a nitride semiconductor layer is provided. The semiconductor device manufacturing method includes: implanting, into a predetermined region of the nitride semiconductor layer, n-type or p-type impurities relative to the nitride semiconductor layer; forming, by atomic layer deposition, a first protective film containing a nitride on and in direct contact with at least the predetermined region; and annealing the nitride semiconductor layer and the first protective film at a temperature of 1300° C. or higher.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: November 6, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Shinya Takashima, Katsunori Ueno, Masaharu Edo
  • Patent number: 10121746
    Abstract: A semiconductor device includes a semiconductor substrate, a first metal layer, an insulation layer, an organic layer, and a second metal layer. The first metal layer, the insulation layer, the organic layer, and the second metal layer are sequentially stacked on a surface of the semiconductor substrate. The first metal layer and the second metal layer are electrically connected to each other through vias formed in the insulation layer and the organic layer. The second metal layer includes an electrode pad at a position corresponding to the positions of the vias. At the interface between the surface of the semiconductor substrate and the first metal layer, a patch portion having a trapezoidal cross-sectional shape is disposed directly below the vias.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: November 6, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Kazuya Kobayashi, Yuichi Sano, Daisuke Tokuda, Hiroaki Tokuya
  • Patent number: 10115633
    Abstract: A method for producing self-aligned line end vias and the resulting device are provided. Embodiments include trench lines formed in a dielectric layer; each trench line including a pair of self aligned line end vias; and a high-density plasma (HDP) oxide, silicon carbide (SiC) or silicon carbon nitride (SiCNH) formed between each pair of self aligned line end vias, wherein the trench lines and self aligned line end vias are filled with a metal liner and metal.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: October 30, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: John H. Zhang, Carl J. Radens, Lawrence A. Clevenger
  • Patent number: 10109521
    Abstract: A method of forming hybrid Co and Cu CA/CB contacts and the resulting device are provided. Embodiments include forming a forming a plurality of trenches through an ILD down to a substrate; forming a first metal liner on side and bottom surfaces of each trench and over the ILD; annealing the first metal liner; forming a second metal liner over the first metal liner; forming a first plating layer over a portion of the second metal liner in each trench; forming a second plating layer over the second metal liner and first plating layer in a remaining portion of each trench, the first and second plating layers being different materials; and planarizing the second plating layer and the second and first metal liners down to the ILD.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: October 23, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Qiang Fang, Shafaat Ahmed, Changhong Wu, Zhiguo Sun, Jiehui Shu
  • Patent number: 10109635
    Abstract: A method of forming a semiconductor device includes forming a tungsten layer over a semiconductor substrate in a first chamber, transferring the substrate over which the tungsten layer is formed from the first chamber to a second chamber without exposing into an atmosphere including oxygen, and forming a silicon nitride layer on the tungsten layer in the second chamber.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: October 23, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Kenichi Kusumoto, Yasutaka Iuchi
  • Patent number: 10090381
    Abstract: A semiconductor device comprises a lower structure on a substrate and including a recess region, first and second barrier layers covering an inner surface of the recess region and a top surface of the lower structure, the inner surface of the recess region including a bottom surface and an inner sidewall connecting the bottom surface to the top surface of the lower structure, and an interlayer dielectric layer provided on the second barrier layer and defining an air gap in the recess region. A first step coverage is obtained by dividing a thickness of the first barrier layer on an inner sidewall of the recess region by a thickness of the first barrier layer on the top surface of the lower structure. A second step coverage is obtained by dividing a thickness of the second barrier layer on the inner sidewall of the recess region by a thickness of the second barrier layer on the top surface of the lower structure. The first step coverage is different from the second step coverage.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: October 2, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jongmin Baek, Vietha Nguyen, Wookyung You, Sangshin Jang, Byunghee Kim, Kyu-Hee Han
  • Patent number: 10079295
    Abstract: A method for manufacturing an oxide semiconductor layer, comprising forming an oxide semiconductor layer over an insulating layer so as to be along with a curved surface of a projecting structural body of the insulating layer, wherein a length of the projecting structural body in a height direction is larger than a width of the projecting structural body, is provided.
    Type: Grant
    Filed: February 24, 2015
    Date of Patent: September 18, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Atsuo Isobe, Toshinari Sasaki, Shinya Sasagawa, Akihiro Ishizuka
  • Patent number: 10055067
    Abstract: [Object] To provide a sensor device capable of detecting an operation position and a pressing force with high accuracy. [Solution] A sensor device includes a first conductor layer, an electrode substrate, and a plurality of first structural bodies configured to separate the first conductor layer from the electrode substrate. At least one of the first conductor layer and the electrode substrate has flexibility. The electrode substrate includes a plurality of first electrodes and a plurality of second electrodes intersecting the plurality of first electrodes. At least one of the first and second electrodes includes a plurality of sub-electrodes.
    Type: Grant
    Filed: February 6, 2014
    Date of Patent: August 21, 2018
    Assignee: Sony Corporation
    Inventors: Shogo Shinkai, Kei Tsukamoto, Tomoko Katsuhara, Hiroto Kawaguchi, Hayato Hasegawa, Fumihiko Iida, Takayuki Tanaka, Tomoaki Suzuki, Taizo Nishimura, Hiroshi Mizuno, Yasuyuki Abe
  • Patent number: 10032698
    Abstract: An interconnection structure and method disclosed for providing an interconnection structure that includes conductive features having reduced topographic variations. The interconnection structure includes a contact pad disposed over a substrate. The contact pad includes a first layer of a first conductive material and a second layer of a second conductive material over the first layer. The first conductive material and the second conductive material are made of substantially the same material and have a first average grain size and a second average grain size that is smaller than the first average grain size. The interconnection structure also includes a passivation layer covering the substrate and the contact pad, and the passivation layer has an opening exposing the contact pad.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: July 24, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Hsiao Yun Lo, Yung-Chi Lin, Yang-Chih Hsueh, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Patent number: 10008446
    Abstract: A structure for an e-Fuse device in a semiconductor device is described. The e-Fuse device includes an anode region, a cathode region and a fuse element which interconnects the anode and cathode regions in a dielectric material on a first surface of a substrate. The fuse element has a smaller cross section and a higher aspect ratio than the anode and cathode regions. The anode and cathode regions are comprised of a high EM-resistant conductive material. The fuse element is comprised of low EM-resistant conductive material.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: June 26, 2018
    Assignee: International Business Machines Corporation
    Inventors: Daniel C Edelstein, Chih-Chao Yang
  • Patent number: 10008409
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a dielectric layer on a substrate; forming a stop layer between the dielectric layer and the substrate, wherein the stop layer contacts the substrate directly and the dielectric layer covers the top surface of the stop layer; forming an opening in the dielectric layer, wherein the dielectric layer comprises a damaged layer adjacent to the opening; forming a dielectric protective layer in the opening; forming a metal layer in the opening; removing the damaged layer and the dielectric protective layer to form a void, wherein the void exposes a top surface of the substrate; and forming a cap layer on and covering the dielectric layer, the void, and the metal layer.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: June 26, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chich-Neng Chang, Ya-Jyuan Hung, Bin-Siang Tsai