At Least One Layer Forms A Diffusion Barrier Patents (Class 257/751)
  • Patent number: 10692717
    Abstract: A method for defining thin film layers on a surface of a substrate includes exposing the surface of the substrate to a first precursor via a first plasma to allow the first precursor to be absorbed by the surface of the substrate. A second precursor that is different from the first precursor is applied to the surface of the substrate via a second plasma. The second precursor is a Carbon dioxide precursor that releases sufficient oxygen radicals to react with the first precursor to form an oxide film layer on the surface of the substrate.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: June 23, 2020
    Assignee: Lam Research Corporation
    Inventors: Douglas Walter Agnew, Ishtak Karim
  • Patent number: 10686014
    Abstract: Embodiments of the invention provide a semiconductor memory device. In some embodiments, the device includes a bottom electrode extending in a y-direction relative to top surface of a substrate and a top electrode extending in an x-direction relative to the top surface of the substrate. An active area is located at the cross-section between the bottom electrode and the top electrode and is located on vertical side walls extending in a z-direction of the semiconductor memory device with respect to the top surface of the substrate. An insulating layer is located in the active area in between the top electrode and the bottom electrode.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: June 16, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Juntao Li, Kangguo Cheng, Takashi Ando, Dexin Kong
  • Patent number: 10679937
    Abstract: Devices and methods of fabricating integrated circuit devices for forming low resistivity interconnects are provided. One method includes, for instance: obtaining an intermediate semiconductor interconnect device having a substrate, a cap layer, and a dielectric matrix including a set of trenches and a set of vias; depositing a barrier layer along a top surface of the semiconductor interconnect device; depositing and annealing a metal interconnect material over a top surface of the barrier layer, wherein the metal interconnect material fills the set of trenches and the set of vias; planarizing a top surface of the intermediate semiconductor interconnect device; exposing a portion of the barrier layer between the set of trenches and the set of vias; and depositing a dielectric cap. Also disclosed is an intermediate device formed by the method.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: June 9, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Xunyuan Zhang, Frank W. Mont, Errol Todd Ryan
  • Patent number: 10672686
    Abstract: A method of forming a conductive through substrate via includes forming an opening in a first surface of a semiconductor substrate comprising a LDMOS transistor structure in the first surface, forming a first conductive layer in a first portion of the opening in the semiconductor substrate using first deposition parameters such that the first conductive layer fills the opening in the first portion, and forming a second conductive layer on the first conductive layer in a second portion of the opening using second deposition parameters such that the second conductive layer bounds a gap in the second portion.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: June 2, 2020
    Assignee: Infineon Technologies AG
    Inventors: Albert Birner, Helmut Brech, Matthias Zigldrum
  • Patent number: 10665556
    Abstract: A mechanism of a semiconductor structure with composite barrier layer under redistribution layer is provided. A semiconductor structure includes a substrate comprising a top metal layer on the substrate; a passivation layer over the top metal layer having an opening therein exposing the top metal layer; a composite barrier layer over the passivation layer and the opening, the composite barrier layer includes a center layer, a bottom layer, and an upper layer, wherein the bottom layer and the upper layer sandwich the center layer; and a redistribution layer (RDL) over the composite barrier layer and electrically connecting the underlying top metal layer.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: May 26, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Yu Wu, Yu-Wei Shang, Chung-Ruei Kang
  • Patent number: 10658313
    Abstract: Representative implementations of techniques and devices are used to remedy or mitigate the effects of damaged interconnect pads of bonded substrates. A recess of predetermined size and shape is formed in the surface of a second substrate of the bonded substrates, at a location that is aligned with the damaged interconnect pad on the first substrate. The recess encloses the damage or surface variance of the pad, when the first and second substrates are bonded.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: May 19, 2020
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Javier A. Delacruz, Rajesh Katkar, Shaowu Huang, Gaius Gillman Fountain, Jr., Liang Wang, Laura Wills Mirkarimi
  • Patent number: 10658176
    Abstract: One illustrative method disclosed includes, among other things, forming a first dielectric layer and forming first and second conductive structures comprising cobalt embedded in the first dielectric layer. A second dielectric layer is formed above and contacting the first dielectric layer. The first and second dielectric layers comprise different materials, and a portion of the second dielectric layer comprises carbon or nitrogen. A first cap layer is formed above the first and second conductive structures and the second dielectric layer.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: May 19, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Frank W. Mont, Han You, Shariq Siddiqui, Brown C. Peethala
  • Patent number: 10658235
    Abstract: Metal interconnect structures are reworked to address possible voids or other defects. Etching of initially deposited interconnect metal to open voids is followed by reflow to accumulate interconnect metal at the bottoms of trenches. Additional interconnect metal is deposited over the initially deposited interconnect metal by electroplating and/or electroless plating. Additional diffusion barrier material may be deposited and patterned prior to deposition of the additional interconnect material.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: May 19, 2020
    Assignee: International Business Machines Corporation
    Inventors: Prasad Bhosale, Terry A. Spooner, Chih-Chao Yang, Lawrence A. Clevenger
  • Patent number: 10658676
    Abstract: An object of the invention is to provide an oxygen reduction catalyst composed of a titanium oxynitride having high oxygen reduction capacity. The oxygen reduction catalyst of the invention is a titanium oxynitride that has a nitrogen element content of 8.0 to 15 mass %, has a crystal structure of anatase titanium dioxide in a powder X-ray diffraction measurement, and has a signal intensity ratio N—Ti—N/O—Ti—N in an X-ray photoelectron spectroscopic analysis of in the range of 0.35 to 0.70.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: May 19, 2020
    Assignees: SHOWA DENKO K.K., NATIONAL UNIVERSITY CORPORATION YOKOHAMA NATIONAL UNIVERSITY
    Inventors: Kunchan Lee, Yoshinori Yamato, Kenichiro Ota, Akimitsu Ishihara
  • Patent number: 10651292
    Abstract: A semiconductor device includes an active region over a substrate; a first cobalt-containing feature disposed over the active region; a conductive cap disposed over and in physical contact with the first cobalt-containing feature; and a second cobalt-containing feature disposed over and in physical contact with the conductive cap.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: May 12, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Liang Cheng, Yen-Yu Chen
  • Patent number: 10651082
    Abstract: In an example, there is disclosed a chemical compound, including a transition metal, a post-transition metal, a metalloid, and a nonmetal. By way of non-limiting example, the post-transition metal may be aluminum. The transition metal is selected from the group consisting of tungsten, tantalum, hafnium, molybdenum, niobium, zirconium, vanadium, and titanium. The metalloid may be boron or silicon. The nonmetal may be carbon or nitrogen. The compound may be used, for example, as a barrier material in an integrated circuit.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: May 12, 2020
    Assignee: Intel Corporation
    Inventors: Daniel J. Zierath, Jason A. Farmer, Daniel B. Bergstrom
  • Patent number: 10651084
    Abstract: A microelectronic device comprises a first conductive material comprising copper, a conductive plug comprising tungsten in electrical communication with the first conductive material, and manganese particles dispersed along an interface between the first conductive material and the conductive plug. Related electronic systems and related methods are also disclosed.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: May 12, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Kentaro Ishii
  • Patent number: 10651081
    Abstract: The present disclosure provides a semiconductor structure and a method for manufacturing the semiconductor structure. The semiconductor structure includes a semiconductor substrate, a dielectric layer, a barrier layer, and a conductive layer. The semiconductor substrate has a plurality of mesas. The dielectric layer is disposed over the semiconductor substrate and has a plurality of blocks disposed over the mesas, respectively. The barrier layer is formed over a first lateral surface of the mesa, a second lateral surface of the block, an upper surface of the semiconductor substrate adjacent to the first lateral surface, and a front surface of the dielectric layer adjacent to the second lateral surface. The conductive layer has a base and a plurality of protrusions extending from the base and in contact with the barrier layer disposed over the upper surface, the first lateral surface, and the second lateral surface. A grain size of the base and the protrusions is consistent.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: May 12, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chung-Lin Huang
  • Patent number: 10651284
    Abstract: One illustrative method disclosed includes, among other things, selectively forming a gate-to-source/drain (GSD) contact opening and a CB gate contact opening in at least one layer of insulating material and forming an initial gate-to-source/drain (GSD) contact structure and an initial CB gate contact structure in their respective openings, wherein an upper surface of each of the GSD contact structure and the CB gate contact structure is positioned at a first level, and performing a recess etching process on the initial GSD contact structure and the initial CB gate contact structure to form a recessed GSD contact structure and a recessed CB gate contact structure, wherein a recessed upper surface of each of these recessed contact structures is positioned at a second level that is below the first level.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: May 12, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Youngtag Woo, Daniel Chanemougame, Bipul C. Paul, Lars W. Liebmann, Heimanu Niebojewski, Xuelian Zhu, Lei Sun, Hui Zang
  • Patent number: 10651125
    Abstract: Various methods and structures for fabricating BEOL metallization layer including at least one bulk cobalt contact, the at least one bulk cobalt contact including a replacement non-cobalt metal cap integral to the at least one bulk cobalt contact. The method includes performing selective deposition, by a chemical exchange reaction of metal between a non-cobalt metal and Cobalt in the at least one bulk cobalt contact, of the replacement non-cobalt metal cap integrally formed in a top surface region of the bulk cobalt contact.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: May 12, 2020
    Assignee: International Business Machines Corporation
    Inventors: James J. Kelly, Cornelius Brown Peethala
  • Patent number: 10651140
    Abstract: A method of manufacturing a semiconductor device includes forming a semiconductor substrate that has a conductive structure, and forming a precursor auxiliary layer stack on a first section of the conductive structure. The precursor auxiliary layer stack has a precursor adhesion layer and a precursor barrier layer between the precursor adhesion layer and the conductive structure. The precursor adhesion layer contains a second metal. The method further includes forming, on the precursor auxiliary layer stack, a metal structure containing a first metal and forming, from portions of the precursor auxiliary layer stack an adhesive layer containing the first and second metals.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: May 12, 2020
    Assignee: Infineon Technologies AG
    Inventors: Manfred Schneegans, Franziska Haering, Hans-Joachim Schulze, Bernhard Weidgans
  • Patent number: 10636705
    Abstract: The method of treating a film stack includes depositing a barrier film containing a metal into a via formed within a dielectric layer disposed on a substrate and depositing a metal contact on the barrier film within the via, where a void is located within the barrier film or between the barrier film and the metal contact. The method also includes exposing the metal contact and the barrier film to an oxidizing agent at a temperature of less than 400° C. and at a pressure of about 20 bar to about 100 bar within a process chamber to produce a metal oxide within the void.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: April 28, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Yifei Wang, Kurtis Leschkies, Fei Wang, Xin Liu, Wei Tang, Yixiong Yang, Wenyi Liu, Ludovic Godet
  • Patent number: 10622250
    Abstract: Apparatus and methods for dielectric gap fill evaluations are provided. In one example, a method can comprise providing a gap fill substrate over one or more interlayer dielectric trenches of a dielectric layer and over a first material located in the one or more interlayer dielectric trenches. The method can also comprise depositing a gap fill candidate material within one or more gap fill substrate trenches of the gap fill substrate. Furthermore, the method can comprise etching the gap fill candidate material until a void within the first material is identified. Additionally, the method can comprise filling the one or more gap fill substrate trenches with a second material to form one or more contacts with the first material to measure a leakage current of one or more pitches.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: April 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Isabel Cristina Chu, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Ekmini Anuja De Silva, Gauri Karve, Fee Li Lie, Nicole Adelle Saulnier, Indira Seshadri, Hosadurga Shobha
  • Patent number: 10622304
    Abstract: A storage device includes a first wiring layer, a second wiring layer spaced from the first wiring layer in a first direction, and a plurality of electrode layers stacked in the first direction between the first wiring layer and the second wiring layer. A semiconductor pillar penetrates the plurality of electrode layers in the first direction. The plurality of electrode layers includes a first electrode layer connected to a first wire in the first wiring layer and a second electrode layer connected to a second wire in the second wiring layer.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: April 14, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Hanae Ishihara
  • Patent number: 10622360
    Abstract: A semiconductor device includes a substrate with an active region, a plurality of conductive line structures on the substrate, an insulating layer separating the plurality of conductive line structures from the substrate, a contact plug between every two adjacent conductive line structures, an insulating spacer structure between each conductive line structure and a corresponding contact plug, a landing pad connected to each contact plug, and a landing pad insulation pattern having an asymmetrical shape based on a vertical axis of the landing pad that extends along a normal to the substrate. The landing pad insulation pattern includes a first portion overlapping the conductive line structures and a second portion overlapping the contact plug, the first and second portions being on opposite sides of the vertical axis.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: April 14, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Nam-gun Kim, Sang-min Lee, Tae-seop Choi, Kon Ha, Seung-jae Lee
  • Patent number: 10615116
    Abstract: A conductive interface includes a first conductor having a recessed area in least one surface. A dielectric layer has a trench positioned over the first conductor. A nitridized layer is formed on a top surface of the first conductor around the recessed area, to a depth on the first conductor that is shallower than a depth of the recessed area. A second conductor is formed in the trench and the recessed area to form a conductive contact with the first conductor.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: April 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lawrence A. Clevenger, Roger A. Quon, Terry A. Spooner, Wei Wang, Chih-Chao Yang
  • Patent number: 10607936
    Abstract: A method of forming an elevationally-extending conductor laterally between a pair of structures comprises forming a pair of structures individually comprising an elevationally-extending-conductive via and a conductive line electrically coupled to and crossing above the conductive via. The conductive line and the conductive via respectively have opposing sides in a vertical cross-section. Elevationally-extending-insulative material is formed along the opposing sides of the conductive via and the conductive line in the vertical cross-section. The forming of the insulative material comprises forming a laterally-inner-insulator material comprising silicon, oxygen, and carbon laterally-outward of the opposing sides of the conductive via and the conductive line in the vertical cross-section. A laterally-intervening-insulator material comprising silicon and oxygen is formed laterally-outward of opposing sides of the laterally-inner-insulator material in the vertical cross-section.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: March 31, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Silvia Borsari
  • Patent number: 10607954
    Abstract: A semiconductor device includes a substrate, a wiring formed on the substrate, an anti-reflection film of titanium nitride formed on the wiring, and a silicon oxide film formed on the anti-reflection film. A pad portion which exposes the wiring is formed at a place where a first opening portion and a second opening portion overlap with each other. A metal nitride region containing fewer dangling bonds is formed from a metal nitride film containing fewer dangling bonds than in the anti-reflection film in at least a part of one or both of an opposed surface of the anti-reflection film which faces the silicon oxide film above the anti-reflection film, and an exposed surface of the anti-reflection film which is exposed in the second opening portion.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: March 31, 2020
    Assignee: ABLIC INC.
    Inventors: Shinjiro Kato, Masaru Akino
  • Patent number: 10593865
    Abstract: A magnetoresistive random access memory (MRAM) is provided in the present invention, including a conductive plug with a protruding portion extending outwardly on one side and a notched portion concaving inwardly on the other side of the upper edge of conductive plug, and a memory cell with a bottom electrode electrically connecting with the conductive plug, a magnetic tunnel junction (MTJ) on the bottom electrode, and a top electrode on the magnetic tunnel junction, wherein the bottom surface of memory cell completely overlaps the top surface of conductive plug.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: March 17, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hung-Chan Lin, Yu-Ping Wang, Hung-Yueh Chen
  • Patent number: 10585211
    Abstract: The invention relates to an article comprising a substrate having at least one major surface coated with a layer A of a material obtained by ion beam assisted vacuum deposition of at least one titanium oxide and of at least one organosilicate compound B, said material having a refractive index at 550 nm higher than or equal to 1.8, an extinction coefficient k at 550 nm lower than or equal to 0.02, and an H:E ratio higher than or equal to 0.046, where H and E designate the hardness of the material and the elastic coefficient of the material, respectively.
    Type: Grant
    Filed: April 28, 2014
    Date of Patent: March 10, 2020
    Assignees: CORPORATION DE L'ECOLE POLYTECHNIQUE DE MONTREAL, ESSILOR INTERNATIONAL
    Inventors: Oleg Zabeida, Thomas Schmitt, Jolanta Sapieha, Ludvik Martinu, Karin Scherer
  • Patent number: 10586767
    Abstract: A method for fabricating semiconductor wafers comprises creating a semiconductor wafer having a plurality of wide copper wires and a plurality of narrow copper wires embedded in a dielectric insulator. The width of each wide copper wire is greater than a cutoff value and each narrow copper is less than the cutoff value. An optical pass through layer is deposited over a top surface of the wafer and a photo-resist layer is deposited over the optical pass through layer. The wafer is exposed to a light source to selectively remove photo-resist, forming a self-aligned pattern where photo-resist only remains in areas above wide copper wires. The self-aligned pattern is transferred to the optical pass through layer and the remaining photo-resist is removed. The wafer is chemically etched to remove the narrow copper wires, defining narrow gaps in the dielectric insulator. The wafer is metallized with non-copper metal, forming narrow non-copper metal wires.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: March 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Cornelius Brown Peethala, Michael Rizzolo, Koichi Motoyama, Gen Tsutsui, Ruqiang Bao, Gangadhara Raja Muthinti, Lawrence A. Clevenger
  • Patent number: 10566243
    Abstract: A method of manufacturing a semiconductor device includes providing a substrate structure including a semiconductor substrate, an interlayer dielectric layer on the semiconductor substrate, multiple trenches extending through the interlayer dielectric layer to the semiconductor substrate and including a first trench of a first NMOS device and a second trench of a second NMOS device, and a dielectric layer on sidewalls and a bottom of the trenches, forming an NMOS work function adjustment layer on the dielectric layer, performing a first oxidation treatment on the NMOS work function adjustment layer in the first trench to form a first oxide layer, and a second oxidation treatment on the NMOS work function adjustment layer in the second trench to form a second oxide layer, and forming a metal electrode layer in the trenches. The first oxide layer has an oxygen content lower than that of the second oxide layer.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: February 18, 2020
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Jiaqi Yang, Jie Zhao
  • Patent number: 10553483
    Abstract: A method of fabricating a semiconductor interconnect structure by providing a semiconductor structure with a dielectric layer with and an embedded electrically conductive structure. A dielectric capping layer and a metal capping layer separating a second dielectric layer located above the first dielectric layer. The segment of metal capping layer covers at least a portion of a top surface of the first electrically conductive structure. Exposing parts of both the first electrically conductive structure and the dielectric capping layer by forming an opening in the second dielectric layer and the metal capping layer. Forming a second electrically conductive structure in the opening, such that (i) the second electrically conductive structure is located over part of the dielectric capping layer, and (ii) the second electrically conductive structure is in electrical contact with the first electrically conductive structure.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: February 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Conal E. Murray, Chih-Chao Yang
  • Patent number: 10553487
    Abstract: A semiconductor device has a semiconductor wafer and a conductive via formed partially through the semiconductor wafer. A portion of the semiconductor wafer and conductive via is removed by a chemical mechanical polishing process. The semiconductor wafer and conductive via are coplanar at first and second surfaces. A first insulating layer and a second insulating layer are formed over the conductive via and semiconductor wafer. The first insulating layer includes an inorganic material and the second insulating layer includes an organic material. An opening in the first and second insulating layers is formed over the conductive via while a second portion of the conductive via remains covered by the first and second insulating layers. A conductive layer is formed over the conductive via and first insulating layer. An interconnect structure is formed over the conductive layer. The semiconductor wafer is singulated into individual semiconductor die.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: February 4, 2020
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Xing Zhao, Duk Ju Na, Lai Yee Chia
  • Patent number: 10546826
    Abstract: A device and method of preventing corrosion of a copper layer in a PCB is disclosed. A first dielectric is disposed on a substrate. A copper layer is plated in an opening in the first dielectric and, after conditioning the copper layer, a redistribution layer is plated on the copper layer. A solder resist layer is disposed above the copper layer. A solder ball is disposed in an opening in the solder resist layer. The solder ball is in conductive contact with the copper layer and in physical contact with the redistribution layer. A non-conductive carbon layer is disposed on and in contact with the redistribution layer or tsi-diehe solder resist layer. The carbon layer is substantially thinner than the copper layer and acts as a diffusion barrier to moisture for the copper layer.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: January 28, 2020
    Inventor: Georg Seidemann
  • Patent number: 10546861
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The method includes providing a substrate, a plurality of word lines and a plurality of bit lines, and then forming a storage node contact on each source/drain region, so that a width of a top surface of each storage node contact in a direction is less than a width of a bottom surface of each storage node contact.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: January 28, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Tzu-Tsen Liu, Li-Wei Feng, Chien-Ting Ho
  • Patent number: 10541174
    Abstract: A semiconductor device is provided. The semiconductor device can have a substrate including dielectric material. A plurality of narrow interconnect openings can be formed within said dielectric material. In addition, a plurality of wide interconnect openings can be formed within said dielectric material. The semiconductor device can include a first metal filling the narrow interconnect openings to form an interconnect structure and conformally covering a surface of the wide interconnect openings formed in the dielectric material, and a second metal formed over the first metal and encapsulated by the first metal to form another interconnect structure within the wide interconnect openings.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: January 21, 2020
    Assignee: Tokyo Electron Limited
    Inventors: Soo Doo Chae, Jeffrey Smith, Gerrit J. Leusink, Robert D. Clark, Kai-Hung Yu
  • Patent number: 10541199
    Abstract: An alloy liner is located on a diffusion barrier liner and both are present in at least a via portion of a combined via/line opening that is present in an interconnect dielectric material. The alloy liner includes an alloy of a first metal or metal alloy having a first bulk resistivity and a second metal or metal alloy having a second bulk resistivity that is higher than the first bulk resistivity. A first electrically conductive structure is located on the alloy liner and is present in at least the via portion of the combined via/line opening. The first electrically conductive structure includes the second metal or metal alloy. A second electrically conductive structure can be present in at least the line portion of the combined via/line opening. The second electrically conductive structure may include a metal or metal alloy having the first or second bulk resistivity.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: January 21, 2020
    Assignee: International Business Machines Corporation
    Inventor: Chih-Chao Yang
  • Patent number: 10535608
    Abstract: Multi-chip package structures and methods for constructing multi-chip package structures are provided, which utilize chip interconnection bridge devices that are designed to provide high interconnect density between adjacent chips (or dies) in the package structure, as well as provide vertical power distribution traces through the chip interconnection bridge device to supply power (and ground) connections from a package substrate to the chips connected to the chip interconnection bridge device.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: January 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Joshua Rubin, Lawrence A. Clevenger, Charles L. Arvin
  • Patent number: 10535525
    Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a semiconductor substrate, a gate structure, a first doped structure, a second doped structure, and a dielectric layer. The method includes forming a through hole in the dielectric layer. The method includes performing a physical vapor deposition process to deposit a first metal layer over the first doped structure exposed by the through hole. The method includes reacting the first metal layer with the first doped structure to form a metal semiconductor compound layer between the first metal layer and the first doped structure. The method includes removing the first metal layer. The method includes performing a chemical vapor deposition process to deposit a second metal layer in the through hole. The method includes forming a conductive structure in the through hole and over the second metal layer.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: January 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-An Lin, Chun-Hsiung Lin, Kai-Hsuan Lee, Sai-Hooi Yeong, Cheng-Yu Yang, Yen-Ting Chen
  • Patent number: 10529662
    Abstract: A method for manufacturing a semiconductor device includes forming a plurality of trenches in a dielectric layer, wherein the plurality of trenches each comprise a rounded surface, depositing a liner layer on the rounded surface of each of plurality of trenches, and depositing a conductive layer on the liner layer in each of the plurality of trenches, wherein the conductive layer and the liner layer form a plurality of interconnects, and each of the plurality of interconnects has a cylindrical shape.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: January 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Michael Rizzolo, Christopher J. Penny, Huai Huang, Lawrence A. Clevenger, Hosadurga Shobha
  • Patent number: 10529663
    Abstract: Voids within metal deposited on interconnect structures are filled with cobalt or a cobalt compound to enhance electromigration performance. A reflow process to enlarge interconnect metal grain size is performed prior to filling the voids. An interconnect metal microstructure beneath the filled voids includes grain boundaries extending to the bottom portions of the voids. A coating of manganese atoms provides resistance to electromigration. Copper interconnects having fine dimensions and improved reliability are obtained.
    Type: Grant
    Filed: October 14, 2018
    Date of Patent: January 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Takeshi Nogami, Chih-Chao Yang
  • Patent number: 10529563
    Abstract: Methods for forming a doped metal oxide film on a substrate by cyclical deposition are provided. In some embodiments, methods may include contacting the substrate with a first reactant comprising a metal halide source, contacting the substrate with a second reactant comprising a hydrogenated source and contacting the substrate with a third reactant comprising an oxide source. In some embodiments, related semiconductor device structures may include a doped metal oxide film formed by cyclical deposition processes.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: January 7, 2020
    Assignee: ASM IP Holdings B.V.
    Inventors: Tom Blomberg, Chiyu Zhu
  • Patent number: 10522486
    Abstract: Methods of forming connectors and packaged semiconductor devices are disclosed. In some embodiments, a connector is formed by forming a first photoresist layer over an interconnect structure, and patterning the first photoresist layer. The patterned first photoresist layer is used to form a first opening in an interconnect structure. The patterned first photoresist is removed, and a second photoresist layer is formed over the interconnect structure and in the first opening. The second photoresist layer is patterned to form a second opening over the interconnect structure in the first opening. The second opening is narrower than the first opening. At least one metal layer is plated through the patterned second photoresist layer to form the connector.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: December 31, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung Wei Cheng, Hai-Ming Chen, Chien-Hsun Lee, Hao-Cheng Hou, Hung-Jen Lin, Chun-Chih Chuang, Ming-Che Liu, Tsung-Ding Wang
  • Patent number: 10522399
    Abstract: The present disclosure provides methods for forming a conductive fill material (e.g., a conductive feature) by a physical vapor deposition (PVD) process. In one embodiment, a method of forming a conductive fill material on a substrate includes maintaining a first substrate temperature at a first range for a first period of time while forming a pre-layer of a conductive fill material on a substrate, providing a thermal energy to the substrate to maintain the substrate at a second substrate temperature at a second range for a second period of time, wherein the second substrate temperature is higher than the first substrate temperature, and continuously providing the thermal energy to the substrate to maintain the substrate a third substrate temperature at a third range for a third period of time to form a bulk layer of the conductive fill material on the substrate.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: December 31, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Nai-Hao Yang, Hung-Wen Su, Kuan-Chia Chen
  • Patent number: 10504778
    Abstract: An embodiment contact plug includes a bilayer structure and a diffusion barrier layer on a sidewall and a bottom surface of the bilayer structure. The bilayer structure includes a conductive core and a conductive liner on a sidewall and a bottom surface of the conductive core. In the embodiment contact plug, the conductive liner comprises cobalt or ruthenium.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Lin, Sheng-Hsuan Lin, Chih-Wei Chang, You-Hua Chou, Chia-Lin Hsu
  • Patent number: 10497649
    Abstract: An integrated circuit device includes a metal film and a complex capping layer covering a top surface of the metal film. The metal film includes a first metal, and penetrates at least a portion of an insulating film formed over a substrate. The complex capping layer includes a conductive alloy capping layer covering the top surface of the metal film, and an insulating capping layer covering a top surface of the conductive alloy capping layer and a top surface of the insulating film. The conductive alloy capping layer includes a semiconductor element and a second metal different from the first metal. The insulating capping layer includes a third metal.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: December 3, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Su-Hyun Bark, Sang-Hoon Ahn, Young-Bae Kim, Hyeok-Sang Oh, Woo-Jin Lee, Hoon-Seok Seo, Sung-Jin Kang
  • Patent number: 10490501
    Abstract: Aspects of the present disclosure include a method for forming a contact on a semiconductor device, the semiconductor device including a conductive region disposed over a substrate, the method comprising: depositing a dielectric material on the substrate; forming an opening in the dielectric material to expose the conductive region; forming a barrier layer on a lower surface and sidewalls of the opening in the dielectric material, the barrier layer terminating below an upper surface of the dielectric material and surrounding a lower portion of the opening; depositing cobalt in the lower portion of the opening, the cobalt terminating at an upper surface of the barrier layer; depositing tungsten to fill the opening to at least the upper surface of the dielectric material; and planarizing the upper surface of the dielectric material with the tungsten in the opening.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: November 26, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jim Shih-Chun Liang, Keith Kwong Hon Wong
  • Patent number: 10483115
    Abstract: A semiconductor device includes a non-insulator structure, at least one carbon nano-tube (CNT), a dielectric layer, and a graphene-based conductive layer. The CNT is over the non-insulator structure. The dielectric layer surrounds the CNT. The graphene-based conductive layer is over the at least one CNT. The CNTs and the graphene-based conductive layer have low resistance.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: November 19, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: You-Hua Chou, Kuo-Sheng Chuang
  • Patent number: 10483163
    Abstract: A method is provided, including the following operations: performing a deposition process on a substrate, the deposition process configured to deposit a ruthenium layer in a feature on the substrate, the ruthenium layer being doped with zinc at an atomic percentage less than approximately 30 percent; after depositing the ruthenium layer, annealing the substrate, wherein the annealing is configured to cause migration of the zinc to an interface of the ruthenium layer and an oxide layer of the substrate, the migration of the zinc producing an adhesive barrier at the interface that inhibits electromigration of the ruthenium layer.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: November 19, 2019
    Assignee: Lam Research Corporation
    Inventors: Aniruddha Joi, Yezdi Dordi
  • Patent number: 10468296
    Abstract: A method of forming an electrical transmission structure that includes forming an opening through an interlevel dielectric layer to expose at least one electrically conductive feature and forming a shield layer on the opening. A gouge is formed in the electrically conductive feature through the opening using a subtractive method during which the shield layer protects the interlevel dielectric layer from being damaged by the subtractive method. A contact is formed within the opening in electrical communication with the at least one electrically conductive feature.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: November 5, 2019
    Assignee: International Business Machines Corporation
    Inventors: Conal E. Murray, Chih-Chao Yang
  • Patent number: 10468298
    Abstract: Techniques are disclosed for providing a decoupled via fill. Given a via trench, a first barrier layer is conformally deposited onto the bottom and sidewalls of the trench. A first metal fill is blanket deposited into the trench. The non-selective deposition is subsequently recessed so that only a portion of the trench is filled with the first metal. The previously deposited first barrier layer is removed along with the first metal, thereby re-exposing the upper sidewalls of the trench. A second barrier layer is conformally deposited onto the top of the first metal and the now re-exposed trench sidewalls. A second metal fill is blanket deposited into the remaining trench. Planarization and/or etching can be carried out as needed for subsequent processing. Thus, a methodology for filling high aspect ratio vias using a dual metal process is provided. Note, however, the first and second fill metals may be the same.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: November 5, 2019
    Assignee: Intel Corporation
    Inventors: Yuriy V. Shusterman, Flavio Griggio, Tejaswi K. Indukuri, Ruth A. Brain
  • Patent number: 10461026
    Abstract: Techniques for improving reliability in Cu interconnects using Cu intermetallics are provided. In one aspect, a method of forming a Cu interconnect in a dielectric over a Cu line includes the steps of: forming at least one via in the dielectric over the Cu line; depositing a metal layer onto the dielectric and lining the via such that the metal layer is in contact with the Cu line at the bottom of the via, wherein the metal layer comprises at least one metal that can react with Cu to form a Cu intermetallic; annealing the metal layer and the Cu line under conditions sufficient to form a Cu intermetallic barrier at the bottom of the via; and plating Cu into the via to form the Cu interconnect, wherein the Cu interconnect is separated from the Cu line by the Cu intermetallic barrier. A device structure is also provided.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: October 29, 2019
    Assignee: International Business Machines Corporation
    Inventors: Chao-Kun Hu, Christian Lavoie, Stephen M. Rossnagel, Thomas M. Shaw
  • Patent number: 10460985
    Abstract: A semiconductor structure and a process for forming a semiconductor structure. There is a back end of the line wiring layer which includes a wiring line, a cap layer and an ILD layer. A metal-filled via extends through the ILD layer to make contact with the wiring line. There is a reliability enhancement material in the cap layer. The reliability enhancement material surrounds the metal-filled via only in the cap layer to make a bottom of the metal-filled via that contacts the wiring line be under compressive stress, wherein the compressive reliability enhancement material has different physical properties than the cap layer. The reliability enhancement material may be compressive as deposited or may be made compressive after deposition.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: October 29, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lawrence A. Clevenger, Baozhen Li, Xiao H. Liu, Kirk D. Peterson
  • Patent number: 10453743
    Abstract: The present invention provides a barrier layer removal method, wherein the barrier layer includes at least one layer of ruthenium or cobalt, the method comprising: removing the barrier layer including ruthenium or cobalt formed on non-recessed areas of a semiconductor structure by thermal flow etching.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: October 22, 2019
    Assignee: ACM Research (Shanghai) Inc.
    Inventors: Zhaowei Jia, Dongfeng Xiao, Jian Wang, Hui Wang