At Least One Layer Forms A Diffusion Barrier Patents (Class 257/751)
  • Patent number: 12112983
    Abstract: An electrode structure for a device, such as a GaN or AlGaN device is described. In one example, a method to form the structure includes providing a substrate including gallium nitride material, forming an insulating layer over a surface of the substrate, forming an opening in the insulating layer to expose a surface region of the substrate, depositing a barrier metal layer over the insulating layer and onto the surface region of the substrate through the opening, and depositing a conducting metal layer over the barrier metal layer. In one case, the barrier metal layer includes a layer of tungsten nitride. The layer of tungsten nitride is deposited over the insulating layer and onto the surface region of the substrate using atomic layer deposition.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: October 8, 2024
    Assignee: MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC.
    Inventors: Timothy E. Boles, Wayne Mack Struble, Gabriel R. Cueva
  • Patent number: 12114486
    Abstract: A semiconductor structure and a method for forming the same are provided. The method includes: providing a semiconductor substrate; determining a position of a bit line contact opening on a top surface of the semiconductor substrate and a top surface of a first dielectric layer; etching an active region, the first dielectric layer and an isolation structure exposed by the bit line contact opening according to the position of the bit line contact opening until the active region is etched to a preset depth to form a bit line contact window; and forming a second dielectric layer on a surface of the isolation structure and a surface of the first dielectric layer that have a depth greater than a depth of a surface of the active region in the bit line contact window.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: October 8, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Wei Wan
  • Patent number: 12108627
    Abstract: A display device includes a first transistor having a first semiconductor layer, in which a first source region includes a first region in contact with a first source electrode, and a first drain region includes a second region in contact with a first drain electrode. The first source and drain regions, the first region, and the second region each include a first impurity element. In a region close to an interface between the first semiconductor layer and a first insulating layer, a concentration of the first impurity element included in the first and second regions is higher than a concentration of the first impurity element included in the first source region and the first drain region. A method of manufacturing a display device includes forming a first gate electrode and a light shielding layer on a first insulating layer, and forming a second semiconductor layer on the light shielding layer.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: October 1, 2024
    Assignee: JAPAN DISPLAY INC.
    Inventors: Akihiro Hanada, Kentaro Miura, Hajime Watakabe, Ryo Onodera
  • Patent number: 12080646
    Abstract: A method having a semiconductor substrate received and a first dielectric layer is formed over the semiconductor substrate. A trench is formed in the first dielectric layer. The trench is filled to form a conductive layer in the first dielectric layer. The conductive layer is segmented to form a first conductive feature and a second conductive feature separated from each other by a recess. The recess is filled with a second dielectric layer, such that one or both of the conductive features are end-capped by a portion of the first dielectric layer and a portion of the second dielectric layer.
    Type: Grant
    Filed: August 8, 2023
    Date of Patent: September 3, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Lin-Yu Huang, Li-Zhen Yu, Cheng-Chi Chuang, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 12046551
    Abstract: Interconnect structures and methods of forming the same are provided. An interconnect structure according to the present disclosure includes a conductive line feature over a substrate, a conductive etch stop layer over the conductive line feature, a contact via over the conductive etch stop layer, and a barrier layer disposed along a sidewall of the conductive line feature, a sidewall of the conductive etch stop layer, and a sidewall of the contact via.
    Type: Grant
    Filed: April 17, 2023
    Date of Patent: July 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chieh-Han Wu, Cheng-Hsiung Tsai, Chih Wei Lu, Chung-Ju Lee
  • Patent number: 11985817
    Abstract: The present disclosure relates to a semiconductor device and a forming method thereof. The forming method includes: providing a substrate; forming node contacts inside the substrate; forming landing pads on an upper surface of the substrate, where the landing pad is in contact with the node contact; forming a barrier layer on exposed surfaces of the landing pads and the node contacts; and after performing an electrical test on the semiconductor device on which the barrier layer is formed, removing the barrier layer on an upper surface of the landing pads.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: May 14, 2024
    Assignee: Changxin Memory Technologies, Inc.
    Inventors: Kai Cao, Liang Zhao
  • Patent number: 11978703
    Abstract: A semiconductor structure includes a conductive line, a pad layer, and a barrier layer. The conductive line is embedded in a multi-level interconnect structure. The pad layer is over the conductive line. The barrier layer is between the conductive line and the pad layer. The pad layer is electrically connected to the conductive line through the barrier layer, and the barrier layer includes a first poly-crystalline layer and a second poly-crystalline layer. A boundary is between the first poly-crystalline layer and the second poly-crystalline layer.
    Type: Grant
    Filed: November 17, 2022
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ya-Chin Chiu, Ming-Hsien Lin, Chia-Tung Hsu, Lun-Chieh Chiu
  • Patent number: 11980018
    Abstract: The present disclosure relates to a semiconductor device and a method of fabricating the same, which includes a substrate, a plurality of bit lines, a plurality of first plugs, a first spacer, a second spacer, a plurality of second plugs and a metal silicide layer. The bit lines are disposed on the substrate. The first plugs are disposed on the substrate and separated from the bit lines. The first spacer and the second spacer are disposed between each of the bit lines and the first plugs, and include a first height and a second height respectively. The second plugs are disposed on the first plugs respectively, and the metal silicide layer is disposed between the first plugs and the second plugs, wherein an end surface of the metal silicide layer is clamped between the second spacer and the first spacer.
    Type: Grant
    Filed: August 8, 2021
    Date of Patent: May 7, 2024
    Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yu-Cheng Tung, Janbo Zhang
  • Patent number: 11955534
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.
    Type: Grant
    Filed: December 7, 2022
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Andrew W. Yeoh, Joseph Steigerwald, Jinhong Shin, Vinay Chikarmane, Christopher P. Auth
  • Patent number: 11862535
    Abstract: The present disclosure relates an integrated chip. The integrated chip includes a semiconductor device arranged along a first side of a semiconductor substrate. The semiconductor substrate has one or more sidewalls extending from the first side of the semiconductor substrate to an opposing second side of the semiconductor substrate. A dielectric liner lines the one or more sidewalls of the semiconductor substrate. A through-substrate-via (TSV) is arranged between the one or more sidewalls and is separated from the semiconductor substrate by the dielectric liner. The TSV has a first width at a first distance from the second side and a second width at a second distance from the second side. The first width is smaller than the second width and the first distance is smaller than the second distance.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: January 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Ling Shih, Wei Chuang Wu, Shih Kuang Yang, Hsing-Chih Lin, Jen-Cheng Liu
  • Patent number: 11855178
    Abstract: A semiconductor device is provided. The semiconductor device includes a fin protruding from a semiconductor substrate and a gate structure formed across the fin. The semiconductor device also includes a gate spacer formed over a sidewall of the gate structure. The gate spacer includes a sidewall spacer and a sealing spacer formed above the sidewall spacer. In addition, an air gap is vertically sandwiched between the sidewall spacer and the sealing spacer. The semiconductor device further includes a hard mask formed over the gate structure and covering a sidewall of the sealing spacer.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Hsiung Lin, Pei-Hsun Wang, Chih-Chao Chou, Chia-Hao Chang, Chih-Hao Wang
  • Patent number: 11849576
    Abstract: A memory device includes a first semiconductor structure and a second semiconductor structure. The memory device further includes a bonding structure between the first semiconductor structure and the second semiconductor structure, the bonding structure comprising a first bonding pattern and a second bonding pattern in contact with each other, the first semiconductor structure being electrically connected with the second semiconductor structure through the bonding structure. The memory device further includes a shielding structure between the first semiconductor structure and the second semiconductor structure and surrounding the bonding structure, the shielding structure comprising a third bonding pattern and a fourth bonding pattern in contact with each other, the shielding structure being electrically connected with a biased voltage.
    Type: Grant
    Filed: January 9, 2023
    Date of Patent: December 19, 2023
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventor: Jin Yong Oh
  • Patent number: 11776583
    Abstract: A semiconductor memory device includes a plurality of bit line structures including bit lines extending in parallel in a first lateral direction on a substrate, and a plurality of buried contacts and a plurality of landing pads. The plurality of buried contacts fill lower portions of spaces between the plurality of bit line structures on the substrate, and the plurality of landing pads fill upper portions of the spaces between the plurality of bit line structures and extend on the plurality of bit line structures. The plurality of landing pads have a hexagonal array structure, and central points of respective top surfaces of a first landing pad, a second landing pad, and a third landing pad, which are adjacent to each other from among the plurality of landing pads, are connected by a scalene triangle.
    Type: Grant
    Filed: May 16, 2020
    Date of Patent: October 3, 2023
    Inventors: Hyejin Seong, Jisuk Park, Sungho Choi
  • Patent number: 11778811
    Abstract: A semiconductor memory device may include a substrate, a bit line structure extending in one direction on the substrate, the bit line structure including a sidewall, a storage node contact on the sidewall of the bit line structure, first and second spacers between the sidewall of the bit line structure and the storage node contact, the first spacer separated from the second spacer by a space between the first spacer and the second spacer, an interlayer dielectric layer on the bit line structure, the interlayer dielectric layer including a bottom surface, a spacer capping pattern extending downward from the bottom surface of the interlayer dielectric layer toward the space between the first and second spacers, and a landing pad structure penetrating the interlayer dielectric layer, the landing pad structure coupled to the storage node contact.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: October 3, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dongjun Lee, Sang Chui Shin, Bong-Soo Kim, Jiyoung Kim
  • Patent number: 11761086
    Abstract: Cobalt precursors are described, having application for vapor deposition of cobalt on substrates, such as in atomic layer deposition (ALD) and chemical vapor deposition (CVD) processes for forming interconnects, capping structures, and bulk cobalt conductors, in the manufacture of integrated circuitry and thin film products.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: September 19, 2023
    Assignee: ENTEGRIS, INC.
    Inventors: Thomas H. Baum, Scott L. Battle, John M. Cleary, David W. Peters, Philip S.H. Chen
  • Patent number: 11764343
    Abstract: A display backboard and a manufacturing method thereof, and a display device are provided. The display backboard includes: a driving substrate; a plurality of driving electrodes on the driving substrate; and a plurality of connection structures respectively on the plurality of driving electrodes. The connection structure includes: at least one conductive component on the driving electrode; and a restriction component on a side of the driving electrodes provided with the at least one conductive component and in at least a part of a peripheral region of the at least one conductive component. The restriction component protrudes from the driving electrode and has a first height in a direction perpendicular to the driving substrate.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: September 19, 2023
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zhiwei Liang, Yingwei Liu, Zhijun Lv, Ke Wang, Zhanfeng Cao, Hsuanwei Mai, Guangcai Yuan, Muxin Di
  • Patent number: 11728223
    Abstract: A semiconductor device and methods of forming the semiconductor device are described herein and are directed towards forming a source/drain contact plug for adjacent finFETs. The source/drain regions of the adjacent finFETs are embedded in an interlayer dielectric and are separated by an isolation region of a cut-metal gate (CMG) structure isolating gate electrodes of the adjacent finFETs The methods include recessing the isolation region, forming a contact plug opening through the interlayer dielectric to expose portions of a contact etch stop layer disposed over the source/drain regions through the contact plug opening, the contact etch stop layer being a different material from the material of the isolation region. Once exposed, the portions of the CESL are removed and a conductive material is formed in the contact plug opening and in contact with the source/drain regions of the adjacent finFETs and in contact with the isolation region.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: August 15, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Ting Chen, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
  • Patent number: 11715689
    Abstract: A device includes a first conductive feature disposed over a substrate; a second conductive feature disposed directly on and in physical contact with the first conductive feature; a dielectric layer surrounding sidewalls of the second conductive feature; and a first barrier layer interposed between the second conductive feature and the dielectric layer and in physical contact with both the second conductive feature and the dielectric layer. The first barrier layer and the dielectric layer comprise at least two common elements.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: August 1, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shin-Yi Yang, Ming-Han Lee, Shau-Lin Shue, Tz-Jun Kuo
  • Patent number: 11652044
    Abstract: A semiconductor device includes an insulating layer, wherein the insulating layer has a via opening and a conductive line opening. The semiconductor device further includes a via in the via opening, wherein the via includes a first conductive material. The semiconductor device further includes a conductive line in the conductive line opening. The conductive line includes a first liner layer, wherein a first thickness of the first liner layer over the via is less than a second thickness of the first liner layer over the insulating layer, and a conductive fill comprising a second conductive material different from the first conductive material.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: May 16, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu-Cheng Chin, Yao-Min Liu, Hung-Wen Su, Chih-Chien Chi, Chi-Feng Lin
  • Patent number: 11646283
    Abstract: A first metal layer can be deposited over first dielectric material layers of a first substrate, and can be patterned into first bonding pads. A first low-k material layer can be formed over the first bonding pads. The first low-k material layer includes a low-k dielectric material such as a MOF dielectric material or organosilicate glass. A second semiconductor die including second bonding pads can be provided. The first bonding pads are bonded to the second bonding pads to form a bonded assembly.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: May 9, 2023
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Lin Hou, Peter Rabkin, Masaaki Higashitani, Ramy Nashed Bassely Said
  • Patent number: 11616064
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a base substrate including a semiconductor substrate having a PMOS region and an NMOS region and a plurality of fins on the semiconductor substrate, a gate layer across the plurality of fins by covering portions of top and sidewall surfaces of the fins, a P-type doped epitaxial layer formed in the fins at both sides of the gate layer in the PMOS region, an N-type doped epitaxial layer formed in the fins at both sides of the gate layer in the NMOS region, and an N-region mask layer formed on sidewall surfaces of the N-type doped epitaxial layer and covering the P-type doped epitaxial layer. A portion of the N-type doped epitaxial layer exposed by the N-region mask layer is processed by an N-type dopant segregated Schottky doping process.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: March 28, 2023
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, SMIC New Technology Research and Development (Shanghai) Corporation
    Inventor: Yong Li
  • Patent number: 11605711
    Abstract: A semiconductor device includes an active pattern on a substrate, a source/drain pattern on the active pattern, a channel pattern connected to the source/drain pattern, the channel pattern including semiconductor patterns stacked and spaced apart from each other, a gate electrode extending across the channel pattern, and inner spacers between the gate electrode and the source/drain pattern. The semiconductor patterns include stacked first and second semiconductor patterns. The gate electrode includes first and second portions, which are sequentially stacked between the substrate and the first and second semiconductor patterns, respectively. The inner spacers include first and second air gaps, between the first and second portions of the gate electrode and the source/drain pattern. The largest width of the first air gap is larger than that of the second air gap.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: March 14, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Haejun Yu, Kyungin Choi, Seung Hun Lee
  • Patent number: 11594548
    Abstract: A semiconductor device includes a substrate, a lower structure on the substrate, the lower structure including a first wiring structure, a second wiring structure, and a lower insulating structure covering the first and second wiring structures, a first pattern layer including a plate portion and a via portion, the plate portion being on the lower insulating structure and the via portion extending into the lower insulating structure from a lower portion of the plate portion and overlapping the first wiring structure, a graphene-like carbon material layer in contact with the via portion and the first wiring structure between the via portion and the first wiring structure, gate layers stacked in a vertical direction perpendicular to an upper surface of the substrate and spaced apart from each other on the first pattern layer, and a memory vertical structure penetrating through the gate layers in the vertical direction.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: February 28, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sangmin Kang, Hanvit Yang
  • Patent number: 11594415
    Abstract: Methods of forming a tungsten film comprising forming a boron seed layer on an oxide surface, an optional tungsten initiation layer on the boron seed layer and a tungsten containing film on the boron seed layer or tungsten initiation layer are described. Film stack comprising a boron seed layer on an oxide surface with an optional tungsten initiation layer and a tungsten containing film are also described.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: February 28, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Susmit Singha Roy, Pramit Manna, Rui Cheng, Abhijit Basu Mallick
  • Patent number: 11587876
    Abstract: The present disclosure relates to method for preparing a semiconductor device with a composite landing pad. The method includes forming a first dielectric layer over a semiconductor substrate. The semiconductor device also includes forming a lower metal plug and a barrier layer in the first dielectric layer. The lower metal plug is surrounded by the barrier layer. The semiconductor device further includes forming an inner silicide portion over the lower metal plug, and an outer silicide portion over the barrier layer. A topmost surface of the outer silicide portion is higher than a topmost surface of the inner silicide portion.
    Type: Grant
    Filed: December 15, 2021
    Date of Patent: February 21, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chun-Cheng Liao
  • Patent number: 11569169
    Abstract: Provided is a semiconductor device including electronic components electrically joined to each other via a metal nanoparticle sintered layer, wherein the metal nanoparticle sintered layer has formed therein a metal diffusion region in which a metal constituting a metallization layer formed on a surface of one of the electronic components is diffused, and in which the metal is present in an amount of 10 mass % or more and less than 100 mass % according to TEM-EDS analysis, and wherein the metal diffusion region has a thickness smaller than a thickness of the metallization layer.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: January 31, 2023
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Tsuyoshi Tanigaki
  • Patent number: 11563104
    Abstract: A semiconductor device is provided. The semiconductor device includes a fin protruding from a semiconductor substrate and a gate structure over the fin. The semiconductor device also includes a source region and a drain region in the fin and at opposite sides of the gate structure. The semiconductor device further includes a gate spacer on a sidewall of the gate structure. The gate spacer includes an air-gap spacer and a sealing spacer above the air-gap spacer, an upper portion of the gate structure is laterally overlapping with the sealing spacer, and the bottom portion of the gate structure is laterally overlapping with the air gap spacer.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: January 24, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Hsiung Lin, Pei-Hsun Wang, Chih-Chao Chou, Chia-Hao Chang, Chih-Hao Wang
  • Patent number: 11562963
    Abstract: According to various examples, a stacked semiconductor package is described. The stacked semiconductor package may include a package substrate. The stacked semiconductor package may also include a base die disposed on and electrically coupled to the package substrate. The stacked semiconductor package may further include a mold portion disposed on the package substrate at a periphery of the base die, the mold portion may include a through-mold interconnect electrically coupled to the package substrate. The stacked semiconductor package may further include a semiconductor device having a first section disposed on the base die and a second section disposed on the mold portion, wherein the second section of the semiconductor device may be electrically coupled to the package substrate through the through-mold interconnect.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: January 24, 2023
    Assignee: Intel Corporation
    Inventors: Chin Lee Kuan, Bok Eng Cheah, Jackson Chung Peng Kong, Sameer Shekhar, Amit Jain
  • Patent number: 11532631
    Abstract: A semiconductor device and method for fabricating the semiconductor device, which secure an overlay margin between the storage node and the storage node contact plug, as well as a processing margin, by excluding the connecting structure between the storage node and the storage node contact plug. A semiconductor device comprises a storage node contact hole provided between bit line structures, a first plug filling a lower portion of the storage node contact hole, a second plug protruding from the first plug, an insulation layer spacer covering a side wall of the second plug, and a storage node positioned at a higher level than the second plug and including an extension contacting another side wall of the second plug and a portion of a top surface of the first plug.
    Type: Grant
    Filed: January 19, 2021
    Date of Patent: December 20, 2022
    Assignee: SK hynix Inc.
    Inventor: Se Han Kwon
  • Patent number: 11532552
    Abstract: A first layer is located over a substrate. The first layer includes a first dielectric component and a first conductive component. A first etching stop layer is located over the first dielectric component. A metal capping layer is located over the first conductive component. A second etching stop layer is located over the first etching stop layer and over the metal capping layer. A second layer is located over the second etching stop layer. The second layer includes a second dielectric component and a second conductive component. A third conductive component electrically interconnects the second conductive component to the first conductive component.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: December 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yung-Hsu Wu, Hai-Ching Chen, Jung-Hsun Tsai, Shau-Lin Shue, Tien-I Bao
  • Patent number: 11482495
    Abstract: A method for fabricating a semiconductor arrangement includes removing a portion of a first dielectric layer to form a first recess defined by sidewalls of the first dielectric layer, forming a first conductive layer in the first recess, removing a portion of the first conductive layer to form a second recess defined by the sidewalls of the first dielectric layer, forming a second conductive layer in the second recess, where the second conductive layer contacts the first conductive layer, forming a second dielectric layer over the second conductive layer, removing a portion of the second dielectric layer to form a third recess defined by sidewalls of the second dielectric layer, where the second conductive layer is exposed through the third recess, and forming a third conductive layer in the third recess, where the third conductive layer contacts the second conductive layer.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: October 25, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, ltd.
    Inventors: Pin-Wen Chen, Mei-Hui Fu, Hong-Mao Lee, Wei-Jung Lin, Chih-Wei Chang
  • Patent number: 11450607
    Abstract: A semiconductor device includes a first interlayer insulating film disposed on a substrate and having a first trench. A first lower conductive pattern fills the first trench and includes first and second valley areas that are spaced apart from each other in a first direction parallel to an upper surface of the substrate. The first and second valley areas are recessed toward the substrate. A second interlayer insulating film is disposed on the first interlayer insulating film and includes a second trench that exposes at least a portion of the first lower conductive pattern. An upper conductive pattern fills the second trench and includes an upper barrier film and an upper filling film disposed on the upper barrier film. The upper conductive pattern at least partially fills the first valley area.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: September 20, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seung Yong Yoo, Jong Jin Lee, Rak Hwan Kim, Eun-Ji Jung, Won Hyuk Hong
  • Patent number: 11437276
    Abstract: A method of wafer dicing includes singulating dies from a semiconductor wafer. The method further includes depositing a metal layer on back sides of the singulated dies, wherein a portion of the metal layer continues beyond the backs sides of the singulated dies to deposit at least partially on lateral sides of the singulated dies. A packaged die includes a semiconductor die and a metal outer layer deposited on the back side of the semiconductor die and on a portion of the lateral side of the semiconductor die nearest the back side. The packaged die further includes a substrate mounted to the back side of the semiconductor die a die attach material that bonds the substrate to the metal outer layer deposited on the semiconductor die, wherein the metal outer layer and the die attach material surround the back edge of the semiconductor die.
    Type: Grant
    Filed: July 3, 2020
    Date of Patent: September 6, 2022
    Assignee: NXP USA, Inc.
    Inventors: Jaynal A Molla, Lakshminarayan Viswanathan, David Abdo, Colby Greg Rampley, Fernando A. Santos
  • Patent number: 11437269
    Abstract: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to ammonia vapor in a non-plasma process. Process parameters including exposure time, substrate temperature, and chamber pressure can be used to tune the inhibition profile. Also provided are methods of filling multiple adjacent lines with reduced or no line bending. The methods involve selectively inhibiting the tungsten nucleation to reduce sidewall growth during feature fill.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: September 6, 2022
    Assignee: Novellus Systems, Inc.
    Inventors: Tsung-Han Yang, Anand Chandrashekar, Jasmine Lin
  • Patent number: 11430756
    Abstract: Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a method for forming a semiconductor device is disclosed. A first device layer is formed above a first substrate. A first bonding layer including a first bonding contact is formed above the first device layer. The first bonding contact is made of a first indiffusible conductive material. A second device layer is formed above a second substrate. A second bonding layer including a second bonding contact is formed above the second device layer. The first substrate and the second substrate are bonded in a face-to-face manner, such that the first bonding contact is in contact with the second bonding contact at a bonding interface.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: August 30, 2022
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Zongliang Huo, Jun Liu, Jifeng Zhu, Jun Chen, Zi Qun Hua, Li Hong Xiao
  • Patent number: 11424371
    Abstract: A multi-trench schottky diode includes a semiconductor base layer, a back metal layer, an epitaxial layer, an interlayer dielectric layer, a first metal layer, a passivation layer and a second metal layer. The epitaxial layer on the semiconductor base layer includes a termination trench structure, a first trench structure, a second trench structure and a third trench structure. The dielectric layer is on the epitaxial layer in a termination area. The first metal layer stacked on the termination trench structure and the interlayer dielectric layer extends between the second trench structure and the third trench structure. The passivation layer is on the first metal layer and the interlayer dielectric layer. The second metal layer on the first metal layer and the passivation layer extends to the first trench structure. Thus, the electric field is dispersed and the voltage breakdown can be avoided with the trench structures in the termination area.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: August 23, 2022
    Assignee: TAIWAN SEMICONDUCTOR CO., LTD.
    Inventors: Yi-Lung Tsai, Syed Sarwar Imam, Yao-Wei Chuang, Ming-Lou Tung
  • Patent number: 11417819
    Abstract: An integrated circuit is provided that comprises a first substrate having a plurality of conductive contact pads spaced apart from one another on a surface of the first substrate, a dielectric layer overlying the first substrate and the plurality of conductive contact pads, and a second substrate overlying the dielectric layer. A plurality of superconducting contacts extend through the second substrate and the dielectric layer to the first substrate, wherein each superconducting contact of the plurality of superconducting contacts is aligned with and in contact with a respective conductive contact pad of the plurality of conductive contact pads.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: August 16, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Christopher A. Cantaloube
  • Patent number: 11410885
    Abstract: Methods of forming fully aligned vias connecting two metal lines extending in two directions are described. The fully aligned via is aligned with the first metal line and the second metal line along both directions. A third metal layer is patterned on a top of a second metal layer in electrical contact with a first metal layer. The patterned third metal layer is misaligned from the top of the second metal layer. The second metal layer is recessed to expose sides of the second metal layer and remove portions not aligned sides of the third metal layer.
    Type: Grant
    Filed: May 1, 2020
    Date of Patent: August 9, 2022
    Assignee: APPLIED MATERIALS, INC.
    Inventors: He Ren, Hao Jiang, Mehul Naik
  • Patent number: 11404373
    Abstract: Disclosed are standard cells and methods for fabricating standard cells used in semiconductor device design and fabrication. Aspects disclosed include a standard cell having a plurality of wide metal lines. The wide metal lines being formed from copper. The standard cell also includes a plurality of narrow metal lines. The narrow metal lines are formed from a material that has a lower resistance than copper for line widths on the order of twelve nanometers or less.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: August 2, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Junjing Bao, John Jianhong Zhu, Giridhar Nallapati
  • Patent number: 11398409
    Abstract: A method of forming a BEOL interconnect structure having improved resistance-capacitance is provided in which a via metal layer is created by a first metallization process and thereafter shrunk by a subtractive etch; these steps relax the critical dimension, ensure a via straight profile, avoid via chamfering and bowing, and maximize metal volume. Top trench metallization is then performed above the via metal layer; this step eliminates reactive ion etch lag and ensures no metallization void issues.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: July 26, 2022
    Assignee: International Business Machines Corporation
    Inventors: Yann Mignot, Yongan Xu, Hsueh-Chung Chen
  • Patent number: 11387143
    Abstract: A method includes forming a metal seed layer over a first conductive feature of a wafer, forming a patterned photo resist on the metal seed layer, forming a second conductive feature in an opening in the patterned photo resist, and heating the wafer to generate a gap between the second conductive feature and the patterned photo resist. A protection layer is plated on the second conductive feature. The method further includes removing the patterned photo resist, and etching the metal seed layer.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: July 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Da Cheng, Wen-Hsiung Lu, Chin Wei Kang, Yung-Han Chuang, Lung-Kai Mao, Yung-Sheng Lin
  • Patent number: 11380638
    Abstract: In one embodiment, a semiconductor device includes a substrate, a first interconnection provided above the substrate, and a first pad provided on the first interconnection. The device further includes a second pad provided on the first pad, and a second interconnection provided on the second pad. Furthermore, the first pad includes a first layer provided in a first insulator above the substrate, and a second layer that is provided in the first insulator via the first layer and is in contact with the first interconnection, or the second pad includes a third layer provided in a second insulator above the substrate, and a fourth layer that is provided in the second insulator via the third layer and is in contact with the second interconnection.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: July 5, 2022
    Assignee: Kioxia Corporation
    Inventor: Masayoshi Tagami
  • Patent number: 11373879
    Abstract: A planarization method and a CMP method are provided. The planarization method includes providing a substrate with a first region and a second region having different degrees of hydrophobicity or hydrophilicity and performing a surface treatment to the first region to render the degrees of hydrophobicity or hydrophilicity in proximity to that of the second region. The CMP method includes providing a substrate with a first region and a second region; providing a polishing slurry on the substrate, wherein the polishing slurry and the surface of the first region have a first contact angle, and the polishing slurry and the surface of the first region have a second contact angle; modifying the surface of the first region to make a contact angle difference between the first contact angle and the second contact angle equal to or less than 30 degrees.
    Type: Grant
    Filed: September 12, 2020
    Date of Patent: June 28, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tung-Kai Chen, Ching-Hsiang Tsai, Kao-Feng Liao, Chih-Chieh Chang, Chun-Hao Kung, Fang-I Chih, Hsin-Ying Ho, Chia-Jung Hsu, Hui-Chi Huang, Kei-Wei Chen
  • Patent number: 11362079
    Abstract: A method of forming a bonded assembly includes providing a first semiconductor die containing a first substrate, first semiconductor devices, first dielectric material layers overlying the first semiconductor devices, and first metal interconnect structures, providing a second semiconductor die containing a second substrate, second semiconductor devices, second dielectric material layers overlying the second semiconductor devices, and second metal interconnect structures, depositing a manganese layer on a top surface of the first dielectric material layers, disposing the second semiconductor die on the manganese layer such that a surface of the second dielectric material layers contacts the manganese layer, and performing a bonding anneal to bond the first semiconductor die to the second semiconductor die and to convert the manganese layer into a manganese-containing oxide layer, such that the manganese-containing oxide layer is bonded to the first dielectric material layers and the second dielectric material
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: June 14, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Chen Wu, Peter Rabkin, Masaaki Higashitani
  • Patent number: 11355512
    Abstract: A semiconductor device includes a substrate, a logic circuit provided on the substrate, a wiring layer including a plurality of wirings that are provided above the logic circuit, a first insulating film below the wiring layer, a plug, and a second insulating film. Each of the wirings contains copper and extends along a surface plane of the substrate in a first direction. The wirings are arranged along the surface plane of the substrate in a second direction different from the first direction. The plug extends through the first insulating film in a third direction crossing the first and second directions and is electrically connected to one of the wirings. The plug contains tungsten. The second insulating film is provided between the first insulating film and the plug.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: June 7, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Jun Iijima, Masayoshi Tagami, Masayuki Kitamura, Satoshi Wakatsuki
  • Patent number: 11355390
    Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip may comprise a first metal line disposed over a substrate. A via may be disposed directly over a top of the first metal line and the via may comprise a first lower surface and a second lower surface above the first lower surface. A first dielectric structure may be disposed laterally adjacent to the first metal line and may be disposed along a sidewall of the first metal line. A first protective etch-stop structure may be disposed directly over a top of the first dielectric structure and the first protective etch-stop structure may vertically separate the second lower surface of the via from the top of the first dielectric structure.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: June 7, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shao-Kuan Lee, Hai-Ching Chen, Hsin-Yen Huang, Shau-Lin Shue, Cheng-Chin Lee
  • Patent number: 11348864
    Abstract: Disclosed are redistribution substrates and semiconductor packages including the same. For example, a redistribution substrate including a dielectric pattern, and a first redistribution pattern in the dielectric pattern is provided. The first redistribution pattern may include: a first via part having a first via seed pattern and a first via conductive pattern on the first via seed pattern, and a first wiring part having a first wiring seed pattern and a first wiring conductive pattern, the first wiring part being disposed on the first via part and having a horizontal width that is different from a horizontal width of the first via part. Additionally, the first wiring seed pattern may cover a bottom surface and a sidewall surface of the first wiring conductive pattern, and the first via conductive pattern is directly connected to the first wiring conductive pattern.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: May 31, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seokhyun Lee, Gwangjae Jeon
  • Patent number: 11328993
    Abstract: An embodiment includes a metal interconnect structure, comprising: a dielectric layer disposed on a substrate; an opening in the dielectric layer, wherein the opening has sidewalls and exposes a conductive region of at least one of the substrate and an interconnect line; an adhesive layer, comprising manganese, disposed over the conductive region and on the sidewalls; and a fill material, comprising cobalt, within the opening and on a surface of the adhesion layer. Other embodiments are described herein.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: May 10, 2022
    Assignee: Intel Corporation
    Inventors: Christopher J. Jezewski, Tejaswi K. Indukuri, Ramanan V. Chebiam, Colin T. Carver
  • Patent number: 11322359
    Abstract: After forming a contact opening in a dielectric material layer located over a substrate, a metal liner layer comprising a nitride of an alloy and a metal contact layer comprising the alloy that provides the metal liner layer are deposited in-situ in the contact opening by sputter deposition in a single process and without an air break. Compositions of the metal liner layer and the metal contact layer can be changed by varying gas compositions employed in the sputtering process.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: May 3, 2022
    Assignee: ELPIS TECHNOLOGIES INC.
    Inventors: Praneet Adusumilli, Alexander Reznicek, Oscar van der Straten, Chih-Chao Yang
  • Patent number: RE49365
    Abstract: A structure for radiofrequency applications includes: a support substrate of high-resistivity silicon comprising a lower part and an upper part having undergone a p-type doping to a depth D; a mesoporous trapping layer of silicon formed in the doped upper part of the support substrate. The depth D is less than 1 micron and the trapping layer has a porosity rate of between 20% and 60%.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: January 10, 2023
    Assignee: Soitec
    Inventors: Oleg Kononchuk, William Van Den Daele, Eric Desbonnets