Principal Metal Being Copper (epo) Patents (Class 257/E23.161)
  • Patent number: 12180576
    Abstract: A physical vapor deposition (PVD) target for performing a PVD process is provided. The PVD target includes a backing plate and a target plate coupled to the backing plate. The target plate includes a sputtering source material and a dopant, with the proviso that the dopant is not impurities in the sputtering source material. The sputtering source material includes a diffusion barrier material.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: December 31, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Hsi Wang, Yen-Yu Chen, Yi-Chih Chen, Shih-Wei Bih
  • Patent number: 12148656
    Abstract: In a method of manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, an adhesion enhancement layer is formed on a surface of the first dielectric layer, and a second dielectric layer is formed on the adhesion enhancement layer.
    Type: Grant
    Filed: May 2, 2022
    Date of Patent: November 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsiao-Min Chen, Jyh-Nan Lin, Kai-Shiung Hsu, Ding-I Liu
  • Patent number: 12119304
    Abstract: Structures and methods of forming fine die-to-die interconnect routing are described. In an embodiment, a package includes a package-level RDL than spans across a die set and includes a plurality of die-to-die interconnects connecting contact pads between each die. In an embodiment, the plurality of die-to-die interconnects is embedded within one or more photoimageable organic dielectric layers.
    Type: Grant
    Filed: May 14, 2021
    Date of Patent: October 15, 2024
    Assignee: Apple Inc.
    Inventors: Sanjay Dabral, Zhitao Cao, Kunzhong Hu
  • Patent number: 12113018
    Abstract: A semiconductor device includes a first connection pattern; a bit line disposed over the first connection pattern in a vertical direction; and a bit-line contact pad, disposed in a first layer between the bit line and the first connection pattern to electrically couple the bit line to the first connection pattern, and formed as an island when viewed along the vertical direction. A predetermined number of the bit-line contact pads are spaced apart from each other by a predetermined distance in a first direction, when viewed along the vertical direction.
    Type: Grant
    Filed: March 29, 2023
    Date of Patent: October 8, 2024
    Assignee: SK hynix inc.
    Inventors: Dong Hyuk Kim, Sung Lae Oh, Tae Sung Park, Soo Nam Jung
  • Patent number: 12087668
    Abstract: A semiconductor device includes a first passivation layer over a circuit and. conductive pad over the first passivation layer, wherein the conductive pad is electrically connected to the circuit. A second passivation layer is disposed over the conductive pad and the first passivation layer, and has a first opening and a second opening. The first opening exposes an upper surface of a layer that extends underneath the conductive pad, and the second opening exposes the conductive pad. A first insulating layer is disposed over the second passivation layer and filling the first and second openings. A through substrate via extends through the insulating layer, second passivation layer, passivation layer, and substrate. A side of the through substrate via and the second passivation layer have a gap that is filled with the first insulating layer. A conductive via extends through the first insulating layer and connecting to the conductive pad.
    Type: Grant
    Filed: April 3, 2023
    Date of Patent: September 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsien-Wei Chen, Jie Chen, Ming-Fa Chen
  • Patent number: 12087692
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method thereof, and more particularly to an interlayer dielectric (ILD) layer in a semiconductor device. In one example, the ILD layer is over a substrate and includes a dielectric with a dielectric constant of less than about 3.3 and a hardness of at least about 3 GPa. The semiconductor device also includes an interconnect formed in the ILD layer.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: September 10, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Joung-Wei Liou, Greg Huang
  • Patent number: 12057423
    Abstract: A method of forming a semiconductor device includes: forming an interconnect structure over a substrate; forming a first passivation layer over the interconnect structure; forming a first conductive feature over the first passivation layer and electrically coupled to the interconnect structure; conformally forming a second passivation layer over the first conductive feature and the first passivation layer; forming a dielectric layer over the second passivation layer; and forming a first bump via and a first conductive bump over and electrically coupled to the first conductive feature, where the first bump via is between the first conductive bump and the first conductive feature, where the first bump via extends into the dielectric layer, through the second passivation layer, and contacts the first conductive feature, where the first conductive bump is over the dielectric layer and electrically coupled to the first bump via.
    Type: Grant
    Filed: October 1, 2021
    Date of Patent: August 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ting-Li Yang, Po-Hao Tsai, Ching-Wen Hsiao, Hong-Seng Shue, Ming-Da Cheng
  • Patent number: 12051592
    Abstract: A method includes receiving a structure having a dielectric layer over a conductive feature, wherein the conductive feature includes a second metal. The method further includes etching a hole through the dielectric layer and exposing the conductive feature and depositing a first metal into the hole and in direct contact with the dielectric layer and the conductive feature, wherein the first metal entirely fills the hole. The method further includes annealing the structure such that atoms of the second metal are diffused into grain boundaries of the first metal and into interfaces between the first metal and the dielectric layer. After the annealing, the method further includes performing a chemical mechanical planarization (CMP) process to remove at least a portion of the first metal.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: July 30, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sung-Li Wang, Hung-Yi Huang, Yu-Yun Peng, Mrunal A. Khaderbad, Chia-Hung Chu, Shuen-Shin Liang, Keng-Chu Lin
  • Patent number: 12016183
    Abstract: A memory chip includes a memory cell circuit, a periphery circuit, an interconnect structure, and a control logic circuit. The periphery circuit is positioned under the memory cell circuit and electrically connected to the memory cell circuit. The interconnect structure is positioned on a side surface of the memory cell circuit. The control logic circuit is positioned under the interconnect structure. The control logic circuit is electrically connected to the interconnect structure and the periphery circuit and includes a dynamic random-access memory.
    Type: Grant
    Filed: November 2, 2021
    Date of Patent: June 18, 2024
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventor: Yan-Ru Chen
  • Patent number: 12014987
    Abstract: The present disclosure provides a structure and a method to reduce electro-migration. An interconnect structure according to the present disclosure includes a conductive feature embedded in a dielectric layer, a capping barrier layer disposed over the conductive feature and the dielectric layer, and an adhesion layer sandwiched between the capping barrier layer and the dielectric layer. The adhesion layer includes a degree of crystallinity between about 40% and about 70%.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: June 18, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Chen Ho, Chien Lin, Cheng-Yeh Yu, Hsin-Hsing Chen, Ju Ru Hsieh
  • Patent number: 12009202
    Abstract: A structure is provided that includes a first conductive component and a first interlayer dielectric (ILD) that surrounds the first conductive component. A self-assembly layer is formed on the first conductive component but not on the first ILD. A first dielectric layer is formed over the first ILD but not over the first conductive component. A second ILD is formed over the first conductive component and over the first ILD. An opening is etched in the second ILD. The opening is at least partially aligned with the first conductive component. The first dielectric layer protects portions of the first ILD located therebelow from being etched. The opening is filled with a conductive material to form a second conductive component in the opening.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: June 11, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shao-Kuan Lee, Hsin-Yen Huang, Yung-Hsu Wu, Cheng-Chin Lee, Hai-Ching Chen, Shau-Lin Shue
  • Patent number: 12009301
    Abstract: An interconnect structure is provided. The interconnect structure includes a first via in a first dielectric layer, a first metal line on and electrically connected to the first via, a first etching stop layer over the first dielectric layer, a second metal line over the first etching stop layer, and an encapsulating layer. The encapsulating layer includes a first vertical portion along a sidewall of the first metal line, a horizontal portion along an upper surface of the first etching stop layer, and a second vertical portion along a sidewall of the second metal line. The interconnect structure also includes a second dielectric layer nested within the encapsulating layer.
    Type: Grant
    Filed: January 18, 2022
    Date of Patent: June 11, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shao-Kuan Lee, Cheng-Chin Lee, Hsin-Yen Huang, Hai-Ching Chen, Shau-Lin Shue
  • Patent number: 11935804
    Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.
    Type: Grant
    Filed: April 10, 2023
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Sung Huang, Ming Hung Tseng, Yen-Liang Lin, Hao-Yi Tsai, Chi-Ming Tsai, Chung-Shi Liu, Chih-Wei Lin, Ming-Che Ho
  • Patent number: 11901251
    Abstract: The semiconductor device has the CSP structure and may include a plurality of electrode pads formed on a semiconductor integrated circuit in order to input/output signals from/to exterior; solder bumps for making external lead electrodes; and rewiring. The solder bumps may be arranged in two rows along the periphery of the semiconductor device. The electrode pads may be arranged inside the outermost solder bumps so as to be interposed between the two rows of solder bumps. Each trace of the rewiring may be extended from an electrode pad and may be connected to any one of the outermost solder bumps or any one of the inner solder bumps.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: February 13, 2024
    Assignee: ROHM CO., LTD
    Inventor: Kunihiro Komiya
  • Patent number: 11876017
    Abstract: Integrated circuit devices and methods of forming the same are provided. The methods of forming an integrated circuit device may include forming a first insulating layer and a via contact on a substrate. The substrate may include an upper surface facing the via contact, and the via contact may be in the first insulating layer and may include a lower surface facing the substrate and an upper surface opposite to the lower surface. The methods may also include forming a second insulating layer and a metallic wire on the via contact. The metallic wire may be in the second insulating layer and may include a lower surface that faces the substrate and contacts the upper surface of the via contact. Both the lower surface of the metallic wire and an interface between the metallic wire and the via contact may have a first width in a horizontal direction that is parallel to the upper surface of the substrate.
    Type: Grant
    Filed: December 15, 2021
    Date of Patent: January 16, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae Yong Bae, Hoon Seok Seo, Ki Hyun Park, Hak-Sun Lee
  • Patent number: 11848285
    Abstract: A semiconductor chip, a semiconductor package including the same, and a method of fabricating the same, the semiconductor chip including a substrate that includes a device region and an edge region; a device layer and a wiring layer that are sequentially stacked on the substrate; a subsidiary pattern on the wiring layer on the edge region; a first capping layer that covers a sidewall of the subsidiary pattern, a top surface of the wiring layer, and a sidewall of the wiring layer, the first capping layer including an upper outer sidewall and a lower outer sidewall, the lower outer sidewall being offset from the upper outer sidewall; and a buried dielectric pattern in contact with the lower outer sidewall of the first capping layer and spaced apart from the upper outer sidewall of the first capping layer.
    Type: Grant
    Filed: February 15, 2022
    Date of Patent: December 19, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kwangwuk Park, Youngmin Lee, Inyoung Lee, Sungdong Cho
  • Patent number: 11837542
    Abstract: Integrated circuit (IC) structures, computing devices, and related methods are disclosed. An IC structure includes an interlayer dielectric (ILD), an interconnect, and a liner material separating the interconnect from the ILD. The interconnect includes a first end extending to or into the ILD and a second end opposite the first end. A second portion of the interconnect extending from the second end to a first portion of the interconnect proximate to the first end does not include the liner material thereon. A method of manufacturing an IC structure includes removing an ILD from between interconnects, applying a conformal hermetic liner, applying a carbon hard mask (CHM) between the interconnects, removing a portion of the CHM, removing the conformal hermetic liner to a remaining CHM, and removing the exposed portion of the liner material to the remaining CHM to expose the second portion of the interconnects.
    Type: Grant
    Filed: January 24, 2022
    Date of Patent: December 5, 2023
    Assignee: Intel Corporation
    Inventors: Manish Chandhok, Richard Schenker, Tristan Tronic
  • Patent number: 11798888
    Abstract: A chip packaging structure and a method for preparing the same are disclosed. The method includes: providing a wafer having a first surface and a second surface, forming a first redistribution layer on the first surface, wherein the wafer includes TSVs having first ends exposed from the wafer; forming welding pads electrically connected to the TSVs through the first redistribution layer; forming a trimming groove in an edge area of the wafer; bonding the first surface of the wafer to a first supporting substrate, and thinning the second surface of the wafer to expose the second ends of the TSVs; forming, on the second surface of the wafer, solder balls electrically connected to the TSVs through a second redistribution layer; bonding the second surface of the wafer to a second supporting substrate, and peeling off the first supporting substrate; and connecting the welding pads to a semiconductor chip.
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: October 24, 2023
    Assignee: SJ SEMICONDUCTOR (JIANGYIN) CORPORATION
    Inventors: Yayuan Xue, Xingtao Xue, Chengchung Lin
  • Patent number: 11769770
    Abstract: A semiconductor device includes a substrate, a semiconductor fin, a shallow trench isolation (STI) structure, an air spacer, and a gate structure. The semiconductor fin extends upwardly from the substrate. The STI structure laterally surrounds a lower portion of the semiconductor fin. The air spacer is interposed the STI structure and the semiconductor fin. The gate structure extends across the semiconductor fin.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: September 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Lien Huang, Che-Ming Hsu, Ching-Feng Fu, Huan-Just Lin
  • Patent number: 11764145
    Abstract: A wiring structure includes a filling metal, a cover metal including cobalt (Co) on the filling metal, the cover metal having a first portion along a side surface and along a lower surface of the filling metal, and a second portion along an upper surface of the filling metal, a barrier metal on an outer surface of the first portion of the cover metal, and a capping metal on an outer surface of the second portion of the cover metal, the capping metal including a cobalt (Co) alloy, wherein the filling metal has higher conductivity than the cover metal and the barrier metal.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: September 19, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jaejin Lee, Hana Kim, Jaewha Park, Dongchan Lim
  • Patent number: 11735468
    Abstract: Back end of line metallization structures and methods for fabricating self-aligned vias. The structures generally include a first interconnect structure disposed above a substrate. The first interconnect structure includes a metal line formed in a first interlayer dielectric. A second interconnect structure overlies the first interconnect structure. The second interconnect structure includes a second cap layer on the first interlayer dielectric, a second interlayer dielectric thereon, and at least one self-aligned via in the second interlayer dielectric conductively coupled to at least a portion of the metal line of the first interconnect structure, wherein any misalignment of the at least one self-aligned via results in the at least one self-aligned via landing on both the metal line of the first interconnect structure and the second cap layer. The second cap layer is an insulating material.
    Type: Grant
    Filed: December 3, 2021
    Date of Patent: August 22, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chih-Chao Yang, Terry A. Spooner, Koichi Motoyama, Shyng-Tsong Chen
  • Patent number: 11735615
    Abstract: An imaging device including: a photoelectric converter; a protection member provided on a light incidence side of the photoelectric converter; a substrate opposed to the protection member with the photoelectric converter interposed therebetween and having a first surface on the photoelectric converter side and a second surface opposed to the first surface; a rewiring layer provided in a selective region of the second surface of the substrate; and a protective resin layer provided on the second surface of the substrate, the second surface of the substrate having an external terminal coupling region exposed from the protective resin layer, and a stress relaxation region exposed from the protective resin layer and disposed at a position different from the external terminal coupling region.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: August 22, 2023
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Yoshiaki Masuda, Tokihisa Kaneguchi
  • Patent number: 11728295
    Abstract: In a method of manufacturing a semiconductor device, an opening is formed in a first dielectric layer so that a part of a lower conductive layer is exposed at a bottom of the opening, one or more liner conductive layers are formed over the part of the lower conductive layer, an inner sidewall of the opening and an upper surface of the first dielectric layer, a main conductive layer is formed over the one or more liner conductive layers, a patterned conductive layer is formed by patterning the main conductive layer and the one or more liner conductive layers, and a cover conductive layer is formed over the patterned conductive layer. The main conductive layer which is patterned is wrapped around by the cover conductive layer and one of the one or more liner conductive layers.
    Type: Grant
    Filed: July 6, 2021
    Date of Patent: August 15, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Chieh Hsiao, Hsiang-Ku Shen, Yuan-Yang Hsiao, Ying-Yao Lai, Dian-Hau Chen
  • Patent number: 11725270
    Abstract: A physical vapor deposition (PVD) target for performing a PVD process is provided. The PVD target includes a backing plate and a target plate coupled to the backing plate. The target plate includes a sputtering source material and a dopant, with the proviso that the dopant is not impurities in the sputtering source material. The sputtering source material includes a diffusion barrier material.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: August 15, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Hsi Wang, Yen-Yu Chen, Yi-Chih Chen, Shih Wei Bih
  • Patent number: 11532661
    Abstract: A semiconductor device includes a first semiconductor chip including a first substrate, a plurality of first dielectric layers and a plurality of conductive lines formed in the first dielectric layers over the first substrate. The semiconductor device further includes a second semiconductor chip having a surface bonded to a first surface of the first semiconductor chip, the second semiconductor chip including a second substrate, a plurality of second dielectric layers and a plurality of second conductive lines formed in the second dielectric layers over the second substrate. The semiconductor device further includes a first conductive feature extending from the first semiconductor chip to one of the plurality of second conductive lines, and a first seal ring structure extending from the first semiconductor chip to the second semiconductor chip.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: December 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Ying Ho, Pao-Tung Chen, Wen-De Wang, Jen-Cheng Liu, Dun-Nian Yaung
  • Patent number: 11527512
    Abstract: The present application discloses a method for fabricating a semiconductor device. The method includes providing a first semiconductor structure; and forming a first connecting structure comprising a first connecting insulating layer on the first semiconductor structure, two first conductive layers in the first connecting insulating layer, and a first porous layer between the two first conductive layers; wherein a porosity of the first porous layer is between about 25% and about 100%.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: December 13, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Tse-Yao Huang
  • Patent number: 11527411
    Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a conductive plug over a substrate; a conductive feature over the conductive plug, wherein the conductive feature has a first sidewall, a second sidewall facing the first sidewall, and a bottom surface; and a carbon-containing barrier layer having a first portion along the first sidewall of the conductive feature, a second portion along the second sidewall of the conductive feature, and a third portion along the bottom surface of the conductive feature.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: December 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
    Inventors: Rueijer Lin, Ya-Lien Lee, Chun-Chieh Lin, Hung-Wen Su
  • Patent number: 9024322
    Abstract: Provided is a technique that allows oxidation of Cu wires to be effectively prevented during plasma processing when forming a passivation film for a display device that utilizes an oxide semiconductor layer. This wiring structure comprises a semiconductor layer (oxide semiconductor) for a thin film transistor, a Cu alloy film (laminated structure comprising a first layer (X) and a second layer (Z)), and a passivation film that are formed on a substrate, starting from the substrate side. The first layer (X) is made of an element that exhibits low electrical resistivity, such as pure Cu; and the second layer contains a plasma-oxidation-resistance improving element. The second layer (Z) is directly connected, at least partially, to the passivation film.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: May 5, 2015
    Assignee: Kobe Steel, Ltd.
    Inventors: Aya Miki, Toshihiro Kugimiya
  • Patent number: 8999839
    Abstract: A method of manufacturing a semiconductor structure, the method includes removing a portion of a dielectric filler from a first metal-containing layer formed over a semiconductor substrate to define an air-gap region according to a predetermined air-gap pattern. The method further includes filling the air-gap region with a decomposable filler and forming a dielectric capping layer over the first metal-containing layer. The method further includes decomposing the decomposable filler.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: April 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Hui Su, Cheng-Lin Huang, Jiing-Feng Yang, Zhen-Cheng Wu, Ren-Guei Wu, Dian-Hau Chen, Yuh-Jier Mii
  • Patent number: 8993435
    Abstract: In the formation of an interconnect structure, a metal feature is formed in a dielectric layer. An etch stop layer (ESL) is formed over the metal feature and the dielectric layer using a precursor and a carbon-source gas including carbon as precursors. The carbon-source gas is free from carbon dioxide (CO2). The precursor is selected from the group consisting essentially of 1-methylsilane (1MS), 2-methylsilane (2MS), 3-methylsilane (3MS), 4-methylsilane (4MS), and combinations thereof.
    Type: Grant
    Filed: March 15, 2010
    Date of Patent: March 31, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Chen Wang, Po-Cheng Shih, Chung-Chi Ko, Keng-Chu Lin, Shwang-Ming Jeng
  • Patent number: 8975749
    Abstract: A method of making a semiconductor device includes forming a dielectric layer over a semiconductor substrate. The method further includes forming a copper-containing layer in the dielectric layer, wherein the copper-containing layer has a first portion and a second portion. The method further includes forming a first barrier layer between the first portion of the copper-containing layer and the dielectric layer. The method further includes forming a second barrier layer at a boundary between the second portion of the copper-containing layer and the dielectric layer wherein the second barrier layer is adjacent to an exposed portion of the dielectric layer. The first barrier layer is a dielectric layer, and the second barrier layer is a metal oxide layer, and a boundary between a sidewall of the copper-containing layer and the first barrier layer is free of the second barrier layer.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: March 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Nai-Wei Liu, Zhen-Cheng Wu, Cheng-Lin Huang, Po-Hsiang Huang, Yung-Chih Wang, Shu-Hui Su, Dian-Hau Chen, Yuh-Jier Mii
  • Patent number: 8970027
    Abstract: One aspect of the present invention is a method of processing a substrate. In one embodiment, the method comprises forming an electrical conductor on or in the substrate by providing a mixture comprising metal particles and an electroless deposition solution and electrolessly depositing a metal matrix and co-depositing the metal particles. In another embodiment, the method comprises forming an electrical conductor on or in the substrate by providing a mixture comprising metal particles and an electrochemical plating solution and electrochemically plating a metal matrix and co-depositing the metal particles. Another aspect of the present invention is a mixture for the formation of an electrical conductor on or in a substrate. Another aspect of the present invention is an electronic device.
    Type: Grant
    Filed: August 10, 2013
    Date of Patent: March 3, 2015
    Assignee: Lam Research Corporation
    Inventors: Artur Kolics, Fritz Redeker
  • Patent number: 8962473
    Abstract: In a method of fabricating a semiconductor device, an opening is formed inside a dielectric layer above a semiconductor substrate. The opening has a wall. At least one diffusion barrier material is then formed over the wall of the opening by at least two alternating steps, which are selected from the group consisting of a process of physical vapor deposition (PVD) and a process of atomic layer deposition (ALD). A liner layer is formed over the at least one diffusion barrier material.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kai-Shiang Kuo, Ken-Yu Chang, Ya-Lien Lee, Hung-Wen Su
  • Patent number: 8946895
    Abstract: A semiconductor device having Cu wiring including a basic crystal structure which can reduce surface voids, and an inspecting technique for the semiconductor device. In the semiconductor device, surface voids can be reduced down to 1/10 or less of a current practical level by specifying a barrier layer and a seed layer and setting a proportion (frequency) of occupation of a coincidence site lattice (CSL) boundary having a grain boundary Sigma value 27 or less to all crystal grain boundaries of a Cu wiring to 60% or higher. Alternatively, a similar effect of surface void reduction can be obtained by specifying a barrier layer and a seed layer and setting a proportion (frequency) of occupation of a coincidence site lattice (CSL) boundary having a grain boundary Sigma value 3 to all crystal grain boundaries of a Cu wiring to 40% or higher.
    Type: Grant
    Filed: February 20, 2009
    Date of Patent: February 3, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Takahiko Kato, Hiroshi Nakano, Haruo Akahoshi, Yuuji Takada, Yoshimi Sudo, Tetsuo Fujiwara, Itaru Kanno, Tomoryo Shono, Yukinori Hirose
  • Patent number: 8937009
    Abstract: Disclosed are a method for metallization during semiconductor wafer processing and the resulting structures. In this method, a passivation layer is patterned with first openings aligned above and extending vertically to metal structures below. A mask layer is formed and patterned with second openings aligned above the first openings, thereby forming two-tier openings extending vertically through the mask layer and passivation layer to the metal structures below. An electrodeposition process forms, in the two-tier openings, both under-bump pad(s) and additional metal feature(s), which are different from the under-bump pad(s) (e.g., a wirebond pad; a final vertical section of a crackstop structure; and/or a probe pad). Each under-bump pad and additional metal feature initially comprises copper with metal cap layers thereon.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: January 20, 2015
    Assignee: International Business Machines Corporation
    Inventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Karen P. McLaughlin, Ekta Misra, Christopher D. Muzzy, Eric D. Perfecto, Wolfgang Sauter
  • Patent number: 8912041
    Abstract: A method for forming an interconnect structure includes forming a dielectric material layer on a semiconductor substrate. An oxygen-rich layer is formed over the dielectric material layer. The dielectric material layer and the oxygen-rich layer are patterned to form a plurality of vias in the semiconductor substrate. A barrier layer is formed in the plurality of vias and on the dielectric material layer leaving a portion of the oxygen-rich layer exposed. A metal layer is formed on the barrier layer and on the exposed portion of the oxygen-rich layer, wherein the metal layer fills the plurality of vias. The semiconductor substrate is annealed at a predetermined temperature range and at a predetermined pressure to transform the exposed portion of the oxygen-rich layer into a metal-oxide stop layer.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: December 16, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Hsien Peng, Hsiang-Huan Lee, Shau-Lin Shue
  • Patent number: 8872341
    Abstract: One or more embodiments relate to a method of forming a semiconductor device, comprising: forming a structure, the structure including at least a first element and a second element; and forming a passivation layer over the structure, the passivation layer including at least the first element and the second element, the first element and the second element of the passivation layer coming from the structure.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: October 28, 2014
    Assignee: Infineon Technologies AG
    Inventors: Gerald Dallmann, Heike Rosslau, Norbert Urbansky, Scott Wallace
  • Patent number: 8866298
    Abstract: A semiconductor component includes a semiconductor die and a copper-containing electrical conductor. The semiconductor die has a semiconductor device region, an aluminum-containing metal layer on the semiconductor device region, and at least one additional metal layer on the aluminum-containing metal layer which is harder than the aluminum-containing metal layer. The copper-containing electrical conductor is bonded to the at least one additional metal layer of the semiconductor die via an electrically conductive coating of the copper-containing electrical conductor which is softer than the copper of the copper-containing electrical conductor.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: October 21, 2014
    Assignee: Infineon Technologies AG
    Inventor: Reinhold Bayerer
  • Patent number: 8860221
    Abstract: Provided are electrode-connecting structures or semiconductor devices, including a lower device including a lower substrate, a lower insulating layer formed on the lower substrate, and a lower electrode structure formed in the lower insulating layer, wherein the lower electrode structure includes a lower electrode barrier layer and a lower metal electrode formed on the lower electrode barrier layer, and an upper device including an upper substrate, an upper insulating layer formed under the upper substrate, and an upper electrode structure formed in the upper insulating layer, wherein the upper electrode structure includes an upper electrode barrier layer extending from the inside of the upper insulating layer under a bottom surface thereof and an upper metal electrode formed on the upper electrode barrier layer. The lower metal electrode is in direct contact with the upper metal electrode.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: October 14, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kun-Sang Park, Byung-Lyul Park, Su-Kyoung Kim, Kwang-Jin Moon, Suk-Chul Bang, Do-Sun Lee, Dong-Chan Lim, Gil-Heyun Choi
  • Patent number: 8836116
    Abstract: The embodiments of methods and structures for forming through silicon vias a CMOS substrate bonded to a MEMS substrate and a capping substrate provide mechanisms for integrating CMOS and MEMS devices that use less real-estate and are more reliable. The through silicon vias electrically connect to metal-1 level of the CMOS devices. Copper metal may be plated on a barrier/Cu-seed layer to partially fill the through silicon vias, which saves time and cost. The formation method may involve using dual dielectric layers on the substrate surface as etching mask to eliminate a photolithographical process during the removal of oxide layer at the bottoms of through silicon vias. In some embodiments, the through silicon vias land on polysilicon gate structures to prevent notch formation during etching of the vias.
    Type: Grant
    Filed: November 11, 2010
    Date of Patent: September 16, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsueh-An Yang
  • Patent number: 8829681
    Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: September 9, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kenichi Watanabe
  • Patent number: 8786087
    Abstract: A semiconductor device is made up of a first insulating layer having a through hole; a first interconnection which includes a first conductive layer, a first barrier layer, and a first main interconnection, and a second interconnection connected to one of the first conductive layer and the first barrier layer. Accordingly, the semiconductor device can avoid a problem where the material of the first main interconnection transfers from a portion connected to the second interconnection due to electromigration to form a void, with the result that the first interconnection is disconnected from the second interconnection.
    Type: Grant
    Filed: July 2, 2010
    Date of Patent: July 22, 2014
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Yusuke Harada
  • Patent number: 8779596
    Abstract: Disclosed structures and methods inhibit atomic migration and related capacitive-resistive effects between a metallization layer and an insulator layer in a semiconductor structure. One exemplary structure includes an inhibiting layer between an insulator and a metallization layer. The insulator includes a polymer or an insulating oxide compound. And, the inhibiting layer has a compound formed from a reaction between the polymer or insulating oxide compound and a transition metal, a representative metal, or a metalloid.
    Type: Grant
    Filed: May 26, 2004
    Date of Patent: July 15, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Paul A. Farrar
  • Patent number: 8754520
    Abstract: A microelectronic substrate which includes a dielectric layer overlying a semiconductor region of a substrate, the dielectric layer having an exposed top surface; a plurality of metal lines of a first metal disposed within the dielectric layer, each metal line having edges and a surface exposed at the top surface of the dielectric layer; a dielectric cap layer having a first portion overlying the surfaces of the metal lines and a second portion overlying the dielectric layer between the metal lines, the first portion has a first height above the surface of the dielectric layer, and the second portion has a second height above the surface of the dielectric layer, the second height being greater than the first height; and an air gap disposed between the metal lines, the air gap underlying the second portion of the cap layer.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: June 17, 2014
    Assignee: International Business Machines Corporation
    Inventors: Takeshi Nogami, Shyng-Tsong Chen, David V. Horak, Son V. Nguyen, Shom Ponoth, Chih-Chao Yang
  • Patent number: 8749066
    Abstract: Some embodiments include semiconductor processing methods in which a copper barrier is formed to be laterally offset from a copper component, and in which nickel is formed to extend across both the barrier and the component. The barrier may extend around an entire lateral periphery of the component, and may be spaced from the component by an intervening ring of electrically insulative material. The copper component may be a bond pad or an interconnect between two levels of metal layers. Some embodiments include semiconductor constructions in which nickel extends across a copper component, a copper barrier is laterally offset from the copper component, and an insulative material is between the copper barrier and the copper component.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: June 10, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Tianhong Zhang, Akram Ditali
  • Patent number: 8729702
    Abstract: A trench is opened in a dielectric layer. The trench is then lined with a barrier layer and a metal seed layer. The metal seed layer is non-uniformly doped and exhibits a vertical doping gradient varying as a function of trench depth. The lined trench is then filled with a metal fill material. A dielectric cap layer is then deposited over the metal filled trench. Dopant from the non-uniformly doped metal seed layer is then migrated to an interface between the metal filled trench and the dielectric cap layer to form a self-aligned metal cap.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: May 20, 2014
    Assignees: STMicroelectronics, Inc., International Business Machines Corporation
    Inventors: Chengyu Niu, Andrew Simon, Keith Kwong Hon Wong, Yun-Yu Wang
  • Patent number: 8729701
    Abstract: The invention concerns a method of forming a copper portion surrounded by an insulating material in an integrated circuit structure, the insulating material being a first oxide, the method having steps including forming a composite material over a region of the insulating material where the copper portion is to be formed, the composite material having first and second materials, annealing such that the second material reacts with the insulating material to form a second oxide that provides a diffusion barrier to copper; and depositing a copper layer over the composite material by electrochemical deposition to form the copper portion.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: May 20, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Nicolas Jourdan, Joaquin Torres
  • Patent number: 8710659
    Abstract: A semiconductor device includes an interlayer dielectric film, a passivation film, made of an insulating material, formed on the interlayer dielectric film, an uppermost wire, made of a material mainly composed of copper, formed between the surface of the interlayer dielectric film and the passivation film, and a wire covering film, made of a material mainly composed of aluminum, interposed between the passivation film and the surface of the uppermost wire for covering the surface of the uppermost wire.
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: April 29, 2014
    Assignee: Rohm Co., Ltd.
    Inventors: Kei Moriyama, Shuichi Tamaki, Shuichi Sako, Mitsuhide Kori, Junji Goto, Tatsuya Sawada
  • Patent number: 8703615
    Abstract: Disclosed are methods of depositing and annealing a copper seed layer. A copper seed layer may be deposited on a ruthenium layer disposed on a surface of a wafer and on features in the wafer. The thickness of the ruthenium layer may be about 40 Angstroms or less. The copper seed layer may be annealed in a reducing atmosphere having an oxygen concentration of about 2 parts per million or less. Annealing the copper seed layer in a low-oxygen atmosphere may improve the properties of the copper seed layer.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: April 22, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Thomas A. Ponnuswamy, John H. Sukamto, Jonathan D. Reid, Steven T. Mayer, Huanfeng Zhu
  • Patent number: 8669182
    Abstract: An interconnect structure is provided that has enhanced electromigration reliability without degrading circuit short yield, and improved technology extendibility. The inventive interconnect structure includes a dielectric material having a dielectric constant of about 3.0 or less. The dielectric material has at least one conductive material embedded therein. A noble metal cap is located directly on an upper surface of the at least one conductive region. The noble metal cap does not substantially extend onto an upper surface of the dielectric material that is adjacent to the at least one conductive region, and the noble cap material does not be deposited on the dielectric surface. A method fabricating such an interconnect structure utilizing a low temperature (about 300° C. or less) chemical deposition process is also provided.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: March 11, 2014
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Daniel C. Edelstein