Principal Metal Being Copper (epo) Patents (Class 257/E23.161)
  • Patent number: 9024322
    Abstract: Provided is a technique that allows oxidation of Cu wires to be effectively prevented during plasma processing when forming a passivation film for a display device that utilizes an oxide semiconductor layer. This wiring structure comprises a semiconductor layer (oxide semiconductor) for a thin film transistor, a Cu alloy film (laminated structure comprising a first layer (X) and a second layer (Z)), and a passivation film that are formed on a substrate, starting from the substrate side. The first layer (X) is made of an element that exhibits low electrical resistivity, such as pure Cu; and the second layer contains a plasma-oxidation-resistance improving element. The second layer (Z) is directly connected, at least partially, to the passivation film.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: May 5, 2015
    Assignee: Kobe Steel, Ltd.
    Inventors: Aya Miki, Toshihiro Kugimiya
  • Patent number: 8999839
    Abstract: A method of manufacturing a semiconductor structure, the method includes removing a portion of a dielectric filler from a first metal-containing layer formed over a semiconductor substrate to define an air-gap region according to a predetermined air-gap pattern. The method further includes filling the air-gap region with a decomposable filler and forming a dielectric capping layer over the first metal-containing layer. The method further includes decomposing the decomposable filler.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: April 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Hui Su, Cheng-Lin Huang, Jiing-Feng Yang, Zhen-Cheng Wu, Ren-Guei Wu, Dian-Hau Chen, Yuh-Jier Mii
  • Patent number: 8993435
    Abstract: In the formation of an interconnect structure, a metal feature is formed in a dielectric layer. An etch stop layer (ESL) is formed over the metal feature and the dielectric layer using a precursor and a carbon-source gas including carbon as precursors. The carbon-source gas is free from carbon dioxide (CO2). The precursor is selected from the group consisting essentially of 1-methylsilane (1MS), 2-methylsilane (2MS), 3-methylsilane (3MS), 4-methylsilane (4MS), and combinations thereof.
    Type: Grant
    Filed: March 15, 2010
    Date of Patent: March 31, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Chen Wang, Po-Cheng Shih, Chung-Chi Ko, Keng-Chu Lin, Shwang-Ming Jeng
  • Patent number: 8975749
    Abstract: A method of making a semiconductor device includes forming a dielectric layer over a semiconductor substrate. The method further includes forming a copper-containing layer in the dielectric layer, wherein the copper-containing layer has a first portion and a second portion. The method further includes forming a first barrier layer between the first portion of the copper-containing layer and the dielectric layer. The method further includes forming a second barrier layer at a boundary between the second portion of the copper-containing layer and the dielectric layer wherein the second barrier layer is adjacent to an exposed portion of the dielectric layer. The first barrier layer is a dielectric layer, and the second barrier layer is a metal oxide layer, and a boundary between a sidewall of the copper-containing layer and the first barrier layer is free of the second barrier layer.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: March 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Nai-Wei Liu, Zhen-Cheng Wu, Cheng-Lin Huang, Po-Hsiang Huang, Yung-Chih Wang, Shu-Hui Su, Dian-Hau Chen, Yuh-Jier Mii
  • Patent number: 8970027
    Abstract: One aspect of the present invention is a method of processing a substrate. In one embodiment, the method comprises forming an electrical conductor on or in the substrate by providing a mixture comprising metal particles and an electroless deposition solution and electrolessly depositing a metal matrix and co-depositing the metal particles. In another embodiment, the method comprises forming an electrical conductor on or in the substrate by providing a mixture comprising metal particles and an electrochemical plating solution and electrochemically plating a metal matrix and co-depositing the metal particles. Another aspect of the present invention is a mixture for the formation of an electrical conductor on or in a substrate. Another aspect of the present invention is an electronic device.
    Type: Grant
    Filed: August 10, 2013
    Date of Patent: March 3, 2015
    Assignee: Lam Research Corporation
    Inventors: Artur Kolics, Fritz Redeker
  • Patent number: 8962473
    Abstract: In a method of fabricating a semiconductor device, an opening is formed inside a dielectric layer above a semiconductor substrate. The opening has a wall. At least one diffusion barrier material is then formed over the wall of the opening by at least two alternating steps, which are selected from the group consisting of a process of physical vapor deposition (PVD) and a process of atomic layer deposition (ALD). A liner layer is formed over the at least one diffusion barrier material.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kai-Shiang Kuo, Ken-Yu Chang, Ya-Lien Lee, Hung-Wen Su
  • Patent number: 8946895
    Abstract: A semiconductor device having Cu wiring including a basic crystal structure which can reduce surface voids, and an inspecting technique for the semiconductor device. In the semiconductor device, surface voids can be reduced down to 1/10 or less of a current practical level by specifying a barrier layer and a seed layer and setting a proportion (frequency) of occupation of a coincidence site lattice (CSL) boundary having a grain boundary Sigma value 27 or less to all crystal grain boundaries of a Cu wiring to 60% or higher. Alternatively, a similar effect of surface void reduction can be obtained by specifying a barrier layer and a seed layer and setting a proportion (frequency) of occupation of a coincidence site lattice (CSL) boundary having a grain boundary Sigma value 3 to all crystal grain boundaries of a Cu wiring to 40% or higher.
    Type: Grant
    Filed: February 20, 2009
    Date of Patent: February 3, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Takahiko Kato, Hiroshi Nakano, Haruo Akahoshi, Yuuji Takada, Yoshimi Sudo, Tetsuo Fujiwara, Itaru Kanno, Tomoryo Shono, Yukinori Hirose
  • Patent number: 8937009
    Abstract: Disclosed are a method for metallization during semiconductor wafer processing and the resulting structures. In this method, a passivation layer is patterned with first openings aligned above and extending vertically to metal structures below. A mask layer is formed and patterned with second openings aligned above the first openings, thereby forming two-tier openings extending vertically through the mask layer and passivation layer to the metal structures below. An electrodeposition process forms, in the two-tier openings, both under-bump pad(s) and additional metal feature(s), which are different from the under-bump pad(s) (e.g., a wirebond pad; a final vertical section of a crackstop structure; and/or a probe pad). Each under-bump pad and additional metal feature initially comprises copper with metal cap layers thereon.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: January 20, 2015
    Assignee: International Business Machines Corporation
    Inventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Karen P. McLaughlin, Ekta Misra, Christopher D. Muzzy, Eric D. Perfecto, Wolfgang Sauter
  • Patent number: 8912041
    Abstract: A method for forming an interconnect structure includes forming a dielectric material layer on a semiconductor substrate. An oxygen-rich layer is formed over the dielectric material layer. The dielectric material layer and the oxygen-rich layer are patterned to form a plurality of vias in the semiconductor substrate. A barrier layer is formed in the plurality of vias and on the dielectric material layer leaving a portion of the oxygen-rich layer exposed. A metal layer is formed on the barrier layer and on the exposed portion of the oxygen-rich layer, wherein the metal layer fills the plurality of vias. The semiconductor substrate is annealed at a predetermined temperature range and at a predetermined pressure to transform the exposed portion of the oxygen-rich layer into a metal-oxide stop layer.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: December 16, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Hsien Peng, Hsiang-Huan Lee, Shau-Lin Shue
  • Patent number: 8872341
    Abstract: One or more embodiments relate to a method of forming a semiconductor device, comprising: forming a structure, the structure including at least a first element and a second element; and forming a passivation layer over the structure, the passivation layer including at least the first element and the second element, the first element and the second element of the passivation layer coming from the structure.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: October 28, 2014
    Assignee: Infineon Technologies AG
    Inventors: Gerald Dallmann, Heike Rosslau, Norbert Urbansky, Scott Wallace
  • Patent number: 8866298
    Abstract: A semiconductor component includes a semiconductor die and a copper-containing electrical conductor. The semiconductor die has a semiconductor device region, an aluminum-containing metal layer on the semiconductor device region, and at least one additional metal layer on the aluminum-containing metal layer which is harder than the aluminum-containing metal layer. The copper-containing electrical conductor is bonded to the at least one additional metal layer of the semiconductor die via an electrically conductive coating of the copper-containing electrical conductor which is softer than the copper of the copper-containing electrical conductor.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: October 21, 2014
    Assignee: Infineon Technologies AG
    Inventor: Reinhold Bayerer
  • Patent number: 8860221
    Abstract: Provided are electrode-connecting structures or semiconductor devices, including a lower device including a lower substrate, a lower insulating layer formed on the lower substrate, and a lower electrode structure formed in the lower insulating layer, wherein the lower electrode structure includes a lower electrode barrier layer and a lower metal electrode formed on the lower electrode barrier layer, and an upper device including an upper substrate, an upper insulating layer formed under the upper substrate, and an upper electrode structure formed in the upper insulating layer, wherein the upper electrode structure includes an upper electrode barrier layer extending from the inside of the upper insulating layer under a bottom surface thereof and an upper metal electrode formed on the upper electrode barrier layer. The lower metal electrode is in direct contact with the upper metal electrode.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: October 14, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kun-Sang Park, Byung-Lyul Park, Su-Kyoung Kim, Kwang-Jin Moon, Suk-Chul Bang, Do-Sun Lee, Dong-Chan Lim, Gil-Heyun Choi
  • Patent number: 8836116
    Abstract: The embodiments of methods and structures for forming through silicon vias a CMOS substrate bonded to a MEMS substrate and a capping substrate provide mechanisms for integrating CMOS and MEMS devices that use less real-estate and are more reliable. The through silicon vias electrically connect to metal-1 level of the CMOS devices. Copper metal may be plated on a barrier/Cu-seed layer to partially fill the through silicon vias, which saves time and cost. The formation method may involve using dual dielectric layers on the substrate surface as etching mask to eliminate a photolithographical process during the removal of oxide layer at the bottoms of through silicon vias. In some embodiments, the through silicon vias land on polysilicon gate structures to prevent notch formation during etching of the vias.
    Type: Grant
    Filed: November 11, 2010
    Date of Patent: September 16, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsueh-An Yang
  • Patent number: 8829681
    Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: September 9, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kenichi Watanabe
  • Patent number: 8786087
    Abstract: A semiconductor device is made up of a first insulating layer having a through hole; a first interconnection which includes a first conductive layer, a first barrier layer, and a first main interconnection, and a second interconnection connected to one of the first conductive layer and the first barrier layer. Accordingly, the semiconductor device can avoid a problem where the material of the first main interconnection transfers from a portion connected to the second interconnection due to electromigration to form a void, with the result that the first interconnection is disconnected from the second interconnection.
    Type: Grant
    Filed: July 2, 2010
    Date of Patent: July 22, 2014
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Yusuke Harada
  • Patent number: 8779596
    Abstract: Disclosed structures and methods inhibit atomic migration and related capacitive-resistive effects between a metallization layer and an insulator layer in a semiconductor structure. One exemplary structure includes an inhibiting layer between an insulator and a metallization layer. The insulator includes a polymer or an insulating oxide compound. And, the inhibiting layer has a compound formed from a reaction between the polymer or insulating oxide compound and a transition metal, a representative metal, or a metalloid.
    Type: Grant
    Filed: May 26, 2004
    Date of Patent: July 15, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Paul A. Farrar
  • Patent number: 8754520
    Abstract: A microelectronic substrate which includes a dielectric layer overlying a semiconductor region of a substrate, the dielectric layer having an exposed top surface; a plurality of metal lines of a first metal disposed within the dielectric layer, each metal line having edges and a surface exposed at the top surface of the dielectric layer; a dielectric cap layer having a first portion overlying the surfaces of the metal lines and a second portion overlying the dielectric layer between the metal lines, the first portion has a first height above the surface of the dielectric layer, and the second portion has a second height above the surface of the dielectric layer, the second height being greater than the first height; and an air gap disposed between the metal lines, the air gap underlying the second portion of the cap layer.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: June 17, 2014
    Assignee: International Business Machines Corporation
    Inventors: Takeshi Nogami, Shyng-Tsong Chen, David V. Horak, Son V. Nguyen, Shom Ponoth, Chih-Chao Yang
  • Patent number: 8749066
    Abstract: Some embodiments include semiconductor processing methods in which a copper barrier is formed to be laterally offset from a copper component, and in which nickel is formed to extend across both the barrier and the component. The barrier may extend around an entire lateral periphery of the component, and may be spaced from the component by an intervening ring of electrically insulative material. The copper component may be a bond pad or an interconnect between two levels of metal layers. Some embodiments include semiconductor constructions in which nickel extends across a copper component, a copper barrier is laterally offset from the copper component, and an insulative material is between the copper barrier and the copper component.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: June 10, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Tianhong Zhang, Akram Ditali
  • Patent number: 8729702
    Abstract: A trench is opened in a dielectric layer. The trench is then lined with a barrier layer and a metal seed layer. The metal seed layer is non-uniformly doped and exhibits a vertical doping gradient varying as a function of trench depth. The lined trench is then filled with a metal fill material. A dielectric cap layer is then deposited over the metal filled trench. Dopant from the non-uniformly doped metal seed layer is then migrated to an interface between the metal filled trench and the dielectric cap layer to form a self-aligned metal cap.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: May 20, 2014
    Assignees: STMicroelectronics, Inc., International Business Machines Corporation
    Inventors: Chengyu Niu, Andrew Simon, Keith Kwong Hon Wong, Yun-Yu Wang
  • Patent number: 8729701
    Abstract: The invention concerns a method of forming a copper portion surrounded by an insulating material in an integrated circuit structure, the insulating material being a first oxide, the method having steps including forming a composite material over a region of the insulating material where the copper portion is to be formed, the composite material having first and second materials, annealing such that the second material reacts with the insulating material to form a second oxide that provides a diffusion barrier to copper; and depositing a copper layer over the composite material by electrochemical deposition to form the copper portion.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: May 20, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Nicolas Jourdan, Joaquin Torres
  • Patent number: 8710659
    Abstract: A semiconductor device includes an interlayer dielectric film, a passivation film, made of an insulating material, formed on the interlayer dielectric film, an uppermost wire, made of a material mainly composed of copper, formed between the surface of the interlayer dielectric film and the passivation film, and a wire covering film, made of a material mainly composed of aluminum, interposed between the passivation film and the surface of the uppermost wire for covering the surface of the uppermost wire.
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: April 29, 2014
    Assignee: Rohm Co., Ltd.
    Inventors: Kei Moriyama, Shuichi Tamaki, Shuichi Sako, Mitsuhide Kori, Junji Goto, Tatsuya Sawada
  • Patent number: 8703615
    Abstract: Disclosed are methods of depositing and annealing a copper seed layer. A copper seed layer may be deposited on a ruthenium layer disposed on a surface of a wafer and on features in the wafer. The thickness of the ruthenium layer may be about 40 Angstroms or less. The copper seed layer may be annealed in a reducing atmosphere having an oxygen concentration of about 2 parts per million or less. Annealing the copper seed layer in a low-oxygen atmosphere may improve the properties of the copper seed layer.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: April 22, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Thomas A. Ponnuswamy, John H. Sukamto, Jonathan D. Reid, Steven T. Mayer, Huanfeng Zhu
  • Patent number: 8669182
    Abstract: An interconnect structure is provided that has enhanced electromigration reliability without degrading circuit short yield, and improved technology extendibility. The inventive interconnect structure includes a dielectric material having a dielectric constant of about 3.0 or less. The dielectric material has at least one conductive material embedded therein. A noble metal cap is located directly on an upper surface of the at least one conductive region. The noble metal cap does not substantially extend onto an upper surface of the dielectric material that is adjacent to the at least one conductive region, and the noble cap material does not be deposited on the dielectric surface. A method fabricating such an interconnect structure utilizing a low temperature (about 300° C. or less) chemical deposition process is also provided.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: March 11, 2014
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Daniel C. Edelstein
  • Publication number: 20140061914
    Abstract: A method of forming a metal interconnect structure includes forming a copper line within an interlevel dielectric (ILD) layer; directly doping a top surface of the copper line with a copper alloy material; and forming a dielectric layer over the ILD layer and the copper alloy material; wherein the copper alloy material serves an adhesion interface layer between the copper line and the dielectric layer.
    Type: Application
    Filed: August 30, 2012
    Publication date: March 6, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas W. Dyer, Daniel C. Edelstein, Tze-man Ko, Andrew H. Simon, Wei-tsu Tseng
  • Publication number: 20140061915
    Abstract: A method of forming an integrated circuit device includes forming a diffusion barrier layer in an opening defined in a substrate; forming a highly doped copper alloy seed layer over the diffusion barrier layer, the copper alloy seed layer having a minority alloy component having a concentration greater than 0.5% atomic; and forming a copper layer over the copper alloy seed layer so as to define a wiring structure of the integrated circuit device.
    Type: Application
    Filed: August 30, 2012
    Publication date: March 6, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Christopher N. Collins, Daniel C. Edelstein, Mukta G. Farooq, Troy L. Graves-Abe, Andrew H. Simon, Richard P. Volant
  • Patent number: 8653664
    Abstract: A copper interconnect includes a copper layer formed in a dielectric layer, having a first portion and a second portion. A first barrier layer is formed between the first portion of the copper layer and the dielectric layer. A second barrier layer is formed at the boundary between the second portion of the copper layer and the dielectric layer. The first barrier layer is a dielectric layer, and the second barrier layer is a metal oxide layer.
    Type: Grant
    Filed: July 8, 2010
    Date of Patent: February 18, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Nai-Wei Liu, Zhen-Cheng Wu, Cheng-Lin Huang, Po-Hsiang Huang, Yung-Chih Wang, Shu-Hui Su, Dian-Hau Chen, Yuh-Jier Mii
  • Patent number: 8653663
    Abstract: A copper interconnect includes a copper layer formed in a dielectric layer. A glue layer is formed between the copper layer and the dielectric layer. A barrier layer is formed at the boundary between the glue layer and the dielectric layer. The barrier layer is a metal oxide.
    Type: Grant
    Filed: April 9, 2010
    Date of Patent: February 18, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Kuang Kao, Huei-Wen Yang, Yung-Sheng Huang, Yu-Wen Lin
  • Publication number: 20140027910
    Abstract: A method for forming an interconnect structure includes forming a recess in a dielectric layer of a substrate, forming a first transition metal layer in the recess on corner portions of the recess, and forming a second transition metal layer in the recess over the first transition metal layer to line the recess. The method further includes filling the recess with a fill layer and annealing the substrate so that the first transition metal layer and the second transition metal layer form an alloy portion proximate the corner portions during the annealing, the alloy portion having a reduced wettability for a material of the fill layer than the second transition metal. Additionally, the method includes polishing the substrate to remove portions of the fill layer extending above the recess.
    Type: Application
    Filed: July 30, 2012
    Publication date: January 30, 2014
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Xunyuan Zhang, Hoon Kim, Vivian W. Ryan
  • Publication number: 20140021616
    Abstract: A semiconductor structure is provided and includes a substrate having an edge surface and a device surface with a central area, a crack stop structure disposed on the device surface and a circuit structure including components disposed on the device surface in the central area and interconnects electrically coupled to the components. The interconnects are configured to extend from the central area to the edge surface while bridging over the crack stop structure.
    Type: Application
    Filed: July 19, 2012
    Publication date: January 23, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Diego Anzola, Evan G. Colgan, Kevin K. Dezfulian, Daniel C. Edelstein, Mark C. H. Lamorey, Sampath Purushothaman, Thomas M. Shaw, Roy R. Yu
  • Publication number: 20140021613
    Abstract: A method for forming an interconnect structure includes forming a recess in a dielectric layer of a substrate. An adhesion barrier layer is formed to line the recess. A first stress level is present across a first interface between the adhesion barrier layer and the dielectric layer. A stress-reducing barrier layer is formed over the adhesion barrier layer. The stress-reducing barrier layer reduces the first stress level to provide a second stress level, less than the first stress level, across a second interface between the adhesion barrier layer, the stress-reducing barrier layer, and the dielectric layer. The recess is filled with a fill layer.
    Type: Application
    Filed: July 20, 2012
    Publication date: January 23, 2014
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Vivian W. Ryan, Xunyuan Zhang, Paul R. Besser
  • Publication number: 20130320544
    Abstract: A method of producing reduced corrosion interconnect structures and structures thereby formed. A method of producing microelectronic interconnects having reduced corrosion begins with a damascene structure having a first dielectric and a first interconnect. A metal oxide layer is deposited selectively to metal or nonselective over the damascene structure and then thermally treated. The treatment converts the metal oxide over the first dielectric to a metal silicate while the metal oxide over the first interconnect remains as a self-aligned protective layer. When a subsequent dielectric stack is formed and patterned, the protective layer acts as an etch stop, oxidation barrier and ion bombardment protector. The protective layer is then removed from the patterned opening and a second interconnect formed. In a preferred embodiment the metal oxide is a manganese oxide and the metal silicate is a MnSiCOH, the interconnects are substantially copper and the dielectric contains ultra low-k.
    Type: Application
    Filed: May 29, 2012
    Publication date: December 5, 2013
    Applicant: International Business Machines Corporation
    Inventors: Wei Lin, Son Nguyen, Vamsi Paruchuri, Tuan A. Vo
  • Patent number: 8575029
    Abstract: By moderately introducing defects into a highly conductive material, such as copper, the resistance versus temperature behavior may be significantly modified so that enhanced electromigration behavior and/or electrical performance may be obtained in metallization structures of advanced semiconductor devices. The defect-related portion of the resistance may be moderately increased so as to change the slope of the resistance versus temperature curve, thereby allowing the incorporation of impurity atoms for enhancing the electromigration endurance while not unduly increasing the overall resistance at the operating temperature or even reducing the corresponding resistance at the specified operating temperature. Thus, by appropriately designing the electrical resistance for a target operating temperature, both the electromigration behavior and the electrical performance may be enhanced.
    Type: Grant
    Filed: October 13, 2011
    Date of Patent: November 5, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Moritz Andreas Meyer, Matthias Lehr, Eckhard Langer
  • Publication number: 20130277842
    Abstract: A structure having a diffusion barrier positioned adjacent to a sidewall and a bottom of an opening being etched in a layer of dielectric material. The structure also having a metal liner positioned directly on top of the diffusion barrier, a seed layer positioned directly on top of the metal liner, wherein the seed layer is made from a material comprising copper, a copper material positioned directly on top of the seed layer, a metallic cap positioned directly on top of and selective to the copper material, and a capping layer positioned directly on top of and adjacent to the metallic cap.
    Type: Application
    Filed: April 20, 2012
    Publication date: October 24, 2013
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC., RENESAS ELECTRONICS CORPORATION, STMICROELECTRONICS, INC.
    Inventors: Frieder Hainrich Baumann, Chao-Kun Hu, Andrew H. Simon, Tibor Bolom, Koichi Motoyama, Chengyu Charles Niu
  • Patent number: 8552559
    Abstract: A new interconnection scheme is described, comprising both coarse and fine line interconnection schemes in an IC chip. The coarse metal interconnection, typically formed by selective electroplating technology, is located on top of the fine line interconnection scheme. It is especially useful for long distance lines, clock, power and ground buses, and other applications such as high Q inductors and bypass lines. The fine line interconnections are more appropriate to be used for local interconnections. The combined structure of coarse and fine line interconnections forms a new interconnection scheme that not only enhances IC speed, but also lowers power consumption.
    Type: Grant
    Filed: March 23, 2005
    Date of Patent: October 8, 2013
    Assignee: Megica Corporation
    Inventors: Mou-Shiung Lin, Chiu-Ming Chou, Chien-Kang Chou
  • Publication number: 20130256891
    Abstract: A semiconductor device with a copper line comprises a lower portion of a copper pattern buried in an interlayer insulating film, an upper portion of the copper disposed over the upper portion of the lower copper pattern, and an upper barrier metal layer disposed over upper and side surfaces of the upper copper pattern. As a result, the copper pattern is protected by the barrier metal layers, providing a metal line with a stable structure.
    Type: Application
    Filed: September 7, 2012
    Publication date: October 3, 2013
    Applicant: SK Hynix Inc.
    Inventor: Hyung Jin PARK
  • Patent number: 8536706
    Abstract: A method for fabricating a semiconductor device, includes forming a dielectric film above a substrate; forming an opening in the dielectric film; forming a first film containing a metal whose energy for forming silicide thereof is lower than that of Cu silicide inside the opening; forming a second film that is conductive and contains copper (Cu) in the opening in which the first film containing the metal is formed; and forming a compound film containing Cu and silicon (Si) selectively on the second film in an atmosphere in which a temperature of the substrate is below 300° C.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: September 17, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yumi Hayashi, Atsuko Sakata, Kei Watanabe, Noriaki Matsunaga, Shinichi Nakao, Makoto Wada, Hiroshi Toyoda
  • Publication number: 20130214414
    Abstract: Interconnect structures and methods of manufacturing the same are disclosed herein. The method includes forming a barrier layer within a structure and forming an alloy metal on the barrier layer. The method further includes forming a pure metal on the alloy metal, and reflowing the pure metal such that the pure metal migrates to a bottom of the structure, while the alloy metal prevents exposure of the barrier layer. The method further includes completely filling in the structure with additional metal.
    Type: Application
    Filed: February 21, 2012
    Publication date: August 22, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Daniel C. EDELSTEIN, Takeshi NOGAMI
  • Patent number: 8513124
    Abstract: Disclosed are methods of depositing a copper seed layer to be used for subsequent electroplating a bulk-layer of copper thereon. A copper seed layer may be deposited with different processes, including CVD, PVD, and electroplating. With electroplating methods for depositing a copper seed layer, disclosed are methods for depositing a copper alloy seed layer, methods for depositing a copper seed layer on the semi-noble metal layer with a non-corrosive electrolyte, methods of treating the semi-noble metal layer that the copper seed layer is deposited on, and methods for promoting a more uniform copper seed layer deposition across a semiconductor wafer.
    Type: Grant
    Filed: May 21, 2010
    Date of Patent: August 20, 2013
    Assignee: Novellus Systems, Inc.
    Inventors: Thomas A. Ponnuswamy, John H. Sukamto, Jonathan D. Reid, Steven T. Mayer
  • Patent number: 8513805
    Abstract: A technology that improves the reliability of a semiconductor device and realizes a high performance by a laminated structure that has enough barrier properties against copper, reduces the wire delay time by lowering the capacitance between wirings and improves the adhesion between wirings is provided. There is a semiconductor device having: a first copper wiring layer, a first barrier layer on the first copper wiring layer, a silicon oxide series porous insulating layer on the first barrier layer, a second barrier layer on the silicon oxide series porous insulating layer, and a second copper wiring layer on the second barrier layer, wherein at least one of the first barrier layer and the second barrier layer consists of an amorphous carbon film, wherein a silicon series insulating layer is directly connected between the amorphous carbon film and any of the first copper wiring layer or the second copper wiring layer.
    Type: Grant
    Filed: February 27, 2008
    Date of Patent: August 20, 2013
    Assignee: Fujitsu Limited
    Inventor: Tsukasa Itani
  • Publication number: 20130187273
    Abstract: Semiconductor devices having copper interconnects and methods for their fabrication are provided. In one embodiment, a semiconductor device is fabricated with a copper interconnect on substrate such as an FEOL processed substrate. The method includes forming a copper layer on a substrate. The copper layer is formed from grains. The copper layer is modified such that the modified copper layer has an average grain size of larger than about 0.05 microns. In the method, the modified copper layer is etched to form a line along the substrate and a via extending upwards from the line.
    Type: Application
    Filed: January 19, 2012
    Publication date: July 25, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Xunyuan Zhang, Hoon Kim
  • Publication number: 20130168860
    Abstract: There are disclosed herein various implementations of semiconductor packages including an interposer without through-semiconductor vias (TSVs). One exemplary implementation includes a first active die situated over an interposer. The interposer includes an interposer dielectric having intra-interposer routing traces. The first active die communicates electrical signals to a package substrate situated below the interposer utilizing the intra-interposer routing traces and without utilizing TSVs. In one implementation, the semiconductor package includes a second active die situated over the interposer, the second active die communicating electrical signals to the package substrate utilizing the intra-interposer routing traces and without utilizing TSVs. Moreover, in one implementation, the first active die and the second active die communicate chip-to-chip signals through the interposer.
    Type: Application
    Filed: December 28, 2011
    Publication date: July 4, 2013
    Applicant: BROADCOM CORPORATION
    Inventors: Sampath K.V. Karikalan, Sam Ziqun Zhao, Kevin Kunzhong Hu, Rezaur Rahman Khan, Pieter Vorenkamp, Xiangdong Chen
  • Publication number: 20130154096
    Abstract: In a manufacturing method of a barrier layer, a via hole is formed in an insulating layer that covers a conductive layer over a substrate, and then the barrier layer is formed in the via hole. The barrier layer is provided by forming a second titanium nitride film after forming a first titanium nitride film. The second titanium nitride film is formed using a method having a weak anisotropy than the first titanium nitride film.
    Type: Application
    Filed: November 6, 2012
    Publication date: June 20, 2013
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Elpida Memory, Inc.
  • Patent number: 8466553
    Abstract: The present invention relates to a semiconductor device and a semiconductor package having the same. The semiconductor device includes a conductive element. The conductive element is disposed on a protruded conductive via and liner, and covers a sidewall of the liner. Whereby, the conductive element can protect the protruded conductive via and liner from being damaged. Further, the size of the conductive element is large, thus it is easy to perform a probe test process.
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: June 18, 2013
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Bing-Hong Cheng, Meng-Jen Wang
  • Patent number: 8466556
    Abstract: In a method of forming a wiring structure for a semiconductor device, an insulation layer is formed on a semiconductor substrate on which a plurality of conductive structures is positioned. An upper surface of the insulation layer is planarized and spaces between the conductive structures are filled with the insulation layer. The insulation layer is partially removed from the substrate to form at least one opening through which the substrate is partially exposed. A residual metal layer is formed on a bottom and a lower portion of the sidewall of the at least one opening and a metal nitride layer is formed on the residual metal layer and an upper sidewall of the opening with a metal material. Accordingly, an upper portion of the barrier layer can be prevented from being removed in a planarization process for forming the metal plug.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: June 18, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Ho Park, Gil-Heyun Choi, Sang-Woo Lee, Ho-Ki Lee
  • Patent number: 8440563
    Abstract: Provided is a film-forming method for performing a film-forming process on a surface of a target substrate to be processed in an evacuable processing chamber, a recessed portion being formed on the surface of the target substrate. The method includes a transition metal-containing film processing process in which a transition metal-containing film is formed by a heat treatment by using a source gas containing a transition metal; and a metal film forming process in which a metal film containing an element of the group VIII of the periodic table is formed.
    Type: Grant
    Filed: January 10, 2011
    Date of Patent: May 14, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Kenji Matsumoto, Yasushi Mizusawa
  • Publication number: 20130113103
    Abstract: An integrated circuit (IC) includes a substrate having a topside semiconductor surface including active circuitry configured to provide functionality and a bottomside surface. A plurality of through substrate vias (TSVs) extend from the topside semiconductor surface to beyond the bottomside surface to provide protruding TSV tips. The TSVs include an outer dielectric liner, a metal comprising diffusion barrier layer on the dielectric liner, and a metal filler on the metal comprising barrier layer. A dielectric metal gettering layer (MGL) is on the bottomside surface lateral to and on sidewalls of the protruding TSV tips. The MGL includes at least one metal gettering agent selected from a halogen or a Group 15 element in an average concentration from 0.1 to 10 atomic %.
    Type: Application
    Filed: June 5, 2012
    Publication date: May 9, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: JEFFREY A. WEST, RAJESH TIWARI
  • Publication number: 20130062770
    Abstract: One or more embodiments relate to a semiconductor structure, comprising: a barrier layer overlying a workpiece surface; a seed layer overlying the barrier layer; an inhibitor layer overlying said seed layer, the inhibitor layer having a opening exposing a portion of the seed layer, and a fill layer overlying the exposed portion of the seed layer.
    Type: Application
    Filed: November 8, 2012
    Publication date: March 14, 2013
    Inventor: Infineon Technologies AG
  • Patent number: 8384217
    Abstract: By forming an aluminum nitride layer by a self-limiting process sequence, the interface characteristics of a copper-based metallization layer may be significantly enhanced while nevertheless maintaining the overall permittivity of the layer stack at a lower level.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: February 26, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Christof Streck, Volker Kahlert
  • Patent number: 8384189
    Abstract: The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting discrete electrical components at a significant distance removed from the underlying silicon surface.
    Type: Grant
    Filed: August 6, 2008
    Date of Patent: February 26, 2013
    Assignee: Megica Corporation
    Inventor: Mou-Shing Lin
  • Publication number: 20130043589
    Abstract: Disclosed herein are various methods of forming methods of forming a non-planar cap layer above a conductive line on a semiconductor device, and to devices incorporating such a non-planar cap layer. In one illustrative example, the method includes forming a conductive structure in a layer of insulating material, recessing an upper surface of the conductive structure relative to an upper surface of the layer of insulating material such that the recessed upper surface of the conductive structure and the upper surface of the layer of insulating material are positioned in different planes and, after recessing the upper surface of the conductive structure, forming a first cap layer on the conductive structure and the layer of insulating material.
    Type: Application
    Filed: August 16, 2011
    Publication date: February 21, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Ryoung-Han Kim, Errol Todd Ryan